Code Coverage

Source file: /home/nikola/llvm_builds/llvm-clang-coverage-build/lib/Target/Mips/MipsGenRegisterInfo.inc

Summary Report

Line number	Line	Number of hits	Tests that cover line
1	/===- TableGen'erated file -------------------------------------- C++ --===\	----
2	\|* *\|	----
3	\|* Target Register Enum Values *\|	----
4	\|* *\|	----
5	\|* Automatically generated file, do not edit! *\|	----
6	\|* *\|	----
7	\===----------------------------------------------------------------------===/	----
8		----
9		----
10	#ifdef GET_REGINFO_ENUM	----
11	#undef GET_REGINFO_ENUM	----
12		----
13	namespace llvm {	----
14		----
15	class MCRegisterClass;	----
16	extern const MCRegisterClass MipsMCRegisterClasses[];	----
17		----
18	namespace Mips {	----
19	enum {	----
20	NoRegister,	----
21	AT = 1,	----
22	DSPCCond = 2,	----
23	DSPCarry = 3,	----
24	DSPEFI = 4,	----
25	DSPOutFlag = 5,	----
26	DSPPos = 6,	----
27	DSPSCount = 7,	----
28	FP = 8,	----
29	GP = 9,	----
30	MSAAccess = 10,	----
31	MSACSR = 11,	----
32	MSAIR = 12,	----
33	MSAMap = 13,	----
34	MSAModify = 14,	----
35	MSARequest = 15,	----
36	MSASave = 16,	----
37	MSAUnmap = 17,	----
38	PC = 18,	----
39	RA = 19,	----
40	SP = 20,	----
41	ZERO = 21,	----
42	A0 = 22,	----
43	A1 = 23,	----
44	A2 = 24,	----
45	A3 = 25,	----
46	AC0 = 26,	----
47	AC1 = 27,	----
48	AC2 = 28,	----
49	AC3 = 29,	----
50	AT_64 = 30,	----
51	COP00 = 31,	----
52	COP01 = 32,	----
53	COP02 = 33,	----
54	COP03 = 34,	----
55	COP04 = 35,	----
56	COP05 = 36,	----
57	COP06 = 37,	----
58	COP07 = 38,	----
59	COP08 = 39,	----
60	COP09 = 40,	----
61	COP20 = 41,	----
62	COP21 = 42,	----
63	COP22 = 43,	----
64	COP23 = 44,	----
65	COP24 = 45,	----
66	COP25 = 46,	----
67	COP26 = 47,	----
68	COP27 = 48,	----
69	COP28 = 49,	----
70	COP29 = 50,	----
71	COP30 = 51,	----
72	COP31 = 52,	----
73	COP32 = 53,	----
74	COP33 = 54,	----
75	COP34 = 55,	----
76	COP35 = 56,	----
77	COP36 = 57,	----
78	COP37 = 58,	----
79	COP38 = 59,	----
80	COP39 = 60,	----
81	COP010 = 61,	----
82	COP011 = 62,	----
83	COP012 = 63,	----
84	COP013 = 64,	----
85	COP014 = 65,	----
86	COP015 = 66,	----
87	COP016 = 67,	----
88	COP017 = 68,	----
89	COP018 = 69,	----
90	COP019 = 70,	----
91	COP020 = 71,	----
92	COP021 = 72,	----
93	COP022 = 73,	----
94	COP023 = 74,	----
95	COP024 = 75,	----
96	COP025 = 76,	----
97	COP026 = 77,	----
98	COP027 = 78,	----
99	COP028 = 79,	----
100	COP029 = 80,	----
101	COP030 = 81,	----
102	COP031 = 82,	----
103	COP210 = 83,	----
104	COP211 = 84,	----
105	COP212 = 85,	----
106	COP213 = 86,	----
107	COP214 = 87,	----
108	COP215 = 88,	----
109	COP216 = 89,	----
110	COP217 = 90,	----
111	COP218 = 91,	----
112	COP219 = 92,	----
113	COP220 = 93,	----
114	COP221 = 94,	----
115	COP222 = 95,	----
116	COP223 = 96,	----
117	COP224 = 97,	----
118	COP225 = 98,	----
119	COP226 = 99,	----
120	COP227 = 100,	----
121	COP228 = 101,	----
122	COP229 = 102,	----
123	COP230 = 103,	----
124	COP231 = 104,	----
125	COP310 = 105,	----
126	COP311 = 106,	----
127	COP312 = 107,	----
128	COP313 = 108,	----
129	COP314 = 109,	----
130	COP315 = 110,	----
131	COP316 = 111,	----
132	COP317 = 112,	----
133	COP318 = 113,	----
134	COP319 = 114,	----
135	COP320 = 115,	----
136	COP321 = 116,	----
137	COP322 = 117,	----
138	COP323 = 118,	----
139	COP324 = 119,	----
140	COP325 = 120,	----
141	COP326 = 121,	----
142	COP327 = 122,	----
143	COP328 = 123,	----
144	COP329 = 124,	----
145	COP330 = 125,	----
146	COP331 = 126,	----
147	D0 = 127,	----
148	D1 = 128,	----
149	D2 = 129,	----
150	D3 = 130,	----
151	D4 = 131,	----
152	D5 = 132,	----
153	D6 = 133,	----
154	D7 = 134,	----
155	D8 = 135,	----
156	D9 = 136,	----
157	D10 = 137,	----
158	D11 = 138,	----
159	D12 = 139,	----
160	D13 = 140,	----
161	D14 = 141,	----
162	D15 = 142,	----
163	DSPOutFlag20 = 143,	----
164	DSPOutFlag21 = 144,	----
165	DSPOutFlag22 = 145,	----
166	DSPOutFlag23 = 146,	----
167	F0 = 147,	----
168	F1 = 148,	----
169	F2 = 149,	----
170	F3 = 150,	----
171	F4 = 151,	----
172	F5 = 152,	----
173	F6 = 153,	----
174	F7 = 154,	----
175	F8 = 155,	----
176	F9 = 156,	----
177	F10 = 157,	----
178	F11 = 158,	----
179	F12 = 159,	----
180	F13 = 160,	----
181	F14 = 161,	----
182	F15 = 162,	----
183	F16 = 163,	----
184	F17 = 164,	----
185	F18 = 165,	----
186	F19 = 166,	----
187	F20 = 167,	----
188	F21 = 168,	----
189	F22 = 169,	----
190	F23 = 170,	----
191	F24 = 171,	----
192	F25 = 172,	----
193	F26 = 173,	----
194	F27 = 174,	----
195	F28 = 175,	----
196	F29 = 176,	----
197	F30 = 177,	----
198	F31 = 178,	----
199	FCC0 = 179,	----
200	FCC1 = 180,	----
201	FCC2 = 181,	----
202	FCC3 = 182,	----
203	FCC4 = 183,	----
204	FCC5 = 184,	----
205	FCC6 = 185,	----
206	FCC7 = 186,	----
207	FCR0 = 187,	----
208	FCR1 = 188,	----
209	FCR2 = 189,	----
210	FCR3 = 190,	----
211	FCR4 = 191,	----
212	FCR5 = 192,	----
213	FCR6 = 193,	----
214	FCR7 = 194,	----
215	FCR8 = 195,	----
216	FCR9 = 196,	----
217	FCR10 = 197,	----
218	FCR11 = 198,	----
219	FCR12 = 199,	----
220	FCR13 = 200,	----
221	FCR14 = 201,	----
222	FCR15 = 202,	----
223	FCR16 = 203,	----
224	FCR17 = 204,	----
225	FCR18 = 205,	----
226	FCR19 = 206,	----
227	FCR20 = 207,	----
228	FCR21 = 208,	----
229	FCR22 = 209,	----
230	FCR23 = 210,	----
231	FCR24 = 211,	----
232	FCR25 = 212,	----
233	FCR26 = 213,	----
234	FCR27 = 214,	----
235	FCR28 = 215,	----
236	FCR29 = 216,	----
237	FCR30 = 217,	----
238	FCR31 = 218,	----
239	FP_64 = 219,	----
240	F_HI0 = 220,	----
241	F_HI1 = 221,	----
242	F_HI2 = 222,	----
243	F_HI3 = 223,	----
244	F_HI4 = 224,	----
245	F_HI5 = 225,	----
246	F_HI6 = 226,	----
247	F_HI7 = 227,	----
248	F_HI8 = 228,	----
249	F_HI9 = 229,	----
250	F_HI10 = 230,	----
251	F_HI11 = 231,	----
252	F_HI12 = 232,	----
253	F_HI13 = 233,	----
254	F_HI14 = 234,	----
255	F_HI15 = 235,	----
256	F_HI16 = 236,	----
257	F_HI17 = 237,	----
258	F_HI18 = 238,	----
259	F_HI19 = 239,	----
260	F_HI20 = 240,	----
261	F_HI21 = 241,	----
262	F_HI22 = 242,	----
263	F_HI23 = 243,	----
264	F_HI24 = 244,	----
265	F_HI25 = 245,	----
266	F_HI26 = 246,	----
267	F_HI27 = 247,	----
268	F_HI28 = 248,	----
269	F_HI29 = 249,	----
270	F_HI30 = 250,	----
271	F_HI31 = 251,	----
272	GP_64 = 252,	----
273	HI0 = 253,	----
274	HI1 = 254,	----
275	HI2 = 255,	----
276	HI3 = 256,	----
277	HWR0 = 257,	----
278	HWR1 = 258,	----
279	HWR2 = 259,	----
280	HWR3 = 260,	----
281	HWR4 = 261,	----
282	HWR5 = 262,	----
283	HWR6 = 263,	----
284	HWR7 = 264,	----
285	HWR8 = 265,	----
286	HWR9 = 266,	----
287	HWR10 = 267,	----
288	HWR11 = 268,	----
289	HWR12 = 269,	----
290	HWR13 = 270,	----
291	HWR14 = 271,	----
292	HWR15 = 272,	----
293	HWR16 = 273,	----
294	HWR17 = 274,	----
295	HWR18 = 275,	----
296	HWR19 = 276,	----
297	HWR20 = 277,	----
298	HWR21 = 278,	----
299	HWR22 = 279,	----
300	HWR23 = 280,	----
301	HWR24 = 281,	----
302	HWR25 = 282,	----
303	HWR26 = 283,	----
304	HWR27 = 284,	----
305	HWR28 = 285,	----
306	HWR29 = 286,	----
307	HWR30 = 287,	----
308	HWR31 = 288,	----
309	K0 = 289,	----
310	K1 = 290,	----
311	LO0 = 291,	----
312	LO1 = 292,	----
313	LO2 = 293,	----
314	LO3 = 294,	----
315	MPL0 = 295,	----
316	MPL1 = 296,	----
317	MPL2 = 297,	----
318	MSA8 = 298,	----
319	MSA9 = 299,	----
320	MSA10 = 300,	----
321	MSA11 = 301,	----
322	MSA12 = 302,	----
323	MSA13 = 303,	----
324	MSA14 = 304,	----
325	MSA15 = 305,	----
326	MSA16 = 306,	----
327	MSA17 = 307,	----
328	MSA18 = 308,	----
329	MSA19 = 309,	----
330	MSA20 = 310,	----
331	MSA21 = 311,	----
332	MSA22 = 312,	----
333	MSA23 = 313,	----
334	MSA24 = 314,	----
335	MSA25 = 315,	----
336	MSA26 = 316,	----
337	MSA27 = 317,	----
338	MSA28 = 318,	----
339	MSA29 = 319,	----
340	MSA30 = 320,	----
341	MSA31 = 321,	----
342	P0 = 322,	----
343	P1 = 323,	----
344	P2 = 324,	----
345	RA_64 = 325,	----
346	S0 = 326,	----
347	S1 = 327,	----
348	S2 = 328,	----
349	S3 = 329,	----
350	S4 = 330,	----
351	S5 = 331,	----
352	S6 = 332,	----
353	S7 = 333,	----
354	SP_64 = 334,	----
355	T0 = 335,	----
356	T1 = 336,	----
357	T2 = 337,	----
358	T3 = 338,	----
359	T4 = 339,	----
360	T5 = 340,	----
361	T6 = 341,	----
362	T7 = 342,	----
363	T8 = 343,	----
364	T9 = 344,	----
365	V0 = 345,	----
366	V1 = 346,	----
367	W0 = 347,	----
368	W1 = 348,	----
369	W2 = 349,	----
370	W3 = 350,	----
371	W4 = 351,	----
372	W5 = 352,	----
373	W6 = 353,	----
374	W7 = 354,	----
375	W8 = 355,	----
376	W9 = 356,	----
377	W10 = 357,	----
378	W11 = 358,	----
379	W12 = 359,	----
380	W13 = 360,	----
381	W14 = 361,	----
382	W15 = 362,	----
383	W16 = 363,	----
384	W17 = 364,	----
385	W18 = 365,	----
386	W19 = 366,	----
387	W20 = 367,	----
388	W21 = 368,	----
389	W22 = 369,	----
390	W23 = 370,	----
391	W24 = 371,	----
392	W25 = 372,	----
393	W26 = 373,	----
394	W27 = 374,	----
395	W28 = 375,	----
396	W29 = 376,	----
397	W30 = 377,	----
398	W31 = 378,	----
399	ZERO_64 = 379,	----
400	A0_64 = 380,	----
401	A1_64 = 381,	----
402	A2_64 = 382,	----
403	A3_64 = 383,	----
404	AC0_64 = 384,	----
405	D0_64 = 385,	----
406	D1_64 = 386,	----
407	D2_64 = 387,	----
408	D3_64 = 388,	----
409	D4_64 = 389,	----
410	D5_64 = 390,	----
411	D6_64 = 391,	----
412	D7_64 = 392,	----
413	D8_64 = 393,	----
414	D9_64 = 394,	----
415	D10_64 = 395,	----
416	D11_64 = 396,	----
417	D12_64 = 397,	----
418	D13_64 = 398,	----
419	D14_64 = 399,	----
420	D15_64 = 400,	----
421	D16_64 = 401,	----
422	D17_64 = 402,	----
423	D18_64 = 403,	----
424	D19_64 = 404,	----
425	D20_64 = 405,	----
426	D21_64 = 406,	----
427	D22_64 = 407,	----
428	D23_64 = 408,	----
429	D24_64 = 409,	----
430	D25_64 = 410,	----
431	D26_64 = 411,	----
432	D27_64 = 412,	----
433	D28_64 = 413,	----
434	D29_64 = 414,	----
435	D30_64 = 415,	----
436	D31_64 = 416,	----
437	DSPOutFlag16_19 = 417,	----
438	HI0_64 = 418,	----
439	K0_64 = 419,	----
440	K1_64 = 420,	----
441	LO0_64 = 421,	----
442	S0_64 = 422,	----
443	S1_64 = 423,	----
444	S2_64 = 424,	----
445	S3_64 = 425,	----
446	S4_64 = 426,	----
447	S5_64 = 427,	----
448	S6_64 = 428,	----
449	S7_64 = 429,	----
450	T0_64 = 430,	----
451	T1_64 = 431,	----
452	T2_64 = 432,	----
453	T3_64 = 433,	----
454	T4_64 = 434,	----
455	T5_64 = 435,	----
456	T6_64 = 436,	----
457	T7_64 = 437,	----
458	T8_64 = 438,	----
459	T9_64 = 439,	----
460	V0_64 = 440,	----
461	V1_64 = 441,	----
462	NUM_TARGET_REGS // 442	----
463	};	----
464	} // end namespace Mips	----
465		----
466	// Register classes	----
467		----
468	namespace Mips {	----
469	enum {	----
470	MSA128F16RegClassID = 0,	----
471	CCRRegClassID = 1,	----
472	COP0RegClassID = 2,	----
473	COP2RegClassID = 3,	----
474	COP3RegClassID = 4,	----
475	DSPRRegClassID = 5,	----
476	FGR32RegClassID = 6,	----
477	FGRCCRegClassID = 7,	----
478	GPR32RegClassID = 8,	----
479	HWRegsRegClassID = 9,	----
480	MSACtrlRegClassID = 10,	----
481	GPR32NONZERORegClassID = 11,	----
482	CPU16RegsPlusSPRegClassID = 12,	----
483	CPU16RegsRegClassID = 13,	----
484	FCCRegClassID = 14,	----
485	GPRMM16RegClassID = 15,	----
486	GPRMM16MovePRegClassID = 16,	----
487	GPRMM16ZeroRegClassID = 17,	----
488	CPU16Regs_and_GPRMM16ZeroRegClassID = 18,	----
489	GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,	----
490	GPRMM16MovePPairSecondRegClassID = 20,	----
491	CPU16Regs_and_GPRMM16MovePRegClassID = 21,	----
492	GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,	----
493	HI32DSPRegClassID = 23,	----
494	LO32DSPRegClassID = 24,	----
495	CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,	----
496	GPRMM16MovePPairFirstRegClassID = 26,	----
497	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,	----
498	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,	----
499	CPURARegRegClassID = 29,	----
500	CPUSPRegRegClassID = 30,	----
501	DSPCCRegClassID = 31,	----
502	GP32RegClassID = 32,	----
503	GPR32ZERORegClassID = 33,	----
504	HI32RegClassID = 34,	----
505	LO32RegClassID = 35,	----
506	SP32RegClassID = 36,	----
507	FGR64RegClassID = 37,	----
508	GPR64RegClassID = 38,	----
509	GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,	----
510	AFGR64RegClassID = 40,	----
511	GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,	----
512	GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,	----
513	GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,	----
514	GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,	----
515	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,	----
516	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,	----
517	GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,	----
518	ACC64DSPRegClassID = 48,	----
519	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,	----
520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,	----
521	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,	----
522	GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,	----
523	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,	----
524	OCTEON_MPLRegClassID = 54,	----
525	OCTEON_PRegClassID = 55,	----
526	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,	----
527	ACC64RegClassID = 57,	----
528	GP64RegClassID = 58,	----
529	GPR64_with_sub_32_in_CPURARegRegClassID = 59,	----
530	GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,	----
531	HI64RegClassID = 61,	----
532	LO64RegClassID = 62,	----
533	SP64RegClassID = 63,	----
534	MSA128BRegClassID = 64,	----
535	MSA128DRegClassID = 65,	----
536	MSA128HRegClassID = 66,	----
537	MSA128WRegClassID = 67,	----
538	MSA128WEvensRegClassID = 68,	----
539	ACC128RegClassID = 69,	----
540		----
541	};	----
542	} // end namespace Mips	----
543		----
544		----
545	// Subregister indices	----
546		----
547	namespace Mips {	----
548	enum : uint16_t {	----
549	NoSubRegister,	----
550	sub_32, // 1	----
551	sub_64, // 2	----
552	sub_dsp16_19, // 3	----
553	sub_dsp20, // 4	----
554	sub_dsp21, // 5	----
555	sub_dsp22, // 6	----
556	sub_dsp23, // 7	----
557	sub_hi, // 8	----
558	sub_lo, // 9	----
559	sub_hi_then_sub_32, // 10	----
560	sub_32_sub_hi_then_sub_32, // 11	----
561	NUM_TARGET_SUBREGS	----
562	};	----
563	} // end namespace Mips	----
564		----
565	// Register pressure sets enum.	----
566	namespace Mips {	----
567	enum RegisterPressureSets {	----
568	DSPCC = 0,	----
569	GPR32ZERO = 1,	----
570	GPR64_with_sub_32_in_CPURAReg = 2,	----
571	HI32 = 3,	----
572	GPRMM16MovePPairFirst = 4,	----
573	CPU16Regs_and_GPRMM16MoveP = 5,	----
574	HI32DSP = 6,	----
575	LO32DSP = 7,	----
576	GPRMM16MovePPairSecond = 8,	----
577	GPRMM16MoveP = 9,	----
578	ACC64DSP = 10,	----
579	CPU16Regs = 11,	----
580	GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,	----
581	CPU16Regs_with_GPRMM16MovePPairSecond = 13,	----
582	CPU16Regs_with_GPRMM16MoveP = 14,	----
583	DSPR = 15,	----
584	FGR32 = 16,	----
585	MSA128WEvens = 17,	----
586	FGR32_with_MSA128WEvens = 18,	----
587	MSA128F16 = 19,	----
588	};	----
589	} // end namespace Mips	----
590		----
591	} // end namespace llvm	----
592		----
593	#endif // GET_REGINFO_ENUM	----
594		----
595	/===- TableGen'erated file -------------------------------------- C++ --===\	----
596	\|* *\|	----
597	\|* MC Register Information *\|	----
598	\|* *\|	----
599	\|* Automatically generated file, do not edit! *\|	----
600	\|* *\|	----
601	\===----------------------------------------------------------------------===/	----
602		----
603		----
604	#ifdef GET_REGINFO_MC_DESC	----
605	#undef GET_REGINFO_MC_DESC	----
606		----
607	namespace llvm {	----
608		----
609	extern const int16_t MipsRegDiffLists[] = {	----
610	/* 0 */ -412, 0,	----
611	/* 2 */ -358, 0,	----
612	/* 4 */ -314, 0,	----
613	/* 6 */ -306, 0,	----
614	/* 8 */ -265, 0,	----
615	/* 10 */ -243, 0,	----
616	/* 12 */ 37, -130, 127, -165, -227, 0,	----
617	/* 18 */ -211, 0,	----
618	/* 20 */ -165, 0,	----
619	/* 22 */ -141, 0,	----
620	/* 24 */ -140, 0,	----
621	/* 26 */ -139, 0,	----
622	/* 28 */ -138, 0,	----
623	/* 30 */ -130, 0,	----
624	/* 32 */ -96, 0,	----
625	/* 34 */ -95, 0,	----
626	/* 36 */ 165, -38, 0,	----
627	/* 39 */ -20, 258, -38, 0,	----
628	/* 43 */ -21, 259, -38, 0,	----
629	/* 47 */ -22, 260, -38, 0,	----
630	/* 51 */ -23, 261, -38, 0,	----
631	/* 55 */ -24, 262, -38, 0,	----
632	/* 59 */ -25, 263, -38, 0,	----
633	/* 63 */ -26, 264, -38, 0,	----
634	/* 67 */ -27, 265, -38, 0,	----
635	/* 71 */ -28, 266, -38, 0,	----
636	/* 75 */ -29, 267, -38, 0,	----
637	/* 79 */ -30, 268, -38, 0,	----
638	/* 83 */ -31, 269, -38, 0,	----
639	/* 87 */ -32, 270, -38, 0,	----
640	/* 91 */ -33, 271, -38, 0,	----
641	/* 95 */ -34, 272, -38, 0,	----
642	/* 99 */ -35, 273, -38, 0,	----
643	/* 103 */ -36, 274, -38, 0,	----
644	/* 107 */ -265, 395, -37, 0,	----
645	/* 111 */ -227, 392, -34, 0,	----
646	/* 115 */ -29, 0,	----
647	/* 117 */ 412, -274, 1, 1, 1, 0,	----
648	/* 123 */ 1, 1, 1, 1, 0,	----
649	/* 128 */ 20, 1, 0,	----
650	/* 131 */ 21, 1, 0,	----
651	/* 134 */ 22, 1, 0,	----
652	/* 137 */ 23, 1, 0,	----
653	/* 140 */ 24, 1, 0,	----
654	/* 143 */ 25, 1, 0,	----
655	/* 146 */ 26, 1, 0,	----
656	/* 149 */ 27, 1, 0,	----
657	/* 152 */ 28, 1, 0,	----
658	/* 155 */ 29, 1, 0,	----
659	/* 158 */ 30, 1, 0,	----
660	/* 161 */ 31, 1, 0,	----
661	/* 164 */ 32, 1, 0,	----
662	/* 167 */ 33, 1, 0,	----
663	/* 170 */ 34, 1, 0,	----
664	/* 173 */ 35, 1, 0,	----
665	/* 176 */ 29, 0,	----
666	/* 178 */ 72, 0,	----
667	/* 180 */ 38, -238, 73, 0,	----
668	/* 184 */ 95, 0,	----
669	/* 186 */ 96, 0,	----
670	/* 188 */ 130, 0,	----
671	/* 190 */ 211, 0,	----
672	/* 192 */ 243, 0,	----
673	/* 194 */ 306, 0,	----
674	/* 196 */ 314, 0,	----
675	/* 198 */ 358, 0,	----
676	};	----
677		----
678	extern const LaneBitmask MipsLaneMaskLists[] = {	----
679	/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),	----
680	/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),	----
681	/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),	----
682	/* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),	----
683	};	----
684		----
685	extern const uint16_t MipsSubRegIdxLists[] = {	----
686	/* 0 */ 1, 0,	----
687	/* 2 */ 3, 4, 5, 6, 7, 0,	----
688	/* 8 */ 2, 9, 8, 0,	----
689	/* 12 */ 9, 1, 8, 10, 11, 0,	----
690	};	----
691		----
692	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {	----
693	{ 65535, 65535 },	----
694	{ 0, 32 }, // sub_32	----
695	{ 0, 64 }, // sub_64	----
696	{ 16, 4 }, // sub_dsp16_19	----
697	{ 20, 1 }, // sub_dsp20	----
698	{ 21, 1 }, // sub_dsp21	----
699	{ 22, 1 }, // sub_dsp22	----
700	{ 23, 1 }, // sub_dsp23	----
701	{ 32, 32 }, // sub_hi	----
702	{ 0, 32 }, // sub_lo	----
703	{ 32, 32 }, // sub_hi_then_sub_32	----
704	{ 0, 64 }, // sub_32_sub_hi_then_sub_32	----
705	};	----
706		----
707		----
708	#ifdef __GNUC__	----
709	#pragma GCC diagnostic push	----
710	#pragma GCC diagnostic ignored "-Woverlength-strings"	----
711	#endif	----
712	extern const char MipsRegStrings[] = {	----
713	/* 0 */ "COP00\0"	----
714	/* 6 */ "COP010\0"	----
715	/* 13 */ "COP210\0"	----
716	/* 20 */ "COP310\0"	----
717	/* 27 */ "MSA10\0"	----
718	/* 33 */ "D10\0"	----
719	/* 37 */ "F10\0"	----
720	/* 41 */ "F_HI10\0"	----
721	/* 48 */ "FCR10\0"	----
722	/* 54 */ "HWR10\0"	----
723	/* 60 */ "W10\0"	----
724	/* 64 */ "COP020\0"	----
725	/* 71 */ "COP220\0"	----
726	/* 78 */ "COP320\0"	----
727	/* 85 */ "MSA20\0"	----
728	/* 91 */ "F20\0"	----
729	/* 95 */ "F_HI20\0"	----
730	/* 102 */ "COP20\0"	----
731	/* 108 */ "FCR20\0"	----
732	/* 114 */ "HWR20\0"	----
733	/* 120 */ "W20\0"	----
734	/* 124 */ "DSPOutFlag20\0"	----
735	/* 137 */ "COP030\0"	----
736	/* 144 */ "COP230\0"	----
737	/* 151 */ "COP330\0"	----
738	/* 158 */ "MSA30\0"	----
739	/* 164 */ "F30\0"	----
740	/* 168 */ "F_HI30\0"	----
741	/* 175 */ "COP30\0"	----
742	/* 181 */ "FCR30\0"	----
743	/* 187 */ "HWR30\0"	----
744	/* 193 */ "W30\0"	----
745	/* 197 */ "A0\0"	----
746	/* 200 */ "AC0\0"	----
747	/* 204 */ "FCC0\0"	----
748	/* 209 */ "D0\0"	----
749	/* 212 */ "F0\0"	----
750	/* 215 */ "F_HI0\0"	----
751	/* 221 */ "K0\0"	----
752	/* 224 */ "MPL0\0"	----
753	/* 229 */ "LO0\0"	----
754	/* 233 */ "P0\0"	----
755	/* 236 */ "FCR0\0"	----
756	/* 241 */ "HWR0\0"	----
757	/* 246 */ "S0\0"	----
758	/* 249 */ "T0\0"	----
759	/* 252 */ "V0\0"	----
760	/* 255 */ "W0\0"	----
761	/* 258 */ "COP01\0"	----
762	/* 264 */ "COP011\0"	----
763	/* 271 */ "COP211\0"	----
764	/* 278 */ "COP311\0"	----
765	/* 285 */ "MSA11\0"	----
766	/* 291 */ "D11\0"	----
767	/* 295 */ "F11\0"	----
768	/* 299 */ "F_HI11\0"	----
769	/* 306 */ "FCR11\0"	----
770	/* 312 */ "HWR11\0"	----
771	/* 318 */ "W11\0"	----
772	/* 322 */ "COP021\0"	----
773	/* 329 */ "COP221\0"	----
774	/* 336 */ "COP321\0"	----
775	/* 343 */ "MSA21\0"	----
776	/* 349 */ "F21\0"	----
777	/* 353 */ "F_HI21\0"	----
778	/* 360 */ "COP21\0"	----
779	/* 366 */ "FCR21\0"	----
780	/* 372 */ "HWR21\0"	----
781	/* 378 */ "W21\0"	----
782	/* 382 */ "DSPOutFlag21\0"	----
783	/* 395 */ "COP031\0"	----
784	/* 402 */ "COP231\0"	----
785	/* 409 */ "COP331\0"	----
786	/* 416 */ "MSA31\0"	----
787	/* 422 */ "F31\0"	----
788	/* 426 */ "F_HI31\0"	----
789	/* 433 */ "COP31\0"	----
790	/* 439 */ "FCR31\0"	----
791	/* 445 */ "HWR31\0"	----
792	/* 451 */ "W31\0"	----
793	/* 455 */ "A1\0"	----
794	/* 458 */ "AC1\0"	----
795	/* 462 */ "FCC1\0"	----
796	/* 467 */ "D1\0"	----
797	/* 470 */ "F1\0"	----
798	/* 473 */ "F_HI1\0"	----
799	/* 479 */ "K1\0"	----
800	/* 482 */ "MPL1\0"	----
801	/* 487 */ "LO1\0"	----
802	/* 491 */ "P1\0"	----
803	/* 494 */ "FCR1\0"	----
804	/* 499 */ "HWR1\0"	----
805	/* 504 */ "S1\0"	----
806	/* 507 */ "T1\0"	----
807	/* 510 */ "V1\0"	----
808	/* 513 */ "W1\0"	----
809	/* 516 */ "COP02\0"	----
810	/* 522 */ "COP012\0"	----
811	/* 529 */ "COP212\0"	----
812	/* 536 */ "COP312\0"	----
813	/* 543 */ "MSA12\0"	----
814	/* 549 */ "D12\0"	----
815	/* 553 */ "F12\0"	----
816	/* 557 */ "F_HI12\0"	----
817	/* 564 */ "FCR12\0"	----
818	/* 570 */ "HWR12\0"	----
819	/* 576 */ "W12\0"	----
820	/* 580 */ "COP022\0"	----
821	/* 587 */ "COP222\0"	----
822	/* 594 */ "COP322\0"	----
823	/* 601 */ "MSA22\0"	----
824	/* 607 */ "F22\0"	----
825	/* 611 */ "F_HI22\0"	----
826	/* 618 */ "COP22\0"	----
827	/* 624 */ "FCR22\0"	----
828	/* 630 */ "HWR22\0"	----
829	/* 636 */ "W22\0"	----
830	/* 640 */ "DSPOutFlag22\0"	----
831	/* 653 */ "COP32\0"	----
832	/* 659 */ "A2\0"	----
833	/* 662 */ "AC2\0"	----
834	/* 666 */ "FCC2\0"	----
835	/* 671 */ "D2\0"	----
836	/* 674 */ "F2\0"	----
837	/* 677 */ "F_HI2\0"	----
838	/* 683 */ "MPL2\0"	----
839	/* 688 */ "LO2\0"	----
840	/* 692 */ "P2\0"	----
841	/* 695 */ "FCR2\0"	----
842	/* 700 */ "HWR2\0"	----
843	/* 705 */ "S2\0"	----
844	/* 708 */ "T2\0"	----
845	/* 711 */ "W2\0"	----
846	/* 714 */ "COP03\0"	----
847	/* 720 */ "COP013\0"	----
848	/* 727 */ "COP213\0"	----
849	/* 734 */ "COP313\0"	----
850	/* 741 */ "MSA13\0"	----
851	/* 747 */ "D13\0"	----
852	/* 751 */ "F13\0"	----
853	/* 755 */ "F_HI13\0"	----
854	/* 762 */ "FCR13\0"	----
855	/* 768 */ "HWR13\0"	----
856	/* 774 */ "W13\0"	----
857	/* 778 */ "COP023\0"	----
858	/* 785 */ "COP223\0"	----
859	/* 792 */ "COP323\0"	----
860	/* 799 */ "MSA23\0"	----
861	/* 805 */ "F23\0"	----
862	/* 809 */ "F_HI23\0"	----
863	/* 816 */ "COP23\0"	----
864	/* 822 */ "FCR23\0"	----
865	/* 828 */ "HWR23\0"	----
866	/* 834 */ "W23\0"	----
867	/* 838 */ "DSPOutFlag23\0"	----
868	/* 851 */ "COP33\0"	----
869	/* 857 */ "A3\0"	----
870	/* 860 */ "AC3\0"	----
871	/* 864 */ "FCC3\0"	----
872	/* 869 */ "D3\0"	----
873	/* 872 */ "F3\0"	----
874	/* 875 */ "F_HI3\0"	----
875	/* 881 */ "LO3\0"	----
876	/* 885 */ "FCR3\0"	----
877	/* 890 */ "HWR3\0"	----
878	/* 895 */ "S3\0"	----
879	/* 898 */ "T3\0"	----
880	/* 901 */ "W3\0"	----
881	/* 904 */ "COP04\0"	----
882	/* 910 */ "COP014\0"	----
883	/* 917 */ "COP214\0"	----
884	/* 924 */ "COP314\0"	----
885	/* 931 */ "MSA14\0"	----
886	/* 937 */ "D14\0"	----
887	/* 941 */ "F14\0"	----
888	/* 945 */ "F_HI14\0"	----
889	/* 952 */ "FCR14\0"	----
890	/* 958 */ "HWR14\0"	----
891	/* 964 */ "W14\0"	----
892	/* 968 */ "COP024\0"	----
893	/* 975 */ "COP224\0"	----
894	/* 982 */ "COP324\0"	----
895	/* 989 */ "MSA24\0"	----
896	/* 995 */ "F24\0"	----
897	/* 999 */ "F_HI24\0"	----
898	/* 1006 */ "COP24\0"	----
899	/* 1012 */ "FCR24\0"	----
900	/* 1018 */ "HWR24\0"	----
901	/* 1024 */ "W24\0"	----
902	/* 1028 */ "COP34\0"	----
903	/* 1034 */ "D10_64\0"	----
904	/* 1041 */ "D20_64\0"	----
905	/* 1048 */ "D30_64\0"	----
906	/* 1055 */ "A0_64\0"	----
907	/* 1061 */ "AC0_64\0"	----
908	/* 1068 */ "D0_64\0"	----
909	/* 1074 */ "HI0_64\0"	----
910	/* 1081 */ "K0_64\0"	----
911	/* 1087 */ "LO0_64\0"	----
912	/* 1094 */ "S0_64\0"	----
913	/* 1100 */ "T0_64\0"	----
914	/* 1106 */ "V0_64\0"	----
915	/* 1112 */ "D11_64\0"	----
916	/* 1119 */ "D21_64\0"	----
917	/* 1126 */ "D31_64\0"	----
918	/* 1133 */ "A1_64\0"	----
919	/* 1139 */ "D1_64\0"	----
920	/* 1145 */ "K1_64\0"	----
921	/* 1151 */ "S1_64\0"	----
922	/* 1157 */ "T1_64\0"	----
923	/* 1163 */ "V1_64\0"	----
924	/* 1169 */ "D12_64\0"	----
925	/* 1176 */ "D22_64\0"	----
926	/* 1183 */ "A2_64\0"	----
927	/* 1189 */ "D2_64\0"	----
928	/* 1195 */ "S2_64\0"	----
929	/* 1201 */ "T2_64\0"	----
930	/* 1207 */ "D13_64\0"	----
931	/* 1214 */ "D23_64\0"	----
932	/* 1221 */ "A3_64\0"	----
933	/* 1227 */ "D3_64\0"	----
934	/* 1233 */ "S3_64\0"	----
935	/* 1239 */ "T3_64\0"	----
936	/* 1245 */ "D14_64\0"	----
937	/* 1252 */ "D24_64\0"	----
938	/* 1259 */ "D4_64\0"	----
939	/* 1265 */ "S4_64\0"	----
940	/* 1271 */ "T4_64\0"	----
941	/* 1277 */ "D15_64\0"	----
942	/* 1284 */ "D25_64\0"	----
943	/* 1291 */ "D5_64\0"	----
944	/* 1297 */ "S5_64\0"	----
945	/* 1303 */ "T5_64\0"	----
946	/* 1309 */ "D16_64\0"	----
947	/* 1316 */ "D26_64\0"	----
948	/* 1323 */ "D6_64\0"	----
949	/* 1329 */ "S6_64\0"	----
950	/* 1335 */ "T6_64\0"	----
951	/* 1341 */ "D17_64\0"	----
952	/* 1348 */ "D27_64\0"	----
953	/* 1355 */ "D7_64\0"	----
954	/* 1361 */ "S7_64\0"	----
955	/* 1367 */ "T7_64\0"	----
956	/* 1373 */ "D18_64\0"	----
957	/* 1380 */ "D28_64\0"	----
958	/* 1387 */ "D8_64\0"	----
959	/* 1393 */ "T8_64\0"	----
960	/* 1399 */ "D19_64\0"	----
961	/* 1406 */ "D29_64\0"	----
962	/* 1413 */ "D9_64\0"	----
963	/* 1419 */ "T9_64\0"	----
964	/* 1425 */ "RA_64\0"	----
965	/* 1431 */ "ZERO_64\0"	----
966	/* 1439 */ "FP_64\0"	----
967	/* 1445 */ "GP_64\0"	----
968	/* 1451 */ "SP_64\0"	----
969	/* 1457 */ "AT_64\0"	----
970	/* 1463 */ "FCC4\0"	----
971	/* 1468 */ "D4\0"	----
972	/* 1471 */ "F4\0"	----
973	/* 1474 */ "F_HI4\0"	----
974	/* 1480 */ "FCR4\0"	----
975	/* 1485 */ "HWR4\0"	----
976	/* 1490 */ "S4\0"	----
977	/* 1493 */ "T4\0"	----
978	/* 1496 */ "W4\0"	----
979	/* 1499 */ "COP05\0"	----
980	/* 1505 */ "COP015\0"	----
981	/* 1512 */ "COP215\0"	----
982	/* 1519 */ "COP315\0"	----
983	/* 1526 */ "MSA15\0"	----
984	/* 1532 */ "D15\0"	----
985	/* 1536 */ "F15\0"	----
986	/* 1540 */ "F_HI15\0"	----
987	/* 1547 */ "FCR15\0"	----
988	/* 1553 */ "HWR15\0"	----
989	/* 1559 */ "W15\0"	----
990	/* 1563 */ "COP025\0"	----
991	/* 1570 */ "COP225\0"	----
992	/* 1577 */ "COP325\0"	----
993	/* 1584 */ "MSA25\0"	----
994	/* 1590 */ "F25\0"	----
995	/* 1594 */ "F_HI25\0"	----
996	/* 1601 */ "COP25\0"	----
997	/* 1607 */ "FCR25\0"	----
998	/* 1613 */ "HWR25\0"	----
999	/* 1619 */ "W25\0"	----
1000	/* 1623 */ "COP35\0"	----
1001	/* 1629 */ "FCC5\0"	----
1002	/* 1634 */ "D5\0"	----
1003	/* 1637 */ "F5\0"	----
1004	/* 1640 */ "F_HI5\0"	----
1005	/* 1646 */ "FCR5\0"	----
1006	/* 1651 */ "HWR5\0"	----
1007	/* 1656 */ "S5\0"	----
1008	/* 1659 */ "T5\0"	----
1009	/* 1662 */ "W5\0"	----
1010	/* 1665 */ "COP06\0"	----
1011	/* 1671 */ "COP016\0"	----
1012	/* 1678 */ "COP216\0"	----
1013	/* 1685 */ "COP316\0"	----
1014	/* 1692 */ "MSA16\0"	----
1015	/* 1698 */ "F16\0"	----
1016	/* 1702 */ "F_HI16\0"	----
1017	/* 1709 */ "FCR16\0"	----
1018	/* 1715 */ "HWR16\0"	----
1019	/* 1721 */ "W16\0"	----
1020	/* 1725 */ "COP026\0"	----
1021	/* 1732 */ "COP226\0"	----
1022	/* 1739 */ "COP326\0"	----
1023	/* 1746 */ "MSA26\0"	----
1024	/* 1752 */ "F26\0"	----
1025	/* 1756 */ "F_HI26\0"	----
1026	/* 1763 */ "COP26\0"	----
1027	/* 1769 */ "FCR26\0"	----
1028	/* 1775 */ "HWR26\0"	----
1029	/* 1781 */ "W26\0"	----
1030	/* 1785 */ "COP36\0"	----
1031	/* 1791 */ "FCC6\0"	----
1032	/* 1796 */ "D6\0"	----
1033	/* 1799 */ "F6\0"	----
1034	/* 1802 */ "F_HI6\0"	----
1035	/* 1808 */ "FCR6\0"	----
1036	/* 1813 */ "HWR6\0"	----
1037	/* 1818 */ "S6\0"	----
1038	/* 1821 */ "T6\0"	----
1039	/* 1824 */ "W6\0"	----
1040	/* 1827 */ "COP07\0"	----
1041	/* 1833 */ "COP017\0"	----
1042	/* 1840 */ "COP217\0"	----
1043	/* 1847 */ "COP317\0"	----
1044	/* 1854 */ "MSA17\0"	----
1045	/* 1860 */ "F17\0"	----
1046	/* 1864 */ "F_HI17\0"	----
1047	/* 1871 */ "FCR17\0"	----
1048	/* 1877 */ "HWR17\0"	----
1049	/* 1883 */ "W17\0"	----
1050	/* 1887 */ "COP027\0"	----
1051	/* 1894 */ "COP227\0"	----
1052	/* 1901 */ "COP327\0"	----
1053	/* 1908 */ "MSA27\0"	----
1054	/* 1914 */ "F27\0"	----
1055	/* 1918 */ "F_HI27\0"	----
1056	/* 1925 */ "COP27\0"	----
1057	/* 1931 */ "FCR27\0"	----
1058	/* 1937 */ "HWR27\0"	----
1059	/* 1943 */ "W27\0"	----
1060	/* 1947 */ "COP37\0"	----
1061	/* 1953 */ "FCC7\0"	----
1062	/* 1958 */ "D7\0"	----
1063	/* 1961 */ "F7\0"	----
1064	/* 1964 */ "F_HI7\0"	----
1065	/* 1970 */ "FCR7\0"	----
1066	/* 1975 */ "HWR7\0"	----
1067	/* 1980 */ "S7\0"	----
1068	/* 1983 */ "T7\0"	----
1069	/* 1986 */ "W7\0"	----
1070	/* 1989 */ "COP08\0"	----
1071	/* 1995 */ "COP018\0"	----
1072	/* 2002 */ "COP218\0"	----
1073	/* 2009 */ "COP318\0"	----
1074	/* 2016 */ "MSA18\0"	----
1075	/* 2022 */ "F18\0"	----
1076	/* 2026 */ "F_HI18\0"	----
1077	/* 2033 */ "FCR18\0"	----
1078	/* 2039 */ "HWR18\0"	----
1079	/* 2045 */ "W18\0"	----
1080	/* 2049 */ "COP028\0"	----
1081	/* 2056 */ "COP228\0"	----
1082	/* 2063 */ "COP328\0"	----
1083	/* 2070 */ "MSA28\0"	----
1084	/* 2076 */ "F28\0"	----
1085	/* 2080 */ "F_HI28\0"	----
1086	/* 2087 */ "COP28\0"	----
1087	/* 2093 */ "FCR28\0"	----
1088	/* 2099 */ "HWR28\0"	----
1089	/* 2105 */ "W28\0"	----
1090	/* 2109 */ "COP38\0"	----
1091	/* 2115 */ "MSA8\0"	----
1092	/* 2120 */ "D8\0"	----
1093	/* 2123 */ "F8\0"	----
1094	/* 2126 */ "F_HI8\0"	----
1095	/* 2132 */ "FCR8\0"	----
1096	/* 2137 */ "HWR8\0"	----
1097	/* 2142 */ "T8\0"	----
1098	/* 2145 */ "W8\0"	----
1099	/* 2148 */ "COP09\0"	----
1100	/* 2154 */ "COP019\0"	----
1101	/* 2161 */ "COP219\0"	----
1102	/* 2168 */ "COP319\0"	----
1103	/* 2175 */ "MSA19\0"	----
1104	/* 2181 */ "F19\0"	----
1105	/* 2185 */ "F_HI19\0"	----
1106	/* 2192 */ "FCR19\0"	----
1107	/* 2198 */ "HWR19\0"	----
1108	/* 2204 */ "W19\0"	----
1109	/* 2208 */ "DSPOutFlag16_19\0"	----
1110	/* 2224 */ "COP029\0"	----
1111	/* 2231 */ "COP229\0"	----
1112	/* 2238 */ "COP329\0"	----
1113	/* 2245 */ "MSA29\0"	----
1114	/* 2251 */ "F29\0"	----
1115	/* 2255 */ "F_HI29\0"	----
1116	/* 2262 */ "COP29\0"	----
1117	/* 2268 */ "FCR29\0"	----
1118	/* 2274 */ "HWR29\0"	----
1119	/* 2280 */ "W29\0"	----
1120	/* 2284 */ "COP39\0"	----
1121	/* 2290 */ "MSA9\0"	----
1122	/* 2295 */ "D9\0"	----
1123	/* 2298 */ "F9\0"	----
1124	/* 2301 */ "F_HI9\0"	----
1125	/* 2307 */ "FCR9\0"	----
1126	/* 2312 */ "HWR9\0"	----
1127	/* 2317 */ "T9\0"	----
1128	/* 2320 */ "W9\0"	----
1129	/* 2323 */ "RA\0"	----
1130	/* 2326 */ "PC\0"	----
1131	/* 2329 */ "DSPEFI\0"	----
1132	/* 2336 */ "ZERO\0"	----
1133	/* 2341 */ "FP\0"	----
1134	/* 2344 */ "GP\0"	----
1135	/* 2347 */ "SP\0"	----
1136	/* 2350 */ "MSAIR\0"	----
1137	/* 2356 */ "MSACSR\0"	----
1138	/* 2363 */ "AT\0"	----
1139	/* 2366 */ "DSPCCond\0"	----
1140	/* 2375 */ "MSASave\0"	----
1141	/* 2383 */ "DSPOutFlag\0"	----
1142	/* 2394 */ "MSAMap\0"	----
1143	/* 2401 */ "MSAUnmap\0"	----
1144	/* 2410 */ "DSPPos\0"	----
1145	/* 2417 */ "MSAAccess\0"	----
1146	/* 2427 */ "DSPSCount\0"	----
1147	/* 2437 */ "MSARequest\0"	----
1148	/* 2448 */ "MSAModify\0"	----
1149	/* 2458 */ "DSPCarry\0"	----
1150	};	----
1151	#ifdef __GNUC__	----
1152	#pragma GCC diagnostic pop	----
1153	#endif	----
1154		----
1155	extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors	----
1156	{ 5, 0, 0, 0, 0, 0 },	----
1157	{ 2363, 1, 176, 1, 4096, 0 },	----
1158	{ 2366, 1, 1, 1, 4097, 0 },	----
1159	{ 2458, 1, 1, 1, 4098, 0 },	----
1160	{ 2329, 1, 1, 1, 4099, 0 },	----
1161	{ 2383, 117, 1, 2, 503812, 4 },	----
1162	{ 2410, 1, 1, 1, 4105, 0 },	----
1163	{ 2427, 1, 1, 1, 4106, 0 },	----
1164	{ 2341, 1, 190, 1, 4107, 0 },	----
1165	{ 2344, 1, 192, 1, 4108, 0 },	----
1166	{ 2417, 1, 1, 1, 4109, 0 },	----
1167	{ 2356, 1, 1, 1, 4110, 0 },	----
1168	{ 2350, 1, 1, 1, 4111, 0 },	----
1169	{ 2394, 1, 1, 1, 4112, 0 },	----
1170	{ 2448, 1, 1, 1, 4113, 0 },	----
1171	{ 2437, 1, 1, 1, 4114, 0 },	----
1172	{ 2375, 1, 1, 1, 4115, 0 },	----
1173	{ 2401, 1, 1, 1, 4116, 0 },	----
1174	{ 2326, 1, 1, 1, 4117, 0 },	----
1175	{ 2323, 1, 194, 1, 4118, 0 },	----
1176	{ 2347, 1, 196, 1, 4119, 0 },	----
1177	{ 2336, 1, 198, 1, 4120, 0 },	----
1178	{ 197, 1, 198, 1, 4121, 0 },	----
1179	{ 455, 1, 198, 1, 4122, 0 },	----
1180	{ 659, 1, 198, 1, 4123, 0 },	----
1181	{ 857, 1, 198, 1, 4124, 0 },	----
1182	{ 200, 68, 198, 9, 495645, 10 },	----
1183	{ 458, 68, 1, 9, 495647, 10 },	----
1184	{ 662, 68, 1, 9, 495649, 10 },	----
1185	{ 860, 68, 1, 9, 495651, 10 },	----
1186	{ 1457, 115, 1, 0, 4096, 2 },	----
1187	{ 0, 1, 1, 1, 4133, 0 },	----
1188	{ 258, 1, 1, 1, 4134, 0 },	----
1189	{ 516, 1, 1, 1, 4135, 0 },	----
1190	{ 714, 1, 1, 1, 4136, 0 },	----
1191	{ 904, 1, 1, 1, 4137, 0 },	----
1192	{ 1499, 1, 1, 1, 4138, 0 },	----
1193	{ 1665, 1, 1, 1, 4139, 0 },	----
1194	{ 1827, 1, 1, 1, 4140, 0 },	----
1195	{ 1989, 1, 1, 1, 4141, 0 },	----
1196	{ 2148, 1, 1, 1, 4142, 0 },	----
1197	{ 102, 1, 1, 1, 4143, 0 },	----
1198	{ 360, 1, 1, 1, 4144, 0 },	----
1199	{ 618, 1, 1, 1, 4145, 0 },	----
1200	{ 816, 1, 1, 1, 4146, 0 },	----
1201	{ 1006, 1, 1, 1, 4147, 0 },	----
1202	{ 1601, 1, 1, 1, 4148, 0 },	----
1203	{ 1763, 1, 1, 1, 4149, 0 },	----
1204	{ 1925, 1, 1, 1, 4150, 0 },	----
1205	{ 2087, 1, 1, 1, 4151, 0 },	----
1206	{ 2262, 1, 1, 1, 4152, 0 },	----
1207	{ 175, 1, 1, 1, 4153, 0 },	----
1208	{ 433, 1, 1, 1, 4154, 0 },	----
1209	{ 653, 1, 1, 1, 4155, 0 },	----
1210	{ 851, 1, 1, 1, 4156, 0 },	----
1211	{ 1028, 1, 1, 1, 4157, 0 },	----
1212	{ 1623, 1, 1, 1, 4158, 0 },	----
1213	{ 1785, 1, 1, 1, 4159, 0 },	----
1214	{ 1947, 1, 1, 1, 4160, 0 },	----
1215	{ 2109, 1, 1, 1, 4161, 0 },	----
1216	{ 2284, 1, 1, 1, 4162, 0 },	----
1217	{ 6, 1, 1, 1, 4163, 0 },	----
1218	{ 264, 1, 1, 1, 4164, 0 },	----
1219	{ 522, 1, 1, 1, 4165, 0 },	----
1220	{ 720, 1, 1, 1, 4166, 0 },	----
1221	{ 910, 1, 1, 1, 4167, 0 },	----
1222	{ 1505, 1, 1, 1, 4168, 0 },	----
1223	{ 1671, 1, 1, 1, 4169, 0 },	----
1224	{ 1833, 1, 1, 1, 4170, 0 },	----
1225	{ 1995, 1, 1, 1, 4171, 0 },	----
1226	{ 2154, 1, 1, 1, 4172, 0 },	----
1227	{ 64, 1, 1, 1, 4173, 0 },	----
1228	{ 322, 1, 1, 1, 4174, 0 },	----
1229	{ 580, 1, 1, 1, 4175, 0 },	----
1230	{ 778, 1, 1, 1, 4176, 0 },	----
1231	{ 968, 1, 1, 1, 4177, 0 },	----
1232	{ 1563, 1, 1, 1, 4178, 0 },	----
1233	{ 1725, 1, 1, 1, 4179, 0 },	----
1234	{ 1887, 1, 1, 1, 4180, 0 },	----
1235	{ 2049, 1, 1, 1, 4181, 0 },	----
1236	{ 2224, 1, 1, 1, 4182, 0 },	----
1237	{ 137, 1, 1, 1, 4183, 0 },	----
1238	{ 395, 1, 1, 1, 4184, 0 },	----
1239	{ 13, 1, 1, 1, 4185, 0 },	----
1240	{ 271, 1, 1, 1, 4186, 0 },	----
1241	{ 529, 1, 1, 1, 4187, 0 },	----
1242	{ 727, 1, 1, 1, 4188, 0 },	----
1243	{ 917, 1, 1, 1, 4189, 0 },	----
1244	{ 1512, 1, 1, 1, 4190, 0 },	----
1245	{ 1678, 1, 1, 1, 4191, 0 },	----
1246	{ 1840, 1, 1, 1, 4192, 0 },	----
1247	{ 2002, 1, 1, 1, 4193, 0 },	----
1248	{ 2161, 1, 1, 1, 4194, 0 },	----
1249	{ 71, 1, 1, 1, 4195, 0 },	----
1250	{ 329, 1, 1, 1, 4196, 0 },	----
1251	{ 587, 1, 1, 1, 4197, 0 },	----
1252	{ 785, 1, 1, 1, 4198, 0 },	----
1253	{ 975, 1, 1, 1, 4199, 0 },	----
1254	{ 1570, 1, 1, 1, 4200, 0 },	----
1255	{ 1732, 1, 1, 1, 4201, 0 },	----
1256	{ 1894, 1, 1, 1, 4202, 0 },	----
1257	{ 2056, 1, 1, 1, 4203, 0 },	----
1258	{ 2231, 1, 1, 1, 4204, 0 },	----
1259	{ 144, 1, 1, 1, 4205, 0 },	----
1260	{ 402, 1, 1, 1, 4206, 0 },	----
1261	{ 20, 1, 1, 1, 4207, 0 },	----
1262	{ 278, 1, 1, 1, 4208, 0 },	----
1263	{ 536, 1, 1, 1, 4209, 0 },	----
1264	{ 734, 1, 1, 1, 4210, 0 },	----
1265	{ 924, 1, 1, 1, 4211, 0 },	----
1266	{ 1519, 1, 1, 1, 4212, 0 },	----
1267	{ 1685, 1, 1, 1, 4213, 0 },	----
1268	{ 1847, 1, 1, 1, 4214, 0 },	----
1269	{ 2009, 1, 1, 1, 4215, 0 },	----
1270	{ 2168, 1, 1, 1, 4216, 0 },	----
1271	{ 78, 1, 1, 1, 4217, 0 },	----
1272	{ 336, 1, 1, 1, 4218, 0 },	----
1273	{ 594, 1, 1, 1, 4219, 0 },	----
1274	{ 792, 1, 1, 1, 4220, 0 },	----
1275	{ 982, 1, 1, 1, 4221, 0 },	----
1276	{ 1577, 1, 1, 1, 4222, 0 },	----
1277	{ 1739, 1, 1, 1, 4223, 0 },	----
1278	{ 1901, 1, 1, 1, 4224, 0 },	----
1279	{ 2063, 1, 1, 1, 4225, 0 },	----
1280	{ 2238, 1, 1, 1, 4226, 0 },	----
1281	{ 151, 1, 1, 1, 4227, 0 },	----
1282	{ 409, 1, 1, 1, 4228, 0 },	----
1283	{ 209, 128, 1, 9, 495749, 10 },	----
1284	{ 467, 131, 1, 9, 495751, 10 },	----
1285	{ 671, 134, 1, 9, 495753, 10 },	----
1286	{ 869, 137, 1, 9, 495755, 10 },	----
1287	{ 1468, 140, 1, 9, 495757, 10 },	----
1288	{ 1634, 143, 1, 9, 495759, 10 },	----
1289	{ 1796, 146, 1, 9, 495761, 10 },	----
1290	{ 1958, 149, 1, 9, 495763, 10 },	----
1291	{ 2120, 152, 1, 9, 495765, 10 },	----
1292	{ 2295, 155, 1, 9, 495767, 10 },	----
1293	{ 33, 158, 1, 9, 495769, 10 },	----
1294	{ 291, 161, 1, 9, 495771, 10 },	----
1295	{ 549, 164, 1, 9, 495773, 10 },	----
1296	{ 747, 167, 1, 9, 495775, 10 },	----
1297	{ 937, 170, 1, 9, 495777, 10 },	----
1298	{ 1532, 173, 1, 9, 495779, 10 },	----
1299	{ 124, 1, 28, 1, 4101, 0 },	----
1300	{ 382, 1, 26, 1, 4102, 0 },	----
1301	{ 640, 1, 24, 1, 4103, 0 },	----
1302	{ 838, 1, 22, 1, 4104, 0 },	----
1303	{ 212, 1, 39, 1, 4229, 0 },	----
1304	{ 470, 1, 43, 1, 4230, 0 },	----
1305	{ 674, 1, 43, 1, 4231, 0 },	----
1306	{ 872, 1, 47, 1, 4232, 0 },	----
1307	{ 1471, 1, 47, 1, 4233, 0 },	----
1308	{ 1637, 1, 51, 1, 4234, 0 },	----
1309	{ 1799, 1, 51, 1, 4235, 0 },	----
1310	{ 1961, 1, 55, 1, 4236, 0 },	----
1311	{ 2123, 1, 55, 1, 4237, 0 },	----
1312	{ 2298, 1, 59, 1, 4238, 0 },	----
1313	{ 37, 1, 59, 1, 4239, 0 },	----
1314	{ 295, 1, 63, 1, 4240, 0 },	----
1315	{ 553, 1, 63, 1, 4241, 0 },	----
1316	{ 751, 1, 67, 1, 4242, 0 },	----
1317	{ 941, 1, 67, 1, 4243, 0 },	----
1318	{ 1536, 1, 71, 1, 4244, 0 },	----
1319	{ 1698, 1, 71, 1, 4245, 0 },	----
1320	{ 1860, 1, 75, 1, 4246, 0 },	----
1321	{ 2022, 1, 75, 1, 4247, 0 },	----
1322	{ 2181, 1, 79, 1, 4248, 0 },	----
1323	{ 91, 1, 79, 1, 4249, 0 },	----
1324	{ 349, 1, 83, 1, 4250, 0 },	----
1325	{ 607, 1, 83, 1, 4251, 0 },	----
1326	{ 805, 1, 87, 1, 4252, 0 },	----
1327	{ 995, 1, 87, 1, 4253, 0 },	----
1328	{ 1590, 1, 91, 1, 4254, 0 },	----
1329	{ 1752, 1, 91, 1, 4255, 0 },	----
1330	{ 1914, 1, 95, 1, 4256, 0 },	----
1331	{ 2076, 1, 95, 1, 4257, 0 },	----
1332	{ 2251, 1, 99, 1, 4258, 0 },	----
1333	{ 164, 1, 99, 1, 4259, 0 },	----
1334	{ 422, 1, 103, 1, 4260, 0 },	----
1335	{ 204, 1, 1, 1, 4261, 0 },	----
1336	{ 462, 1, 1, 1, 4262, 0 },	----
1337	{ 666, 1, 1, 1, 4263, 0 },	----
1338	{ 864, 1, 1, 1, 4264, 0 },	----
1339	{ 1463, 1, 1, 1, 4265, 0 },	----
1340	{ 1629, 1, 1, 1, 4266, 0 },	----
1341	{ 1791, 1, 1, 1, 4267, 0 },	----
1342	{ 1953, 1, 1, 1, 4268, 0 },	----
1343	{ 236, 1, 1, 1, 4269, 0 },	----
1344	{ 494, 1, 1, 1, 4270, 0 },	----
1345	{ 695, 1, 1, 1, 4271, 0 },	----
1346	{ 885, 1, 1, 1, 4272, 0 },	----
1347	{ 1480, 1, 1, 1, 4273, 0 },	----
1348	{ 1646, 1, 1, 1, 4274, 0 },	----
1349	{ 1808, 1, 1, 1, 4275, 0 },	----
1350	{ 1970, 1, 1, 1, 4276, 0 },	----
1351	{ 2132, 1, 1, 1, 4277, 0 },	----
1352	{ 2307, 1, 1, 1, 4278, 0 },	----
1353	{ 48, 1, 1, 1, 4279, 0 },	----
1354	{ 306, 1, 1, 1, 4280, 0 },	----
1355	{ 564, 1, 1, 1, 4281, 0 },	----
1356	{ 762, 1, 1, 1, 4282, 0 },	----
1357	{ 952, 1, 1, 1, 4283, 0 },	----
1358	{ 1547, 1, 1, 1, 4284, 0 },	----
1359	{ 1709, 1, 1, 1, 4285, 0 },	----
1360	{ 1871, 1, 1, 1, 4286, 0 },	----
1361	{ 2033, 1, 1, 1, 4287, 0 },	----
1362	{ 2192, 1, 1, 1, 4288, 0 },	----
1363	{ 108, 1, 1, 1, 4289, 0 },	----
1364	{ 366, 1, 1, 1, 4290, 0 },	----
1365	{ 624, 1, 1, 1, 4291, 0 },	----
1366	{ 822, 1, 1, 1, 4292, 0 },	----
1367	{ 1012, 1, 1, 1, 4293, 0 },	----
1368	{ 1607, 1, 1, 1, 4294, 0 },	----
1369	{ 1769, 1, 1, 1, 4295, 0 },	----
1370	{ 1931, 1, 1, 1, 4296, 0 },	----
1371	{ 2093, 1, 1, 1, 4297, 0 },	----
1372	{ 2268, 1, 1, 1, 4298, 0 },	----
1373	{ 181, 1, 1, 1, 4299, 0 },	----
1374	{ 439, 1, 1, 1, 4300, 0 },	----
1375	{ 1439, 18, 1, 0, 4107, 2 },	----
1376	{ 215, 1, 36, 1, 4301, 0 },	----
1377	{ 473, 1, 36, 1, 4302, 0 },	----
1378	{ 677, 1, 36, 1, 4303, 0 },	----
1379	{ 875, 1, 36, 1, 4304, 0 },	----
1380	{ 1474, 1, 36, 1, 4305, 0 },	----
1381	{ 1640, 1, 36, 1, 4306, 0 },	----
1382	{ 1802, 1, 36, 1, 4307, 0 },	----
1383	{ 1964, 1, 36, 1, 4308, 0 },	----
1384	{ 2126, 1, 36, 1, 4309, 0 },	----
1385	{ 2301, 1, 36, 1, 4310, 0 },	----
1386	{ 41, 1, 36, 1, 4311, 0 },	----
1387	{ 299, 1, 36, 1, 4312, 0 },	----
1388	{ 557, 1, 36, 1, 4313, 0 },	----
1389	{ 755, 1, 36, 1, 4314, 0 },	----
1390	{ 945, 1, 36, 1, 4315, 0 },	----
1391	{ 1540, 1, 36, 1, 4316, 0 },	----
1392	{ 1702, 1, 36, 1, 4317, 0 },	----
1393	{ 1864, 1, 36, 1, 4318, 0 },	----
1394	{ 2026, 1, 36, 1, 4319, 0 },	----
1395	{ 2185, 1, 36, 1, 4320, 0 },	----
1396	{ 95, 1, 36, 1, 4321, 0 },	----
1397	{ 353, 1, 36, 1, 4322, 0 },	----
1398	{ 611, 1, 36, 1, 4323, 0 },	----
1399	{ 809, 1, 36, 1, 4324, 0 },	----
1400	{ 999, 1, 36, 1, 4325, 0 },	----
1401	{ 1594, 1, 36, 1, 4326, 0 },	----
1402	{ 1756, 1, 36, 1, 4327, 0 },	----
1403	{ 1918, 1, 36, 1, 4328, 0 },	----
1404	{ 2080, 1, 36, 1, 4329, 0 },	----
1405	{ 2255, 1, 36, 1, 4330, 0 },	----
1406	{ 168, 1, 36, 1, 4331, 0 },	----
1407	{ 426, 1, 36, 1, 4332, 0 },	----
1408	{ 1445, 10, 1, 0, 4108, 2 },	----
1409	{ 217, 1, 111, 1, 4126, 0 },	----
1410	{ 475, 1, 16, 1, 4128, 0 },	----
1411	{ 679, 1, 16, 1, 4130, 0 },	----
1412	{ 877, 1, 16, 1, 4132, 0 },	----
1413	{ 241, 1, 1, 1, 4333, 0 },	----
1414	{ 499, 1, 1, 1, 4334, 0 },	----
1415	{ 700, 1, 1, 1, 4335, 0 },	----
1416	{ 890, 1, 1, 1, 4336, 0 },	----
1417	{ 1485, 1, 1, 1, 4337, 0 },	----
1418	{ 1651, 1, 1, 1, 4338, 0 },	----
1419	{ 1813, 1, 1, 1, 4339, 0 },	----
1420	{ 1975, 1, 1, 1, 4340, 0 },	----
1421	{ 2137, 1, 1, 1, 4341, 0 },	----
1422	{ 2312, 1, 1, 1, 4342, 0 },	----
1423	{ 54, 1, 1, 1, 4343, 0 },	----
1424	{ 312, 1, 1, 1, 4344, 0 },	----
1425	{ 570, 1, 1, 1, 4345, 0 },	----
1426	{ 768, 1, 1, 1, 4346, 0 },	----
1427	{ 958, 1, 1, 1, 4347, 0 },	----
1428	{ 1553, 1, 1, 1, 4348, 0 },	----
1429	{ 1715, 1, 1, 1, 4349, 0 },	----
1430	{ 1877, 1, 1, 1, 4350, 0 },	----
1431	{ 2039, 1, 1, 1, 4351, 0 },	----
1432	{ 2198, 1, 1, 1, 4352, 0 },	----
1433	{ 114, 1, 1, 1, 4353, 0 },	----
1434	{ 372, 1, 1, 1, 4354, 0 },	----
1435	{ 630, 1, 1, 1, 4355, 0 },	----
1436	{ 828, 1, 1, 1, 4356, 0 },	----
1437	{ 1018, 1, 1, 1, 4357, 0 },	----
1438	{ 1613, 1, 1, 1, 4358, 0 },	----
1439	{ 1775, 1, 1, 1, 4359, 0 },	----
1440	{ 1937, 1, 1, 1, 4360, 0 },	----
1441	{ 2099, 1, 1, 1, 4361, 0 },	----
1442	{ 2274, 1, 1, 1, 4362, 0 },	----
1443	{ 187, 1, 1, 1, 4363, 0 },	----
1444	{ 445, 1, 1, 1, 4364, 0 },	----
1445	{ 221, 1, 188, 1, 4365, 0 },	----
1446	{ 479, 1, 188, 1, 4366, 0 },	----
1447	{ 229, 1, 107, 1, 4125, 0 },	----
1448	{ 487, 1, 8, 1, 4127, 0 },	----
1449	{ 688, 1, 8, 1, 4129, 0 },	----
1450	{ 881, 1, 8, 1, 4131, 0 },	----
1451	{ 224, 1, 1, 1, 4367, 0 },	----
1452	{ 482, 1, 1, 1, 4368, 0 },	----
1453	{ 683, 1, 1, 1, 4369, 0 },	----
1454	{ 2115, 1, 1, 1, 4370, 0 },	----
1455	{ 2290, 1, 1, 1, 4371, 0 },	----
1456	{ 27, 1, 1, 1, 4372, 0 },	----
1457	{ 285, 1, 1, 1, 4373, 0 },	----
1458	{ 543, 1, 1, 1, 4374, 0 },	----
1459	{ 741, 1, 1, 1, 4375, 0 },	----
1460	{ 931, 1, 1, 1, 4376, 0 },	----
1461	{ 1526, 1, 1, 1, 4377, 0 },	----
1462	{ 1692, 1, 1, 1, 4378, 0 },	----
1463	{ 1854, 1, 1, 1, 4379, 0 },	----
1464	{ 2016, 1, 1, 1, 4380, 0 },	----
1465	{ 2175, 1, 1, 1, 4381, 0 },	----
1466	{ 85, 1, 1, 1, 4382, 0 },	----
1467	{ 343, 1, 1, 1, 4383, 0 },	----
1468	{ 601, 1, 1, 1, 4384, 0 },	----
1469	{ 799, 1, 1, 1, 4385, 0 },	----
1470	{ 989, 1, 1, 1, 4386, 0 },	----
1471	{ 1584, 1, 1, 1, 4387, 0 },	----
1472	{ 1746, 1, 1, 1, 4388, 0 },	----
1473	{ 1908, 1, 1, 1, 4389, 0 },	----
1474	{ 2070, 1, 1, 1, 4390, 0 },	----
1475	{ 2245, 1, 1, 1, 4391, 0 },	----
1476	{ 158, 1, 1, 1, 4392, 0 },	----
1477	{ 416, 1, 1, 1, 4393, 0 },	----
1478	{ 233, 1, 1, 1, 4394, 0 },	----
1479	{ 491, 1, 1, 1, 4395, 0 },	----
1480	{ 692, 1, 1, 1, 4396, 0 },	----
1481	{ 1425, 6, 1, 0, 4118, 2 },	----
1482	{ 246, 1, 186, 1, 4397, 0 },	----
1483	{ 504, 1, 186, 1, 4398, 0 },	----
1484	{ 705, 1, 186, 1, 4399, 0 },	----
1485	{ 895, 1, 186, 1, 4400, 0 },	----
1486	{ 1490, 1, 186, 1, 4401, 0 },	----
1487	{ 1656, 1, 186, 1, 4402, 0 },	----
1488	{ 1818, 1, 186, 1, 4403, 0 },	----
1489	{ 1980, 1, 186, 1, 4404, 0 },	----
1490	{ 1451, 4, 1, 0, 4119, 2 },	----
1491	{ 249, 1, 184, 1, 4405, 0 },	----
1492	{ 507, 1, 184, 1, 4406, 0 },	----
1493	{ 708, 1, 184, 1, 4407, 0 },	----
1494	{ 898, 1, 184, 1, 4408, 0 },	----
1495	{ 1493, 1, 184, 1, 4409, 0 },	----
1496	{ 1659, 1, 184, 1, 4410, 0 },	----
1497	{ 1821, 1, 184, 1, 4411, 0 },	----
1498	{ 1983, 1, 184, 1, 4412, 0 },	----
1499	{ 2142, 1, 184, 1, 4413, 0 },	----
1500	{ 2317, 1, 184, 1, 4414, 0 },	----
1501	{ 252, 1, 184, 1, 4415, 0 },	----
1502	{ 510, 1, 184, 1, 4416, 0 },	----
1503	{ 255, 180, 1, 8, 729221, 10 },	----
1504	{ 513, 180, 1, 8, 729222, 10 },	----
1505	{ 711, 180, 1, 8, 729223, 10 },	----
1506	{ 901, 180, 1, 8, 729224, 10 },	----
1507	{ 1496, 180, 1, 8, 729225, 10 },	----
1508	{ 1662, 180, 1, 8, 729226, 10 },	----
1509	{ 1824, 180, 1, 8, 729227, 10 },	----
1510	{ 1986, 180, 1, 8, 729228, 10 },	----
1511	{ 2145, 180, 1, 8, 729229, 10 },	----
1512	{ 2320, 180, 1, 8, 729230, 10 },	----
1513	{ 60, 180, 1, 8, 729231, 10 },	----
1514	{ 318, 180, 1, 8, 729232, 10 },	----
1515	{ 576, 180, 1, 8, 729233, 10 },	----
1516	{ 774, 180, 1, 8, 729234, 10 },	----
1517	{ 964, 180, 1, 8, 729235, 10 },	----
1518	{ 1559, 180, 1, 8, 729236, 10 },	----
1519	{ 1721, 180, 1, 8, 729237, 10 },	----
1520	{ 1883, 180, 1, 8, 729238, 10 },	----
1521	{ 2045, 180, 1, 8, 729239, 10 },	----
1522	{ 2204, 180, 1, 8, 729240, 10 },	----
1523	{ 120, 180, 1, 8, 729241, 10 },	----
1524	{ 378, 180, 1, 8, 729242, 10 },	----
1525	{ 636, 180, 1, 8, 729243, 10 },	----
1526	{ 834, 180, 1, 8, 729244, 10 },	----
1527	{ 1024, 180, 1, 8, 729245, 10 },	----
1528	{ 1619, 180, 1, 8, 729246, 10 },	----
1529	{ 1781, 180, 1, 8, 729247, 10 },	----
1530	{ 1943, 180, 1, 8, 729248, 10 },	----
1531	{ 2105, 180, 1, 8, 729249, 10 },	----
1532	{ 2280, 180, 1, 8, 729250, 10 },	----
1533	{ 193, 180, 1, 8, 729251, 10 },	----
1534	{ 451, 180, 1, 8, 729252, 10 },	----
1535	{ 1431, 2, 1, 0, 4120, 2 },	----
1536	{ 1055, 2, 1, 0, 4121, 2 },	----
1537	{ 1133, 2, 1, 0, 4122, 2 },	----
1538	{ 1183, 2, 1, 0, 4123, 2 },	----
1539	{ 1221, 2, 1, 0, 4124, 2 },	----
1540	{ 1061, 12, 1, 12, 495645, 10 },	----
1541	{ 1068, 181, 37, 9, 729221, 10 },	----
1542	{ 1139, 181, 37, 9, 729222, 10 },	----
1543	{ 1189, 181, 37, 9, 729223, 10 },	----
1544	{ 1227, 181, 37, 9, 729224, 10 },	----
1545	{ 1259, 181, 37, 9, 729225, 10 },	----
1546	{ 1291, 181, 37, 9, 729226, 10 },	----
1547	{ 1323, 181, 37, 9, 729227, 10 },	----
1548	{ 1355, 181, 37, 9, 729228, 10 },	----
1549	{ 1387, 181, 37, 9, 729229, 10 },	----
1550	{ 1413, 181, 37, 9, 729230, 10 },	----
1551	{ 1034, 181, 37, 9, 729231, 10 },	----
1552	{ 1112, 181, 37, 9, 729232, 10 },	----
1553	{ 1169, 181, 37, 9, 729233, 10 },	----
1554	{ 1207, 181, 37, 9, 729234, 10 },	----
1555	{ 1245, 181, 37, 9, 729235, 10 },	----
1556	{ 1277, 181, 37, 9, 729236, 10 },	----
1557	{ 1309, 181, 37, 9, 729237, 10 },	----
1558	{ 1341, 181, 37, 9, 729238, 10 },	----
1559	{ 1373, 181, 37, 9, 729239, 10 },	----
1560	{ 1399, 181, 37, 9, 729240, 10 },	----
1561	{ 1041, 181, 37, 9, 729241, 10 },	----
1562	{ 1119, 181, 37, 9, 729242, 10 },	----
1563	{ 1176, 181, 37, 9, 729243, 10 },	----
1564	{ 1214, 181, 37, 9, 729244, 10 },	----
1565	{ 1252, 181, 37, 9, 729245, 10 },	----
1566	{ 1284, 181, 37, 9, 729246, 10 },	----
1567	{ 1316, 181, 37, 9, 729247, 10 },	----
1568	{ 1348, 181, 37, 9, 729248, 10 },	----
1569	{ 1380, 181, 37, 9, 729249, 10 },	----
1570	{ 1406, 181, 37, 9, 729250, 10 },	----
1571	{ 1048, 181, 37, 9, 729251, 10 },	----
1572	{ 1126, 181, 37, 9, 729252, 10 },	----
1573	{ 2208, 1, 0, 1, 4100, 0 },	----
1574	{ 1074, 20, 113, 0, 4126, 2 },	----
1575	{ 1081, 30, 1, 0, 4365, 2 },	----
1576	{ 1145, 30, 1, 0, 4366, 2 },	----
1577	{ 1087, 30, 109, 0, 4125, 2 },	----
1578	{ 1094, 32, 1, 0, 4397, 2 },	----
1579	{ 1151, 32, 1, 0, 4398, 2 },	----
1580	{ 1195, 32, 1, 0, 4399, 2 },	----
1581	{ 1233, 32, 1, 0, 4400, 2 },	----
1582	{ 1265, 32, 1, 0, 4401, 2 },	----
1583	{ 1297, 32, 1, 0, 4402, 2 },	----
1584	{ 1329, 32, 1, 0, 4403, 2 },	----
1585	{ 1361, 32, 1, 0, 4404, 2 },	----
1586	{ 1100, 34, 1, 0, 4405, 2 },	----
1587	{ 1157, 34, 1, 0, 4406, 2 },	----
1588	{ 1201, 34, 1, 0, 4407, 2 },	----
1589	{ 1239, 34, 1, 0, 4408, 2 },	----
1590	{ 1271, 34, 1, 0, 4409, 2 },	----
1591	{ 1303, 34, 1, 0, 4410, 2 },	----
1592	{ 1335, 34, 1, 0, 4411, 2 },	----
1593	{ 1367, 34, 1, 0, 4412, 2 },	----
1594	{ 1393, 34, 1, 0, 4413, 2 },	----
1595	{ 1419, 34, 1, 0, 4414, 2 },	----
1596	{ 1106, 34, 1, 0, 4415, 2 },	----
1597	{ 1163, 34, 1, 0, 4416, 2 },	----
1598	};	----
1599		----
1600	extern const MCPhysReg MipsRegUnitRoots[][2] = {	----
1601	{ Mips::AT },	----
1602	{ Mips::DSPCCond },	----
1603	{ Mips::DSPCarry },	----
1604	{ Mips::DSPEFI },	----
1605	{ Mips::DSPOutFlag16_19 },	----
1606	{ Mips::DSPOutFlag20 },	----
1607	{ Mips::DSPOutFlag21 },	----
1608	{ Mips::DSPOutFlag22 },	----
1609	{ Mips::DSPOutFlag23 },	----
1610	{ Mips::DSPPos },	----
1611	{ Mips::DSPSCount },	----
1612	{ Mips::FP },	----
1613	{ Mips::GP },	----
1614	{ Mips::MSAAccess },	----
1615	{ Mips::MSACSR },	----
1616	{ Mips::MSAIR },	----
1617	{ Mips::MSAMap },	----
1618	{ Mips::MSAModify },	----
1619	{ Mips::MSARequest },	----
1620	{ Mips::MSASave },	----
1621	{ Mips::MSAUnmap },	----
1622	{ Mips::PC },	----
1623	{ Mips::RA },	----
1624	{ Mips::SP },	----
1625	{ Mips::ZERO },	----
1626	{ Mips::A0 },	----
1627	{ Mips::A1 },	----
1628	{ Mips::A2 },	----
1629	{ Mips::A3 },	----
1630	{ Mips::LO0 },	----
1631	{ Mips::HI0 },	----
1632	{ Mips::LO1 },	----
1633	{ Mips::HI1 },	----
1634	{ Mips::LO2 },	----
1635	{ Mips::HI2 },	----
1636	{ Mips::LO3 },	----
1637	{ Mips::HI3 },	----
1638	{ Mips::COP00 },	----
1639	{ Mips::COP01 },	----
1640	{ Mips::COP02 },	----
1641	{ Mips::COP03 },	----
1642	{ Mips::COP04 },	----
1643	{ Mips::COP05 },	----
1644	{ Mips::COP06 },	----
1645	{ Mips::COP07 },	----
1646	{ Mips::COP08 },	----
1647	{ Mips::COP09 },	----
1648	{ Mips::COP20 },	----
1649	{ Mips::COP21 },	----
1650	{ Mips::COP22 },	----
1651	{ Mips::COP23 },	----
1652	{ Mips::COP24 },	----
1653	{ Mips::COP25 },	----
1654	{ Mips::COP26 },	----
1655	{ Mips::COP27 },	----
1656	{ Mips::COP28 },	----
1657	{ Mips::COP29 },	----
1658	{ Mips::COP30 },	----
1659	{ Mips::COP31 },	----
1660	{ Mips::COP32 },	----
1661	{ Mips::COP33 },	----
1662	{ Mips::COP34 },	----
1663	{ Mips::COP35 },	----
1664	{ Mips::COP36 },	----
1665	{ Mips::COP37 },	----
1666	{ Mips::COP38 },	----
1667	{ Mips::COP39 },	----
1668	{ Mips::COP010 },	----
1669	{ Mips::COP011 },	----
1670	{ Mips::COP012 },	----
1671	{ Mips::COP013 },	----
1672	{ Mips::COP014 },	----
1673	{ Mips::COP015 },	----
1674	{ Mips::COP016 },	----
1675	{ Mips::COP017 },	----
1676	{ Mips::COP018 },	----
1677	{ Mips::COP019 },	----
1678	{ Mips::COP020 },	----
1679	{ Mips::COP021 },	----
1680	{ Mips::COP022 },	----
1681	{ Mips::COP023 },	----
1682	{ Mips::COP024 },	----
1683	{ Mips::COP025 },	----
1684	{ Mips::COP026 },	----
1685	{ Mips::COP027 },	----
1686	{ Mips::COP028 },	----
1687	{ Mips::COP029 },	----
1688	{ Mips::COP030 },	----
1689	{ Mips::COP031 },	----
1690	{ Mips::COP210 },	----
1691	{ Mips::COP211 },	----
1692	{ Mips::COP212 },	----
1693	{ Mips::COP213 },	----
1694	{ Mips::COP214 },	----
1695	{ Mips::COP215 },	----
1696	{ Mips::COP216 },	----
1697	{ Mips::COP217 },	----
1698	{ Mips::COP218 },	----
1699	{ Mips::COP219 },	----
1700	{ Mips::COP220 },	----
1701	{ Mips::COP221 },	----
1702	{ Mips::COP222 },	----
1703	{ Mips::COP223 },	----
1704	{ Mips::COP224 },	----
1705	{ Mips::COP225 },	----
1706	{ Mips::COP226 },	----
1707	{ Mips::COP227 },	----
1708	{ Mips::COP228 },	----
1709	{ Mips::COP229 },	----
1710	{ Mips::COP230 },	----
1711	{ Mips::COP231 },	----
1712	{ Mips::COP310 },	----
1713	{ Mips::COP311 },	----
1714	{ Mips::COP312 },	----
1715	{ Mips::COP313 },	----
1716	{ Mips::COP314 },	----
1717	{ Mips::COP315 },	----
1718	{ Mips::COP316 },	----
1719	{ Mips::COP317 },	----
1720	{ Mips::COP318 },	----
1721	{ Mips::COP319 },	----
1722	{ Mips::COP320 },	----
1723	{ Mips::COP321 },	----
1724	{ Mips::COP322 },	----
1725	{ Mips::COP323 },	----
1726	{ Mips::COP324 },	----
1727	{ Mips::COP325 },	----
1728	{ Mips::COP326 },	----
1729	{ Mips::COP327 },	----
1730	{ Mips::COP328 },	----
1731	{ Mips::COP329 },	----
1732	{ Mips::COP330 },	----
1733	{ Mips::COP331 },	----
1734	{ Mips::F0 },	----
1735	{ Mips::F1 },	----
1736	{ Mips::F2 },	----
1737	{ Mips::F3 },	----
1738	{ Mips::F4 },	----
1739	{ Mips::F5 },	----
1740	{ Mips::F6 },	----
1741	{ Mips::F7 },	----
1742	{ Mips::F8 },	----
1743	{ Mips::F9 },	----
1744	{ Mips::F10 },	----
1745	{ Mips::F11 },	----
1746	{ Mips::F12 },	----
1747	{ Mips::F13 },	----
1748	{ Mips::F14 },	----
1749	{ Mips::F15 },	----
1750	{ Mips::F16 },	----
1751	{ Mips::F17 },	----
1752	{ Mips::F18 },	----
1753	{ Mips::F19 },	----
1754	{ Mips::F20 },	----
1755	{ Mips::F21 },	----
1756	{ Mips::F22 },	----
1757	{ Mips::F23 },	----
1758	{ Mips::F24 },	----
1759	{ Mips::F25 },	----
1760	{ Mips::F26 },	----
1761	{ Mips::F27 },	----
1762	{ Mips::F28 },	----
1763	{ Mips::F29 },	----
1764	{ Mips::F30 },	----
1765	{ Mips::F31 },	----
1766	{ Mips::FCC0 },	----
1767	{ Mips::FCC1 },	----
1768	{ Mips::FCC2 },	----
1769	{ Mips::FCC3 },	----
1770	{ Mips::FCC4 },	----
1771	{ Mips::FCC5 },	----
1772	{ Mips::FCC6 },	----
1773	{ Mips::FCC7 },	----
1774	{ Mips::FCR0 },	----
1775	{ Mips::FCR1 },	----
1776	{ Mips::FCR2 },	----
1777	{ Mips::FCR3 },	----
1778	{ Mips::FCR4 },	----
1779	{ Mips::FCR5 },	----
1780	{ Mips::FCR6 },	----
1781	{ Mips::FCR7 },	----
1782	{ Mips::FCR8 },	----
1783	{ Mips::FCR9 },	----
1784	{ Mips::FCR10 },	----
1785	{ Mips::FCR11 },	----
1786	{ Mips::FCR12 },	----
1787	{ Mips::FCR13 },	----
1788	{ Mips::FCR14 },	----
1789	{ Mips::FCR15 },	----
1790	{ Mips::FCR16 },	----
1791	{ Mips::FCR17 },	----
1792	{ Mips::FCR18 },	----
1793	{ Mips::FCR19 },	----
1794	{ Mips::FCR20 },	----
1795	{ Mips::FCR21 },	----
1796	{ Mips::FCR22 },	----
1797	{ Mips::FCR23 },	----
1798	{ Mips::FCR24 },	----
1799	{ Mips::FCR25 },	----
1800	{ Mips::FCR26 },	----
1801	{ Mips::FCR27 },	----
1802	{ Mips::FCR28 },	----
1803	{ Mips::FCR29 },	----
1804	{ Mips::FCR30 },	----
1805	{ Mips::FCR31 },	----
1806	{ Mips::F_HI0 },	----
1807	{ Mips::F_HI1 },	----
1808	{ Mips::F_HI2 },	----
1809	{ Mips::F_HI3 },	----
1810	{ Mips::F_HI4 },	----
1811	{ Mips::F_HI5 },	----
1812	{ Mips::F_HI6 },	----
1813	{ Mips::F_HI7 },	----
1814	{ Mips::F_HI8 },	----
1815	{ Mips::F_HI9 },	----
1816	{ Mips::F_HI10 },	----
1817	{ Mips::F_HI11 },	----
1818	{ Mips::F_HI12 },	----
1819	{ Mips::F_HI13 },	----
1820	{ Mips::F_HI14 },	----
1821	{ Mips::F_HI15 },	----
1822	{ Mips::F_HI16 },	----
1823	{ Mips::F_HI17 },	----
1824	{ Mips::F_HI18 },	----
1825	{ Mips::F_HI19 },	----
1826	{ Mips::F_HI20 },	----
1827	{ Mips::F_HI21 },	----
1828	{ Mips::F_HI22 },	----
1829	{ Mips::F_HI23 },	----
1830	{ Mips::F_HI24 },	----
1831	{ Mips::F_HI25 },	----
1832	{ Mips::F_HI26 },	----
1833	{ Mips::F_HI27 },	----
1834	{ Mips::F_HI28 },	----
1835	{ Mips::F_HI29 },	----
1836	{ Mips::F_HI30 },	----
1837	{ Mips::F_HI31 },	----
1838	{ Mips::HWR0 },	----
1839	{ Mips::HWR1 },	----
1840	{ Mips::HWR2 },	----
1841	{ Mips::HWR3 },	----
1842	{ Mips::HWR4 },	----
1843	{ Mips::HWR5 },	----
1844	{ Mips::HWR6 },	----
1845	{ Mips::HWR7 },	----
1846	{ Mips::HWR8 },	----
1847	{ Mips::HWR9 },	----
1848	{ Mips::HWR10 },	----
1849	{ Mips::HWR11 },	----
1850	{ Mips::HWR12 },	----
1851	{ Mips::HWR13 },	----
1852	{ Mips::HWR14 },	----
1853	{ Mips::HWR15 },	----
1854	{ Mips::HWR16 },	----
1855	{ Mips::HWR17 },	----
1856	{ Mips::HWR18 },	----
1857	{ Mips::HWR19 },	----
1858	{ Mips::HWR20 },	----
1859	{ Mips::HWR21 },	----
1860	{ Mips::HWR22 },	----
1861	{ Mips::HWR23 },	----
1862	{ Mips::HWR24 },	----
1863	{ Mips::HWR25 },	----
1864	{ Mips::HWR26 },	----
1865	{ Mips::HWR27 },	----
1866	{ Mips::HWR28 },	----
1867	{ Mips::HWR29 },	----
1868	{ Mips::HWR30 },	----
1869	{ Mips::HWR31 },	----
1870	{ Mips::K0 },	----
1871	{ Mips::K1 },	----
1872	{ Mips::MPL0 },	----
1873	{ Mips::MPL1 },	----
1874	{ Mips::MPL2 },	----
1875	{ Mips::MSA8 },	----
1876	{ Mips::MSA9 },	----
1877	{ Mips::MSA10 },	----
1878	{ Mips::MSA11 },	----
1879	{ Mips::MSA12 },	----
1880	{ Mips::MSA13 },	----
1881	{ Mips::MSA14 },	----
1882	{ Mips::MSA15 },	----
1883	{ Mips::MSA16 },	----
1884	{ Mips::MSA17 },	----
1885	{ Mips::MSA18 },	----
1886	{ Mips::MSA19 },	----
1887	{ Mips::MSA20 },	----
1888	{ Mips::MSA21 },	----
1889	{ Mips::MSA22 },	----
1890	{ Mips::MSA23 },	----
1891	{ Mips::MSA24 },	----
1892	{ Mips::MSA25 },	----
1893	{ Mips::MSA26 },	----
1894	{ Mips::MSA27 },	----
1895	{ Mips::MSA28 },	----
1896	{ Mips::MSA29 },	----
1897	{ Mips::MSA30 },	----
1898	{ Mips::MSA31 },	----
1899	{ Mips::P0 },	----
1900	{ Mips::P1 },	----
1901	{ Mips::P2 },	----
1902	{ Mips::S0 },	----
1903	{ Mips::S1 },	----
1904	{ Mips::S2 },	----
1905	{ Mips::S3 },	----
1906	{ Mips::S4 },	----
1907	{ Mips::S5 },	----
1908	{ Mips::S6 },	----
1909	{ Mips::S7 },	----
1910	{ Mips::T0 },	----
1911	{ Mips::T1 },	----
1912	{ Mips::T2 },	----
1913	{ Mips::T3 },	----
1914	{ Mips::T4 },	----
1915	{ Mips::T5 },	----
1916	{ Mips::T6 },	----
1917	{ Mips::T7 },	----
1918	{ Mips::T8 },	----
1919	{ Mips::T9 },	----
1920	{ Mips::V0 },	----
1921	{ Mips::V1 },	----
1922	};	----
1923		----
1924	namespace { // Register classes...	----
1925	// MSA128F16 Register Class...	----
1926	const MCPhysReg MSA128F16[] = {	----
1927	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	----
1928	};	----
1929		----
1930	// MSA128F16 Bit set.	----
1931	const uint8_t MSA128F16Bits[] = {	----
1932	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
1933	};	----
1934		----
1935	// CCR Register Class...	----
1936	const MCPhysReg CCR[] = {	----
1937	Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,	----
1938	};	----
1939		----
1940	// CCR Bit set.	----
1941	const uint8_t CCRBits[] = {	----
1942	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
1943	};	----
1944		----
1945	// COP0 Register Class...	----
1946	const MCPhysReg COP0[] = {	----
1947	Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,	----
1948	};	----
1949		----
1950	// COP0 Bit set.	----
1951	const uint8_t COP0Bits[] = {	----
1952	0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,	----
1953	};	----
1954		----
1955	// COP2 Register Class...	----
1956	const MCPhysReg COP2[] = {	----
1957	Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,	----
1958	};	----
1959		----
1960	// COP2 Bit set.	----
1961	const uint8_t COP2Bits[] = {	----
1962	0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,	----
1963	};	----
1964		----
1965	// COP3 Register Class...	----
1966	const MCPhysReg COP3[] = {	----
1967	Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,	----
1968	};	----
1969		----
1970	// COP3 Bit set.	----
1971	const uint8_t COP3Bits[] = {	----
1972	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,	----
1973	};	----
1974		----
1975	// DSPR Register Class...	----
1976	const MCPhysReg DSPR[] = {	----
1977	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	----
1978	};	----
1979		----
1980	// DSPR Bit set.	----
1981	const uint8_t DSPRBits[] = {	----
1982	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	----
1983	};	----
1984		----
1985	// FGR32 Register Class...	----
1986	const MCPhysReg FGR32[] = {	----
1987	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	----
1988	};	----
1989		----
1990	// FGR32 Bit set.	----
1991	const uint8_t FGR32Bits[] = {	----
1992	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
1993	};	----
1994		----
1995	// FGRCC Register Class...	----
1996	const MCPhysReg FGRCC[] = {	----
1997	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	----
1998	};	----
1999		----
2000	// FGRCC Bit set.	----
2001	const uint8_t FGRCCBits[] = {	----
2002	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
2003	};	----
2004		----
2005	// GPR32 Register Class...	----
2006	const MCPhysReg GPR32[] = {	----
2007	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	----
2008	};	----
2009		----
2010	// GPR32 Bit set.	----
2011	const uint8_t GPR32Bits[] = {	----
2012	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	----
2013	};	----
2014		----
2015	// HWRegs Register Class...	----
2016	const MCPhysReg HWRegs[] = {	----
2017	Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,	----
2018	};	----
2019		----
2020	// HWRegs Bit set.	----
2021	const uint8_t HWRegsBits[] = {	----
2022	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	----
2023	};	----
2024		----
2025	// MSACtrl Register Class...	----
2026	const MCPhysReg MSACtrl[] = {	----
2027	Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,	----
2028	};	----
2029		----
2030	// MSACtrl Bit set.	----
2031	const uint8_t MSACtrlBits[] = {	----
2032	0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,	----
2033	};	----
2034		----
2035	// GPR32NONZERO Register Class...	----
2036	const MCPhysReg GPR32NONZERO[] = {	----
2037	Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	----
2038	};	----
2039		----
2040	// GPR32NONZERO Bit set.	----
2041	const uint8_t GPR32NONZEROBits[] = {	----
2042	0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	----
2043	};	----
2044		----
2045	// CPU16RegsPlusSP Register Class...	----
2046	const MCPhysReg CPU16RegsPlusSP[] = {	----
2047	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,	----
2048	};	----
2049		----
2050	// CPU16RegsPlusSP Bit set.	----
2051	const uint8_t CPU16RegsPlusSPBits[] = {	----
2052	0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	----
2053	};	----
2054		----
2055	// CPU16Regs Register Class...	----
2056	const MCPhysReg CPU16Regs[] = {	----
2057	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,	----
2058	};	----
2059		----
2060	// CPU16Regs Bit set.	----
2061	const uint8_t CPU16RegsBits[] = {	----
2062	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	----
2063	};	----
2064		----
2065	// FCC Register Class...	----
2066	const MCPhysReg FCC[] = {	----
2067	Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,	----
2068	};	----
2069		----
2070	// FCC Bit set.	----
2071	const uint8_t FCCBits[] = {	----
2072	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,	----
2073	};	----
2074		----
2075	// GPRMM16 Register Class...	----
2076	const MCPhysReg GPRMM16[] = {	----
2077	Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	----
2078	};	----
2079		----
2080	// GPRMM16 Bit set.	----
2081	const uint8_t GPRMM16Bits[] = {	----
2082	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	----
2083	};	----
2084		----
2085	// GPRMM16MoveP Register Class...	----
2086	const MCPhysReg GPRMM16MoveP[] = {	----
2087	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	----
2088	};	----
2089		----
2090	// GPRMM16MoveP Bit set.	----
2091	const uint8_t GPRMM16MovePBits[] = {	----
2092	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	----
2093	};	----
2094		----
2095	// GPRMM16Zero Register Class...	----
2096	const MCPhysReg GPRMM16Zero[] = {	----
2097	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	----
2098	};	----
2099		----
2100	// GPRMM16Zero Bit set.	----
2101	const uint8_t GPRMM16ZeroBits[] = {	----
2102	0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	----
2103	};	----
2104		----
2105	// CPU16Regs_and_GPRMM16Zero Register Class...	----
2106	const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {	----
2107	Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	----
2108	};	----
2109		----
2110	// CPU16Regs_and_GPRMM16Zero Bit set.	----
2111	const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {	----
2112	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	----
2113	};	----
2114		----
2115	// GPR32NONZERO_and_GPRMM16MoveP Register Class...	----
2116	const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {	----
2117	Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	----
2118	};	----
2119		----
2120	// GPR32NONZERO_and_GPRMM16MoveP Bit set.	----
2121	const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {	----
2122	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	----
2123	};	----
2124		----
2125	// GPRMM16MovePPairSecond Register Class...	----
2126	const MCPhysReg GPRMM16MovePPairSecond[] = {	----
2127	Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,	----
2128	};	----
2129		----
2130	// GPRMM16MovePPairSecond Bit set.	----
2131	const uint8_t GPRMM16MovePPairSecondBits[] = {	----
2132	0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	----
2133	};	----
2134		----
2135	// CPU16Regs_and_GPRMM16MoveP Register Class...	----
2136	const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {	----
2137	Mips::S1, Mips::V0, Mips::V1, Mips::S0,	----
2138	};	----
2139		----
2140	// CPU16Regs_and_GPRMM16MoveP Bit set.	----
2141	const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {	----
2142	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	----
2143	};	----
2144		----
2145	// GPRMM16MoveP_and_GPRMM16Zero Register Class...	----
2146	const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {	----
2147	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,	----
2148	};	----
2149		----
2150	// GPRMM16MoveP_and_GPRMM16Zero Bit set.	----
2151	const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	----
2152	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	----
2153	};	----
2154		----
2155	// HI32DSP Register Class...	----
2156	const MCPhysReg HI32DSP[] = {	----
2157	Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,	----
2158	};	----
2159		----
2160	// HI32DSP Bit set.	----
2161	const uint8_t HI32DSPBits[] = {	----
2162	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,	----
2163	};	----
2164		----
2165	// LO32DSP Register Class...	----
2166	const MCPhysReg LO32DSP[] = {	----
2167	Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,	----
2168	};	----
2169		----
2170	// LO32DSP Bit set.	----
2171	const uint8_t LO32DSPBits[] = {	----
2172	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,	----
2173	};	----
2174		----
2175	// CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	----
2176	const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {	----
2177	Mips::A1, Mips::A2, Mips::A3,	----
2178	};	----
2179		----
2180	// CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	----
2181	const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	----
2182	0x00, 0x00, 0x80, 0x03,	----
2183	};	----
2184		----
2185	// GPRMM16MovePPairFirst Register Class...	----
2186	const MCPhysReg GPRMM16MovePPairFirst[] = {	----
2187	Mips::A0, Mips::A1, Mips::A2,	----
2188	};	----
2189		----
2190	// GPRMM16MovePPairFirst Bit set.	----
2191	const uint8_t GPRMM16MovePPairFirstBits[] = {	----
2192	0x00, 0x00, 0xc0, 0x01,	----
2193	};	----
2194		----
2195	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	----
2196	const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	----
2197	Mips::S1, Mips::V0, Mips::V1,	----
2198	};	----
2199		----
2200	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	----
2201	const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	----
2202	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	----
2203	};	----
2204		----
2205	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	----
2206	const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	----
2207	Mips::A1, Mips::A2,	----
2208	};	----
2209		----
2210	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	----
2211	const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	----
2212	0x00, 0x00, 0x80, 0x01,	----
2213	};	----
2214		----
2215	// CPURAReg Register Class...	----
2216	const MCPhysReg CPURAReg[] = {	----
2217	Mips::RA,	----
2218	};	----
2219		----
2220	// CPURAReg Bit set.	----
2221	const uint8_t CPURARegBits[] = {	----
2222	0x00, 0x00, 0x08,	----
2223	};	----
2224		----
2225	// CPUSPReg Register Class...	----
2226	const MCPhysReg CPUSPReg[] = {	----
2227	Mips::SP,	----
2228	};	----
2229		----
2230	// CPUSPReg Bit set.	----
2231	const uint8_t CPUSPRegBits[] = {	----
2232	0x00, 0x00, 0x10,	----
2233	};	----
2234		----
2235	// DSPCC Register Class...	----
2236	const MCPhysReg DSPCC[] = {	----
2237	Mips::DSPCCond,	----
2238	};	----
2239		----
2240	// DSPCC Bit set.	----
2241	const uint8_t DSPCCBits[] = {	----
2242	0x04,	----
2243	};	----
2244		----
2245	// GP32 Register Class...	----
2246	const MCPhysReg GP32[] = {	----
2247	Mips::GP,	----
2248	};	----
2249		----
2250	// GP32 Bit set.	----
2251	const uint8_t GP32Bits[] = {	----
2252	0x00, 0x02,	----
2253	};	----
2254		----
2255	// GPR32ZERO Register Class...	----
2256	const MCPhysReg GPR32ZERO[] = {	----
2257	Mips::ZERO,	----
2258	};	----
2259		----
2260	// GPR32ZERO Bit set.	----
2261	const uint8_t GPR32ZEROBits[] = {	----
2262	0x00, 0x00, 0x20,	----
2263	};	----
2264		----
2265	// HI32 Register Class...	----
2266	const MCPhysReg HI32[] = {	----
2267	Mips::HI0,	----
2268	};	----
2269		----
2270	// HI32 Bit set.	----
2271	const uint8_t HI32Bits[] = {	----
2272	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	----
2273	};	----
2274		----
2275	// LO32 Register Class...	----
2276	const MCPhysReg LO32[] = {	----
2277	Mips::LO0,	----
2278	};	----
2279		----
2280	// LO32 Bit set.	----
2281	const uint8_t LO32Bits[] = {	----
2282	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	----
2283	};	----
2284		----
2285	// SP32 Register Class...	----
2286	const MCPhysReg SP32[] = {	----
2287	Mips::SP,	----
2288	};	----
2289		----
2290	// SP32 Bit set.	----
2291	const uint8_t SP32Bits[] = {	----
2292	0x00, 0x00, 0x10,	----
2293	};	----
2294		----
2295	// FGR64 Register Class...	----
2296	const MCPhysReg FGR64[] = {	----
2297	Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,	----
2298	};	----
2299		----
2300	// FGR64 Bit set.	----
2301	const uint8_t FGR64Bits[] = {	----
2302	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	----
2303	};	----
2304		----
2305	// GPR64 Register Class...	----
2306	const MCPhysReg GPR64[] = {	----
2307	Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	----
2308	};	----
2309		----
2310	// GPR64 Bit set.	----
2311	const uint8_t GPR64Bits[] = {	----
2312	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	----
2313	};	----
2314		----
2315	// GPR64_with_sub_32_in_GPR32NONZERO Register Class...	----
2316	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {	----
2317	Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	----
2318	};	----
2319		----
2320	// GPR64_with_sub_32_in_GPR32NONZERO Bit set.	----
2321	const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {	----
2322	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	----
2323	};	----
2324		----
2325	// AFGR64 Register Class...	----
2326	const MCPhysReg AFGR64[] = {	----
2327	Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,	----
2328	};	----
2329		----
2330	// AFGR64 Bit set.	----
2331	const uint8_t AFGR64Bits[] = {	----
2332	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,	----
2333	};	----
2334		----
2335	// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...	----
2336	const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {	----
2337	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,	----
2338	};	----
2339		----
2340	// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.	----
2341	const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {	----
2342	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	----
2343	};	----
2344		----
2345	// GPR64_with_sub_32_in_CPU16Regs Register Class...	----
2346	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {	----
2347	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,	----
2348	};	----
2349		----
2350	// GPR64_with_sub_32_in_CPU16Regs Bit set.	----
2351	const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {	----
2352	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	----
2353	};	----
2354		----
2355	// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...	----
2356	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {	----
2357	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	----
2358	};	----
2359		----
2360	// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.	----
2361	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {	----
2362	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	----
2363	};	----
2364		----
2365	// GPR64_with_sub_32_in_GPRMM16Zero Register Class...	----
2366	const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {	----
2367	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	----
2368	};	----
2369		----
2370	// GPR64_with_sub_32_in_GPRMM16Zero Bit set.	----
2371	const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {	----
2372	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	----
2373	};	----
2374		----
2375	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...	----
2376	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {	----
2377	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	----
2378	};	----
2379		----
2380	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.	----
2381	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {	----
2382	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	----
2383	};	----
2384		----
2385	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...	----
2386	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {	----
2387	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	----
2388	};	----
2389		----
2390	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.	----
2391	const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {	----
2392	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	----
2393	};	----
2394		----
2395	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...	----
2396	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {	----
2397	Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,	----
2398	};	----
2399		----
2400	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.	----
2401	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {	----
2402	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	----
2403	};	----
2404		----
2405	// ACC64DSP Register Class...	----
2406	const MCPhysReg ACC64DSP[] = {	----
2407	Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,	----
2408	};	----
2409		----
2410	// ACC64DSP Bit set.	----
2411	const uint8_t ACC64DSPBits[] = {	----
2412	0x00, 0x00, 0x00, 0x3c,	----
2413	};	----
2414		----
2415	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...	----
2416	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {	----
2417	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,	----
2418	};	----
2419		----
2420	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.	----
2421	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {	----
2422	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	----
2423	};	----
2424		----
2425	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...	----
2426	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {	----
2427	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,	----
2428	};	----
2429		----
2430	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.	----
2431	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	----
2432	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	----
2433	};	----
2434		----
2435	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	----
2436	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {	----
2437	Mips::A1_64, Mips::A2_64, Mips::A3_64,	----
2438	};	----
2439		----
2440	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	----
2441	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	----
2442	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,	----
2443	};	----
2444		----
2445	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...	----
2446	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {	----
2447	Mips::A0_64, Mips::A1_64, Mips::A2_64,	----
2448	};	----
2449		----
2450	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.	----
2451	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {	----
2452	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,	----
2453	};	----
2454		----
2455	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	----
2456	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	----
2457	Mips::V0_64, Mips::V1_64, Mips::S1_64,	----
2458	};	----
2459		----
2460	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	----
2461	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	----
2462	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	----
2463	};	----
2464		----
2465	// OCTEON_MPL Register Class...	----
2466	const MCPhysReg OCTEON_MPL[] = {	----
2467	Mips::MPL0, Mips::MPL1, Mips::MPL2,	----
2468	};	----
2469		----
2470	// OCTEON_MPL Bit set.	----
2471	const uint8_t OCTEON_MPLBits[] = {	----
2472	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,	----
2473	};	----
2474		----
2475	// OCTEON_P Register Class...	----
2476	const MCPhysReg OCTEON_P[] = {	----
2477	Mips::P0, Mips::P1, Mips::P2,	----
2478	};	----
2479		----
2480	// OCTEON_P Bit set.	----
2481	const uint8_t OCTEON_PBits[] = {	----
2482	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,	----
2483	};	----
2484		----
2485	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	----
2486	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	----
2487	Mips::A1_64, Mips::A2_64,	----
2488	};	----
2489		----
2490	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	----
2491	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	----
2492	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,	----
2493	};	----
2494		----
2495	// ACC64 Register Class...	----
2496	const MCPhysReg ACC64[] = {	----
2497	Mips::AC0,	----
2498	};	----
2499		----
2500	// ACC64 Bit set.	----
2501	const uint8_t ACC64Bits[] = {	----
2502	0x00, 0x00, 0x00, 0x04,	----
2503	};	----
2504		----
2505	// GP64 Register Class...	----
2506	const MCPhysReg GP64[] = {	----
2507	Mips::GP_64,	----
2508	};	----
2509		----
2510	// GP64 Bit set.	----
2511	const uint8_t GP64Bits[] = {	----
2512	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,	----
2513	};	----
2514		----
2515	// GPR64_with_sub_32_in_CPURAReg Register Class...	----
2516	const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {	----
2517	Mips::RA_64,	----
2518	};	----
2519		----
2520	// GPR64_with_sub_32_in_CPURAReg Bit set.	----
2521	const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {	----
2522	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	----
2523	};	----
2524		----
2525	// GPR64_with_sub_32_in_GPR32ZERO Register Class...	----
2526	const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {	----
2527	Mips::ZERO_64,	----
2528	};	----
2529		----
2530	// GPR64_with_sub_32_in_GPR32ZERO Bit set.	----
2531	const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {	----
2532	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	----
2533	};	----
2534		----
2535	// HI64 Register Class...	----
2536	const MCPhysReg HI64[] = {	----
2537	Mips::HI0_64,	----
2538	};	----
2539		----
2540	// HI64 Bit set.	----
2541	const uint8_t HI64Bits[] = {	----
2542	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,	----
2543	};	----
2544		----
2545	// LO64 Register Class...	----
2546	const MCPhysReg LO64[] = {	----
2547	Mips::LO0_64,	----
2548	};	----
2549		----
2550	// LO64 Bit set.	----
2551	const uint8_t LO64Bits[] = {	----
2552	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	----
2553	};	----
2554		----
2555	// SP64 Register Class...	----
2556	const MCPhysReg SP64[] = {	----
2557	Mips::SP_64,	----
2558	};	----
2559		----
2560	// SP64 Bit set.	----
2561	const uint8_t SP64Bits[] = {	----
2562	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,	----
2563	};	----
2564		----
2565	// MSA128B Register Class...	----
2566	const MCPhysReg MSA128B[] = {	----
2567	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	----
2568	};	----
2569		----
2570	// MSA128B Bit set.	----
2571	const uint8_t MSA128BBits[] = {	----
2572	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
2573	};	----
2574		----
2575	// MSA128D Register Class...	----
2576	const MCPhysReg MSA128D[] = {	----
2577	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	----
2578	};	----
2579		----
2580	// MSA128D Bit set.	----
2581	const uint8_t MSA128DBits[] = {	----
2582	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
2583	};	----
2584		----
2585	// MSA128H Register Class...	----
2586	const MCPhysReg MSA128H[] = {	----
2587	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	----
2588	};	----
2589		----
2590	// MSA128H Bit set.	----
2591	const uint8_t MSA128HBits[] = {	----
2592	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
2593	};	----
2594		----
2595	// MSA128W Register Class...	----
2596	const MCPhysReg MSA128W[] = {	----
2597	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	----
2598	};	----
2599		----
2600	// MSA128W Bit set.	----
2601	const uint8_t MSA128WBits[] = {	----
2602	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	----
2603	};	----
2604		----
2605	// MSA128WEvens Register Class...	----
2606	const MCPhysReg MSA128WEvens[] = {	----
2607	Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,	----
2608	};	----
2609		----
2610	// MSA128WEvens Bit set.	----
2611	const uint8_t MSA128WEvensBits[] = {	----
2612	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,	----
2613	};	----
2614		----
2615	// ACC128 Register Class...	----
2616	const MCPhysReg ACC128[] = {	----
2617	Mips::AC0_64,	----
2618	};	----
2619		----
2620	// ACC128 Bit set.	----
2621	const uint8_t ACC128Bits[] = {	----
2622	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,	----
2623	};	----
2624		----
2625	} // end anonymous namespace	----
2626		----
2627		----
2628	#ifdef __GNUC__	----
2629	#pragma GCC diagnostic push	----
2630	#pragma GCC diagnostic ignored "-Woverlength-strings"	----
2631	#endif	----
2632	extern const char MipsRegClassStrings[] = {	----
2633	/* 0 */ "COP0\0"	----
2634	/* 5 */ "HI32\0"	----
2635	/* 10 */ "LO32\0"	----
2636	/* 15 */ "GP32\0"	----
2637	/* 20 */ "SP32\0"	----
2638	/* 25 */ "FGR32\0"	----
2639	/* 31 */ "GPR32\0"	----
2640	/* 37 */ "COP2\0"	----
2641	/* 42 */ "COP3\0"	----
2642	/* 47 */ "ACC64\0"	----
2643	/* 53 */ "HI64\0"	----
2644	/* 58 */ "LO64\0"	----
2645	/* 63 */ "GP64\0"	----
2646	/* 68 */ "SP64\0"	----
2647	/* 73 */ "AFGR64\0"	----
2648	/* 80 */ "GPR64\0"	----
2649	/* 86 */ "MSA128F16\0"	----
2650	/* 96 */ "GPRMM16\0"	----
2651	/* 104 */ "ACC128\0"	----
2652	/* 111 */ "MSA128B\0"	----
2653	/* 119 */ "FCC\0"	----
2654	/* 123 */ "DSPCC\0"	----
2655	/* 129 */ "FGRCC\0"	----
2656	/* 135 */ "MSA128D\0"	----
2657	/* 143 */ "MSA128H\0"	----
2658	/* 151 */ "OCTEON_MPL\0"	----
2659	/* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"	----
2660	/* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"	----
2661	/* 227 */ "HI32DSP\0"	----
2662	/* 235 */ "LO32DSP\0"	----
2663	/* 243 */ "ACC64DSP\0"	----
2664	/* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"	----
2665	/* 289 */ "OCTEON_P\0"	----
2666	/* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"	----
2667	/* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"	----
2668	/* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"	----
2669	/* 431 */ "CCR\0"	----
2670	/* 435 */ "DSPR\0"	----
2671	/* 440 */ "MSA128W\0"	----
2672	/* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"	----
2673	/* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"	----
2674	/* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"	----
2675	/* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"	----
2676	/* 650 */ "CPUSPReg\0"	----
2677	/* 659 */ "MSACtrl\0"	----
2678	/* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"	----
2679	/* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"	----
2680	/* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"	----
2681	/* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"	----
2682	/* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"	----
2683	/* 892 */ "HWRegs\0"	----
2684	/* 899 */ "MSA128WEvens\0"	----
2685	/* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"	----
2686	};	----
2687	#ifdef __GNUC__	----
2688	#pragma GCC diagnostic pop	----
2689	#endif	----
2690		----
2691	extern const MCRegisterClass MipsMCRegisterClasses[] = {	----
2692	{ MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },	----
2693	{ CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },	----
2694	{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },	----
2695	{ COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },	----
2696	{ COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },	----
2697	{ DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },	----
2698	{ FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },	----
2699	{ FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },	----
2700	{ GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },	----
2701	{ HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },	----
2702	{ MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },	----
2703	{ GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },	----
2704	{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },	----
2705	{ CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },	----
2706	{ FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },	----
2707	{ GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },	----
2708	{ GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },	----
2709	{ GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },	----
2710	{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	----
2711	{ GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },	----
2712	{ GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },	----
2713	{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },	----
2714	{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },	----
2715	{ HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },	----
2716	{ LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },	----
2717	{ CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	----
2718	{ GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },	----
2719	{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	----
2720	{ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	----
2721	{ CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },	----
2722	{ CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },	----
2723	{ DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },	----
2724	{ GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },	----
2725	{ GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },	----
2726	{ HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },	----
2727	{ LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },	----
2728	{ SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },	----
2729	{ FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },	----
2730	{ GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },	----
2731	{ GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },	----
2732	{ AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },	----
2733	{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },	----
2734	{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },	----
2735	{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },	----
2736	{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },	----
2737	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	----
2738	{ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },	----
2739	{ GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	----
2740	{ ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },	----
2741	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },	----
2742	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },	----
2743	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	----
2744	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },	----
2745	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	----
2746	{ OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },	----
2747	{ OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },	----
2748	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	----
2749	{ ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },	----
2750	{ GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },	----
2751	{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },	----
2752	{ GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },	----
2753	{ HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },	----
2754	{ LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },	----
2755	{ SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },	----
2756	{ MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },	----
2757	{ MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },	----
2758	{ MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },	----
2759	{ MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },	----
2760	{ MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },	----
2761	{ ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },	----
2762	};	----
2763		----
2764	// Mips Dwarf<->LLVM register mappings.	----
2765	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {	----
2766	{ 0U, Mips::ZERO_64 },	----
2767	{ 1U, Mips::AT_64 },	----
2768	{ 2U, Mips::V0_64 },	----
2769	{ 3U, Mips::V1_64 },	----
2770	{ 4U, Mips::A0_64 },	----
2771	{ 5U, Mips::A1_64 },	----
2772	{ 6U, Mips::A2_64 },	----
2773	{ 7U, Mips::A3_64 },	----
2774	{ 8U, Mips::T0_64 },	----
2775	{ 9U, Mips::T1_64 },	----
2776	{ 10U, Mips::T2_64 },	----
2777	{ 11U, Mips::T3_64 },	----
2778	{ 12U, Mips::T4_64 },	----
2779	{ 13U, Mips::T5_64 },	----
2780	{ 14U, Mips::T6_64 },	----
2781	{ 15U, Mips::T7_64 },	----
2782	{ 16U, Mips::S0_64 },	----
2783	{ 17U, Mips::S1_64 },	----
2784	{ 18U, Mips::S2_64 },	----
2785	{ 19U, Mips::S3_64 },	----
2786	{ 20U, Mips::S4_64 },	----
2787	{ 21U, Mips::S5_64 },	----
2788	{ 22U, Mips::S6_64 },	----
2789	{ 23U, Mips::S7_64 },	----
2790	{ 24U, Mips::T8_64 },	----
2791	{ 25U, Mips::T9_64 },	----
2792	{ 26U, Mips::K0_64 },	----
2793	{ 27U, Mips::K1_64 },	----
2794	{ 28U, Mips::GP_64 },	----
2795	{ 29U, Mips::SP_64 },	----
2796	{ 30U, Mips::FP_64 },	----
2797	{ 31U, Mips::RA_64 },	----
2798	{ 32U, Mips::D0_64 },	----
2799	{ 33U, Mips::D1_64 },	----
2800	{ 34U, Mips::D2_64 },	----
2801	{ 35U, Mips::D3_64 },	----
2802	{ 36U, Mips::D4_64 },	----
2803	{ 37U, Mips::D5_64 },	----
2804	{ 38U, Mips::D6_64 },	----
2805	{ 39U, Mips::D7_64 },	----
2806	{ 40U, Mips::D8_64 },	----
2807	{ 41U, Mips::D9_64 },	----
2808	{ 42U, Mips::D10_64 },	----
2809	{ 43U, Mips::D11_64 },	----
2810	{ 44U, Mips::D12_64 },	----
2811	{ 45U, Mips::D13_64 },	----
2812	{ 46U, Mips::D14_64 },	----
2813	{ 47U, Mips::D15_64 },	----
2814	{ 48U, Mips::D16_64 },	----
2815	{ 49U, Mips::D17_64 },	----
2816	{ 50U, Mips::D18_64 },	----
2817	{ 51U, Mips::D19_64 },	----
2818	{ 52U, Mips::D20_64 },	----
2819	{ 53U, Mips::D21_64 },	----
2820	{ 54U, Mips::D22_64 },	----
2821	{ 55U, Mips::D23_64 },	----
2822	{ 56U, Mips::D24_64 },	----
2823	{ 57U, Mips::D25_64 },	----
2824	{ 58U, Mips::D26_64 },	----
2825	{ 59U, Mips::D27_64 },	----
2826	{ 60U, Mips::D28_64 },	----
2827	{ 61U, Mips::D29_64 },	----
2828	{ 62U, Mips::D30_64 },	----
2829	{ 63U, Mips::D31_64 },	----
2830	{ 64U, Mips::HI0 },	----
2831	{ 65U, Mips::LO0 },	----
2832	{ 176U, Mips::HI1 },	----
2833	{ 177U, Mips::LO1 },	----
2834	{ 178U, Mips::HI2 },	----
2835	{ 179U, Mips::LO2 },	----
2836	{ 180U, Mips::HI3 },	----
2837	{ 181U, Mips::LO3 },	----
2838	};	----
2839	extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);	----
2840		----
2841	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {	----
2842	{ 0U, Mips::ZERO_64 },	----
2843	{ 1U, Mips::AT_64 },	----
2844	{ 2U, Mips::V0_64 },	----
2845	{ 3U, Mips::V1_64 },	----
2846	{ 4U, Mips::A0_64 },	----
2847	{ 5U, Mips::A1_64 },	----
2848	{ 6U, Mips::A2_64 },	----
2849	{ 7U, Mips::A3_64 },	----
2850	{ 8U, Mips::T0_64 },	----
2851	{ 9U, Mips::T1_64 },	----
2852	{ 10U, Mips::T2_64 },	----
2853	{ 11U, Mips::T3_64 },	----
2854	{ 12U, Mips::T4_64 },	----
2855	{ 13U, Mips::T5_64 },	----
2856	{ 14U, Mips::T6_64 },	----
2857	{ 15U, Mips::T7_64 },	----
2858	{ 16U, Mips::S0_64 },	----
2859	{ 17U, Mips::S1_64 },	----
2860	{ 18U, Mips::S2_64 },	----
2861	{ 19U, Mips::S3_64 },	----
2862	{ 20U, Mips::S4_64 },	----
2863	{ 21U, Mips::S5_64 },	----
2864	{ 22U, Mips::S6_64 },	----
2865	{ 23U, Mips::S7_64 },	----
2866	{ 24U, Mips::T8_64 },	----
2867	{ 25U, Mips::T9_64 },	----
2868	{ 26U, Mips::K0_64 },	----
2869	{ 27U, Mips::K1_64 },	----
2870	{ 28U, Mips::GP_64 },	----
2871	{ 29U, Mips::SP_64 },	----
2872	{ 30U, Mips::FP_64 },	----
2873	{ 31U, Mips::RA_64 },	----
2874	{ 32U, Mips::D0_64 },	----
2875	{ 33U, Mips::D1_64 },	----
2876	{ 34U, Mips::D2_64 },	----
2877	{ 35U, Mips::D3_64 },	----
2878	{ 36U, Mips::D4_64 },	----
2879	{ 37U, Mips::D5_64 },	----
2880	{ 38U, Mips::D6_64 },	----
2881	{ 39U, Mips::D7_64 },	----
2882	{ 40U, Mips::D8_64 },	----
2883	{ 41U, Mips::D9_64 },	----
2884	{ 42U, Mips::D10_64 },	----
2885	{ 43U, Mips::D11_64 },	----
2886	{ 44U, Mips::D12_64 },	----
2887	{ 45U, Mips::D13_64 },	----
2888	{ 46U, Mips::D14_64 },	----
2889	{ 47U, Mips::D15_64 },	----
2890	{ 48U, Mips::D16_64 },	----
2891	{ 49U, Mips::D17_64 },	----
2892	{ 50U, Mips::D18_64 },	----
2893	{ 51U, Mips::D19_64 },	----
2894	{ 52U, Mips::D20_64 },	----
2895	{ 53U, Mips::D21_64 },	----
2896	{ 54U, Mips::D22_64 },	----
2897	{ 55U, Mips::D23_64 },	----
2898	{ 56U, Mips::D24_64 },	----
2899	{ 57U, Mips::D25_64 },	----
2900	{ 58U, Mips::D26_64 },	----
2901	{ 59U, Mips::D27_64 },	----
2902	{ 60U, Mips::D28_64 },	----
2903	{ 61U, Mips::D29_64 },	----
2904	{ 62U, Mips::D30_64 },	----
2905	{ 63U, Mips::D31_64 },	----
2906	{ 64U, Mips::HI0 },	----
2907	{ 65U, Mips::LO0 },	----
2908	{ 176U, Mips::HI1 },	----
2909	{ 177U, Mips::LO1 },	----
2910	{ 178U, Mips::HI2 },	----
2911	{ 179U, Mips::LO2 },	----
2912	{ 180U, Mips::HI3 },	----
2913	{ 181U, Mips::LO3 },	----
2914	};	----
2915	extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);	----
2916		----
2917	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {	----
2918	{ Mips::AT, 1U },	----
2919	{ Mips::FP, 30U },	----
2920	{ Mips::GP, 28U },	----
2921	{ Mips::RA, 31U },	----
2922	{ Mips::SP, 29U },	----
2923	{ Mips::ZERO, 0U },	----
2924	{ Mips::A0, 4U },	----
2925	{ Mips::A1, 5U },	----
2926	{ Mips::A2, 6U },	----
2927	{ Mips::A3, 7U },	----
2928	{ Mips::AT_64, 1U },	----
2929	{ Mips::F0, 32U },	----
2930	{ Mips::F1, 33U },	----
2931	{ Mips::F2, 34U },	----
2932	{ Mips::F3, 35U },	----
2933	{ Mips::F4, 36U },	----
2934	{ Mips::F5, 37U },	----
2935	{ Mips::F6, 38U },	----
2936	{ Mips::F7, 39U },	----
2937	{ Mips::F8, 40U },	----
2938	{ Mips::F9, 41U },	----
2939	{ Mips::F10, 42U },	----
2940	{ Mips::F11, 43U },	----
2941	{ Mips::F12, 44U },	----
2942	{ Mips::F13, 45U },	----
2943	{ Mips::F14, 46U },	----
2944	{ Mips::F15, 47U },	----
2945	{ Mips::F16, 48U },	----
2946	{ Mips::F17, 49U },	----
2947	{ Mips::F18, 50U },	----
2948	{ Mips::F19, 51U },	----
2949	{ Mips::F20, 52U },	----
2950	{ Mips::F21, 53U },	----
2951	{ Mips::F22, 54U },	----
2952	{ Mips::F23, 55U },	----
2953	{ Mips::F24, 56U },	----
2954	{ Mips::F25, 57U },	----
2955	{ Mips::F26, 58U },	----
2956	{ Mips::F27, 59U },	----
2957	{ Mips::F28, 60U },	----
2958	{ Mips::F29, 61U },	----
2959	{ Mips::F30, 62U },	----
2960	{ Mips::F31, 63U },	----
2961	{ Mips::FP_64, 30U },	----
2962	{ Mips::F_HI0, 32U },	----
2963	{ Mips::F_HI1, 33U },	----
2964	{ Mips::F_HI2, 34U },	----
2965	{ Mips::F_HI3, 35U },	----
2966	{ Mips::F_HI4, 36U },	----
2967	{ Mips::F_HI5, 37U },	----
2968	{ Mips::F_HI6, 38U },	----
2969	{ Mips::F_HI7, 39U },	----
2970	{ Mips::F_HI8, 40U },	----
2971	{ Mips::F_HI9, 41U },	----
2972	{ Mips::F_HI10, 42U },	----
2973	{ Mips::F_HI11, 43U },	----
2974	{ Mips::F_HI12, 44U },	----
2975	{ Mips::F_HI13, 45U },	----
2976	{ Mips::F_HI14, 46U },	----
2977	{ Mips::F_HI15, 47U },	----
2978	{ Mips::F_HI16, 48U },	----
2979	{ Mips::F_HI17, 49U },	----
2980	{ Mips::F_HI18, 50U },	----
2981	{ Mips::F_HI19, 51U },	----
2982	{ Mips::F_HI20, 52U },	----
2983	{ Mips::F_HI21, 53U },	----
2984	{ Mips::F_HI22, 54U },	----
2985	{ Mips::F_HI23, 55U },	----
2986	{ Mips::F_HI24, 56U },	----
2987	{ Mips::F_HI25, 57U },	----
2988	{ Mips::F_HI26, 58U },	----
2989	{ Mips::F_HI27, 59U },	----
2990	{ Mips::F_HI28, 60U },	----
2991	{ Mips::F_HI29, 61U },	----
2992	{ Mips::F_HI30, 62U },	----
2993	{ Mips::F_HI31, 63U },	----
2994	{ Mips::GP_64, 28U },	----
2995	{ Mips::HI0, 64U },	----
2996	{ Mips::HI1, 176U },	----
2997	{ Mips::HI2, 178U },	----
2998	{ Mips::HI3, 180U },	----
2999	{ Mips::K0, 26U },	----
3000	{ Mips::K1, 27U },	----
3001	{ Mips::LO0, 65U },	----
3002	{ Mips::LO1, 177U },	----
3003	{ Mips::LO2, 179U },	----
3004	{ Mips::LO3, 181U },	----
3005	{ Mips::RA_64, 31U },	----
3006	{ Mips::S0, 16U },	----
3007	{ Mips::S1, 17U },	----
3008	{ Mips::S2, 18U },	----
3009	{ Mips::S3, 19U },	----
3010	{ Mips::S4, 20U },	----
3011	{ Mips::S5, 21U },	----
3012	{ Mips::S6, 22U },	----
3013	{ Mips::S7, 23U },	----
3014	{ Mips::SP_64, 29U },	----
3015	{ Mips::T0, 8U },	----
3016	{ Mips::T1, 9U },	----
3017	{ Mips::T2, 10U },	----
3018	{ Mips::T3, 11U },	----
3019	{ Mips::T4, 12U },	----
3020	{ Mips::T5, 13U },	----
3021	{ Mips::T6, 14U },	----
3022	{ Mips::T7, 15U },	----
3023	{ Mips::T8, 24U },	----
3024	{ Mips::T9, 25U },	----
3025	{ Mips::V0, 2U },	----
3026	{ Mips::V1, 3U },	----
3027	{ Mips::W0, 32U },	----
3028	{ Mips::W1, 33U },	----
3029	{ Mips::W2, 34U },	----
3030	{ Mips::W3, 35U },	----
3031	{ Mips::W4, 36U },	----
3032	{ Mips::W5, 37U },	----
3033	{ Mips::W6, 38U },	----
3034	{ Mips::W7, 39U },	----
3035	{ Mips::W8, 40U },	----
3036	{ Mips::W9, 41U },	----
3037	{ Mips::W10, 42U },	----
3038	{ Mips::W11, 43U },	----
3039	{ Mips::W12, 44U },	----
3040	{ Mips::W13, 45U },	----
3041	{ Mips::W14, 46U },	----
3042	{ Mips::W15, 47U },	----
3043	{ Mips::W16, 48U },	----
3044	{ Mips::W17, 49U },	----
3045	{ Mips::W18, 50U },	----
3046	{ Mips::W19, 51U },	----
3047	{ Mips::W20, 52U },	----
3048	{ Mips::W21, 53U },	----
3049	{ Mips::W22, 54U },	----
3050	{ Mips::W23, 55U },	----
3051	{ Mips::W24, 56U },	----
3052	{ Mips::W25, 57U },	----
3053	{ Mips::W26, 58U },	----
3054	{ Mips::W27, 59U },	----
3055	{ Mips::W28, 60U },	----
3056	{ Mips::W29, 61U },	----
3057	{ Mips::W30, 62U },	----
3058	{ Mips::W31, 63U },	----
3059	{ Mips::ZERO_64, 0U },	----
3060	{ Mips::A0_64, 4U },	----
3061	{ Mips::A1_64, 5U },	----
3062	{ Mips::A2_64, 6U },	----
3063	{ Mips::A3_64, 7U },	----
3064	{ Mips::D0_64, 32U },	----
3065	{ Mips::D1_64, 33U },	----
3066	{ Mips::D2_64, 34U },	----
3067	{ Mips::D3_64, 35U },	----
3068	{ Mips::D4_64, 36U },	----
3069	{ Mips::D5_64, 37U },	----
3070	{ Mips::D6_64, 38U },	----
3071	{ Mips::D7_64, 39U },	----
3072	{ Mips::D8_64, 40U },	----
3073	{ Mips::D9_64, 41U },	----
3074	{ Mips::D10_64, 42U },	----
3075	{ Mips::D11_64, 43U },	----
3076	{ Mips::D12_64, 44U },	----
3077	{ Mips::D13_64, 45U },	----
3078	{ Mips::D14_64, 46U },	----
3079	{ Mips::D15_64, 47U },	----
3080	{ Mips::D16_64, 48U },	----
3081	{ Mips::D17_64, 49U },	----
3082	{ Mips::D18_64, 50U },	----
3083	{ Mips::D19_64, 51U },	----
3084	{ Mips::D20_64, 52U },	----
3085	{ Mips::D21_64, 53U },	----
3086	{ Mips::D22_64, 54U },	----
3087	{ Mips::D23_64, 55U },	----
3088	{ Mips::D24_64, 56U },	----
3089	{ Mips::D25_64, 57U },	----
3090	{ Mips::D26_64, 58U },	----
3091	{ Mips::D27_64, 59U },	----
3092	{ Mips::D28_64, 60U },	----
3093	{ Mips::D29_64, 61U },	----
3094	{ Mips::D30_64, 62U },	----
3095	{ Mips::D31_64, 63U },	----
3096	{ Mips::K0_64, 26U },	----
3097	{ Mips::K1_64, 27U },	----
3098	{ Mips::S0_64, 16U },	----
3099	{ Mips::S1_64, 17U },	----
3100	{ Mips::S2_64, 18U },	----
3101	{ Mips::S3_64, 19U },	----
3102	{ Mips::S4_64, 20U },	----
3103	{ Mips::S5_64, 21U },	----
3104	{ Mips::S6_64, 22U },	----
3105	{ Mips::S7_64, 23U },	----
3106	{ Mips::T0_64, 8U },	----
3107	{ Mips::T1_64, 9U },	----
3108	{ Mips::T2_64, 10U },	----
3109	{ Mips::T3_64, 11U },	----
3110	{ Mips::T4_64, 12U },	----
3111	{ Mips::T5_64, 13U },	----
3112	{ Mips::T6_64, 14U },	----
3113	{ Mips::T7_64, 15U },	----
3114	{ Mips::T8_64, 24U },	----
3115	{ Mips::T9_64, 25U },	----
3116	{ Mips::V0_64, 2U },	----
3117	{ Mips::V1_64, 3U },	----
3118	};	----
3119	extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);	----
3120		----
3121	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {	----
3122	{ Mips::AT, 1U },	----
3123	{ Mips::FP, 30U },	----
3124	{ Mips::GP, 28U },	----
3125	{ Mips::RA, 31U },	----
3126	{ Mips::SP, 29U },	----
3127	{ Mips::ZERO, 0U },	----
3128	{ Mips::A0, 4U },	----
3129	{ Mips::A1, 5U },	----
3130	{ Mips::A2, 6U },	----
3131	{ Mips::A3, 7U },	----
3132	{ Mips::AT_64, 1U },	----
3133	{ Mips::F0, 32U },	----
3134	{ Mips::F1, 33U },	----
3135	{ Mips::F2, 34U },	----
3136	{ Mips::F3, 35U },	----
3137	{ Mips::F4, 36U },	----
3138	{ Mips::F5, 37U },	----
3139	{ Mips::F6, 38U },	----
3140	{ Mips::F7, 39U },	----
3141	{ Mips::F8, 40U },	----
3142	{ Mips::F9, 41U },	----
3143	{ Mips::F10, 42U },	----
3144	{ Mips::F11, 43U },	----
3145	{ Mips::F12, 44U },	----
3146	{ Mips::F13, 45U },	----
3147	{ Mips::F14, 46U },	----
3148	{ Mips::F15, 47U },	----
3149	{ Mips::F16, 48U },	----
3150	{ Mips::F17, 49U },	----
3151	{ Mips::F18, 50U },	----
3152	{ Mips::F19, 51U },	----
3153	{ Mips::F20, 52U },	----
3154	{ Mips::F21, 53U },	----
3155	{ Mips::F22, 54U },	----
3156	{ Mips::F23, 55U },	----
3157	{ Mips::F24, 56U },	----
3158	{ Mips::F25, 57U },	----
3159	{ Mips::F26, 58U },	----
3160	{ Mips::F27, 59U },	----
3161	{ Mips::F28, 60U },	----
3162	{ Mips::F29, 61U },	----
3163	{ Mips::F30, 62U },	----
3164	{ Mips::F31, 63U },	----
3165	{ Mips::FP_64, 30U },	----
3166	{ Mips::F_HI0, 32U },	----
3167	{ Mips::F_HI1, 33U },	----
3168	{ Mips::F_HI2, 34U },	----
3169	{ Mips::F_HI3, 35U },	----
3170	{ Mips::F_HI4, 36U },	----
3171	{ Mips::F_HI5, 37U },	----
3172	{ Mips::F_HI6, 38U },	----
3173	{ Mips::F_HI7, 39U },	----
3174	{ Mips::F_HI8, 40U },	----
3175	{ Mips::F_HI9, 41U },	----
3176	{ Mips::F_HI10, 42U },	----
3177	{ Mips::F_HI11, 43U },	----
3178	{ Mips::F_HI12, 44U },	----
3179	{ Mips::F_HI13, 45U },	----
3180	{ Mips::F_HI14, 46U },	----
3181	{ Mips::F_HI15, 47U },	----
3182	{ Mips::F_HI16, 48U },	----
3183	{ Mips::F_HI17, 49U },	----
3184	{ Mips::F_HI18, 50U },	----
3185	{ Mips::F_HI19, 51U },	----
3186	{ Mips::F_HI20, 52U },	----
3187	{ Mips::F_HI21, 53U },	----
3188	{ Mips::F_HI22, 54U },	----
3189	{ Mips::F_HI23, 55U },	----
3190	{ Mips::F_HI24, 56U },	----
3191	{ Mips::F_HI25, 57U },	----
3192	{ Mips::F_HI26, 58U },	----
3193	{ Mips::F_HI27, 59U },	----
3194	{ Mips::F_HI28, 60U },	----
3195	{ Mips::F_HI29, 61U },	----
3196	{ Mips::F_HI30, 62U },	----
3197	{ Mips::F_HI31, 63U },	----
3198	{ Mips::GP_64, 28U },	----
3199	{ Mips::HI0, 64U },	----
3200	{ Mips::HI1, 176U },	----
3201	{ Mips::HI2, 178U },	----
3202	{ Mips::HI3, 180U },	----
3203	{ Mips::K0, 26U },	----
3204	{ Mips::K1, 27U },	----
3205	{ Mips::LO0, 65U },	----
3206	{ Mips::LO1, 177U },	----
3207	{ Mips::LO2, 179U },	----
3208	{ Mips::LO3, 181U },	----
3209	{ Mips::RA_64, 31U },	----
3210	{ Mips::S0, 16U },	----
3211	{ Mips::S1, 17U },	----
3212	{ Mips::S2, 18U },	----
3213	{ Mips::S3, 19U },	----
3214	{ Mips::S4, 20U },	----
3215	{ Mips::S5, 21U },	----
3216	{ Mips::S6, 22U },	----
3217	{ Mips::S7, 23U },	----
3218	{ Mips::SP_64, 29U },	----
3219	{ Mips::T0, 8U },	----
3220	{ Mips::T1, 9U },	----
3221	{ Mips::T2, 10U },	----
3222	{ Mips::T3, 11U },	----
3223	{ Mips::T4, 12U },	----
3224	{ Mips::T5, 13U },	----
3225	{ Mips::T6, 14U },	----
3226	{ Mips::T7, 15U },	----
3227	{ Mips::T8, 24U },	----
3228	{ Mips::T9, 25U },	----
3229	{ Mips::V0, 2U },	----
3230	{ Mips::V1, 3U },	----
3231	{ Mips::W0, 32U },	----
3232	{ Mips::W1, 33U },	----
3233	{ Mips::W2, 34U },	----
3234	{ Mips::W3, 35U },	----
3235	{ Mips::W4, 36U },	----
3236	{ Mips::W5, 37U },	----
3237	{ Mips::W6, 38U },	----
3238	{ Mips::W7, 39U },	----
3239	{ Mips::W8, 40U },	----
3240	{ Mips::W9, 41U },	----
3241	{ Mips::W10, 42U },	----
3242	{ Mips::W11, 43U },	----
3243	{ Mips::W12, 44U },	----
3244	{ Mips::W13, 45U },	----
3245	{ Mips::W14, 46U },	----
3246	{ Mips::W15, 47U },	----
3247	{ Mips::W16, 48U },	----
3248	{ Mips::W17, 49U },	----
3249	{ Mips::W18, 50U },	----
3250	{ Mips::W19, 51U },	----
3251	{ Mips::W20, 52U },	----
3252	{ Mips::W21, 53U },	----
3253	{ Mips::W22, 54U },	----
3254	{ Mips::W23, 55U },	----
3255	{ Mips::W24, 56U },	----
3256	{ Mips::W25, 57U },	----
3257	{ Mips::W26, 58U },	----
3258	{ Mips::W27, 59U },	----
3259	{ Mips::W28, 60U },	----
3260	{ Mips::W29, 61U },	----
3261	{ Mips::W30, 62U },	----
3262	{ Mips::W31, 63U },	----
3263	{ Mips::ZERO_64, 0U },	----
3264	{ Mips::A0_64, 4U },	----
3265	{ Mips::A1_64, 5U },	----
3266	{ Mips::A2_64, 6U },	----
3267	{ Mips::A3_64, 7U },	----
3268	{ Mips::D0_64, 32U },	----
3269	{ Mips::D1_64, 33U },	----
3270	{ Mips::D2_64, 34U },	----
3271	{ Mips::D3_64, 35U },	----
3272	{ Mips::D4_64, 36U },	----
3273	{ Mips::D5_64, 37U },	----
3274	{ Mips::D6_64, 38U },	----
3275	{ Mips::D7_64, 39U },	----
3276	{ Mips::D8_64, 40U },	----
3277	{ Mips::D9_64, 41U },	----
3278	{ Mips::D10_64, 42U },	----
3279	{ Mips::D11_64, 43U },	----
3280	{ Mips::D12_64, 44U },	----
3281	{ Mips::D13_64, 45U },	----
3282	{ Mips::D14_64, 46U },	----
3283	{ Mips::D15_64, 47U },	----
3284	{ Mips::D16_64, 48U },	----
3285	{ Mips::D17_64, 49U },	----
3286	{ Mips::D18_64, 50U },	----
3287	{ Mips::D19_64, 51U },	----
3288	{ Mips::D20_64, 52U },	----
3289	{ Mips::D21_64, 53U },	----
3290	{ Mips::D22_64, 54U },	----
3291	{ Mips::D23_64, 55U },	----
3292	{ Mips::D24_64, 56U },	----
3293	{ Mips::D25_64, 57U },	----
3294	{ Mips::D26_64, 58U },	----
3295	{ Mips::D27_64, 59U },	----
3296	{ Mips::D28_64, 60U },	----
3297	{ Mips::D29_64, 61U },	----
3298	{ Mips::D30_64, 62U },	----
3299	{ Mips::D31_64, 63U },	----
3300	{ Mips::K0_64, 26U },	----
3301	{ Mips::K1_64, 27U },	----
3302	{ Mips::S0_64, 16U },	----
3303	{ Mips::S1_64, 17U },	----
3304	{ Mips::S2_64, 18U },	----
3305	{ Mips::S3_64, 19U },	----
3306	{ Mips::S4_64, 20U },	----
3307	{ Mips::S5_64, 21U },	----
3308	{ Mips::S6_64, 22U },	----
3309	{ Mips::S7_64, 23U },	----
3310	{ Mips::T0_64, 8U },	----
3311	{ Mips::T1_64, 9U },	----
3312	{ Mips::T2_64, 10U },	----
3313	{ Mips::T3_64, 11U },	----
3314	{ Mips::T4_64, 12U },	----
3315	{ Mips::T5_64, 13U },	----
3316	{ Mips::T6_64, 14U },	----
3317	{ Mips::T7_64, 15U },	----
3318	{ Mips::T8_64, 24U },	----
3319	{ Mips::T9_64, 25U },	----
3320	{ Mips::V0_64, 2U },	----
3321	{ Mips::V1_64, 3U },	----
3322	};	----
3323	extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);	----
3324		----
3325	extern const uint16_t MipsRegEncodingTable[] = {	----
3326	0,	----
3327	1,	----
3328	0,	----
3329	0,	----
3330	0,	----
3331	0,	----
3332	0,	----
3333	0,	----
3334	30,	----
3335	28,	----
3336	2,	----
3337	1,	----
3338	0,	----
3339	6,	----
3340	4,	----
3341	5,	----
3342	3,	----
3343	7,	----
3344	0,	----
3345	31,	----
3346	29,	----
3347	0,	----
3348	4,	----
3349	5,	----
3350	6,	----
3351	7,	----
3352	0,	----
3353	1,	----
3354	2,	----
3355	3,	----
3356	1,	----
3357	0,	----
3358	1,	----
3359	2,	----
3360	3,	----
3361	4,	----
3362	5,	----
3363	6,	----
3364	7,	----
3365	8,	----
3366	9,	----
3367	0,	----
3368	1,	----
3369	2,	----
3370	3,	----
3371	4,	----
3372	5,	----
3373	6,	----
3374	7,	----
3375	8,	----
3376	9,	----
3377	0,	----
3378	1,	----
3379	2,	----
3380	3,	----
3381	4,	----
3382	5,	----
3383	6,	----
3384	7,	----
3385	8,	----
3386	9,	----
3387	10,	----
3388	11,	----
3389	12,	----
3390	13,	----
3391	14,	----
3392	15,	----
3393	16,	----
3394	17,	----
3395	18,	----
3396	19,	----
3397	20,	----
3398	21,	----
3399	22,	----
3400	23,	----
3401	24,	----
3402	25,	----
3403	26,	----
3404	27,	----
3405	28,	----
3406	29,	----
3407	30,	----
3408	31,	----
3409	10,	----
3410	11,	----
3411	12,	----
3412	13,	----
3413	14,	----
3414	15,	----
3415	16,	----
3416	17,	----
3417	18,	----
3418	19,	----
3419	20,	----
3420	21,	----
3421	22,	----
3422	23,	----
3423	24,	----
3424	25,	----
3425	26,	----
3426	27,	----
3427	28,	----
3428	29,	----
3429	30,	----
3430	31,	----
3431	10,	----
3432	11,	----
3433	12,	----
3434	13,	----
3435	14,	----
3436	15,	----
3437	16,	----
3438	17,	----
3439	18,	----
3440	19,	----
3441	20,	----
3442	21,	----
3443	22,	----
3444	23,	----
3445	24,	----
3446	25,	----
3447	26,	----
3448	27,	----
3449	28,	----
3450	29,	----
3451	30,	----
3452	31,	----
3453	0,	----
3454	2,	----
3455	4,	----
3456	6,	----
3457	8,	----
3458	10,	----
3459	12,	----
3460	14,	----
3461	16,	----
3462	18,	----
3463	20,	----
3464	22,	----
3465	24,	----
3466	26,	----
3467	28,	----
3468	30,	----
3469	0,	----
3470	0,	----
3471	0,	----
3472	0,	----
3473	0,	----
3474	1,	----
3475	2,	----
3476	3,	----
3477	4,	----
3478	5,	----
3479	6,	----
3480	7,	----
3481	8,	----
3482	9,	----
3483	10,	----
3484	11,	----
3485	12,	----
3486	13,	----
3487	14,	----
3488	15,	----
3489	16,	----
3490	17,	----
3491	18,	----
3492	19,	----
3493	20,	----
3494	21,	----
3495	22,	----
3496	23,	----
3497	24,	----
3498	25,	----
3499	26,	----
3500	27,	----
3501	28,	----
3502	29,	----
3503	30,	----
3504	31,	----
3505	0,	----
3506	1,	----
3507	2,	----
3508	3,	----
3509	4,	----
3510	5,	----
3511	6,	----
3512	7,	----
3513	0,	----
3514	1,	----
3515	2,	----
3516	3,	----
3517	4,	----
3518	5,	----
3519	6,	----
3520	7,	----
3521	8,	----
3522	9,	----
3523	10,	----
3524	11,	----
3525	12,	----
3526	13,	----
3527	14,	----
3528	15,	----
3529	16,	----
3530	17,	----
3531	18,	----
3532	19,	----
3533	20,	----
3534	21,	----
3535	22,	----
3536	23,	----
3537	24,	----
3538	25,	----
3539	26,	----
3540	27,	----
3541	28,	----
3542	29,	----
3543	30,	----
3544	31,	----
3545	30,	----
3546	0,	----
3547	1,	----
3548	2,	----
3549	3,	----
3550	4,	----
3551	5,	----
3552	6,	----
3553	7,	----
3554	8,	----
3555	9,	----
3556	10,	----
3557	11,	----
3558	12,	----
3559	13,	----
3560	14,	----
3561	15,	----
3562	16,	----
3563	17,	----
3564	18,	----
3565	19,	----
3566	20,	----
3567	21,	----
3568	22,	----
3569	23,	----
3570	24,	----
3571	25,	----
3572	26,	----
3573	27,	----
3574	28,	----
3575	29,	----
3576	30,	----
3577	31,	----
3578	28,	----
3579	0,	----
3580	1,	----
3581	2,	----
3582	3,	----
3583	0,	----
3584	1,	----
3585	2,	----
3586	3,	----
3587	4,	----
3588	5,	----
3589	6,	----
3590	7,	----
3591	8,	----
3592	9,	----
3593	10,	----
3594	11,	----
3595	12,	----
3596	13,	----
3597	14,	----
3598	15,	----
3599	16,	----
3600	17,	----
3601	18,	----
3602	19,	----
3603	20,	----
3604	21,	----
3605	22,	----
3606	23,	----
3607	24,	----
3608	25,	----
3609	26,	----
3610	27,	----
3611	28,	----
3612	29,	----
3613	30,	----
3614	31,	----
3615	26,	----
3616	27,	----
3617	0,	----
3618	1,	----
3619	2,	----
3620	3,	----
3621	0,	----
3622	1,	----
3623	2,	----
3624	8,	----
3625	9,	----
3626	10,	----
3627	11,	----
3628	12,	----
3629	13,	----
3630	14,	----
3631	15,	----
3632	16,	----
3633	17,	----
3634	18,	----
3635	19,	----
3636	20,	----
3637	21,	----
3638	22,	----
3639	23,	----
3640	24,	----
3641	25,	----
3642	26,	----
3643	27,	----
3644	28,	----
3645	29,	----
3646	30,	----
3647	31,	----
3648	0,	----
3649	1,	----
3650	2,	----
3651	31,	----
3652	16,	----
3653	17,	----
3654	18,	----
3655	19,	----
3656	20,	----
3657	21,	----
3658	22,	----
3659	23,	----
3660	29,	----
3661	8,	----
3662	9,	----
3663	10,	----
3664	11,	----
3665	12,	----
3666	13,	----
3667	14,	----
3668	15,	----
3669	24,	----
3670	25,	----
3671	2,	----
3672	3,	----
3673	0,	----
3674	1,	----
3675	2,	----
3676	3,	----
3677	4,	----
3678	5,	----
3679	6,	----
3680	7,	----
3681	8,	----
3682	9,	----
3683	10,	----
3684	11,	----
3685	12,	----
3686	13,	----
3687	14,	----
3688	15,	----
3689	16,	----
3690	17,	----
3691	18,	----
3692	19,	----
3693	20,	----
3694	21,	----
3695	22,	----
3696	23,	----
3697	24,	----
3698	25,	----
3699	26,	----
3700	27,	----
3701	28,	----
3702	29,	----
3703	30,	----
3704	31,	----
3705	0,	----
3706	4,	----
3707	5,	----
3708	6,	----
3709	7,	----
3710	0,	----
3711	0,	----
3712	1,	----
3713	2,	----
3714	3,	----
3715	4,	----
3716	5,	----
3717	6,	----
3718	7,	----
3719	8,	----
3720	9,	----
3721	10,	----
3722	11,	----
3723	12,	----
3724	13,	----
3725	14,	----
3726	15,	----
3727	16,	----
3728	17,	----
3729	18,	----
3730	19,	----
3731	20,	----
3732	21,	----
3733	22,	----
3734	23,	----
3735	24,	----
3736	25,	----
3737	26,	----
3738	27,	----
3739	28,	----
3740	29,	----
3741	30,	----
3742	31,	----
3743	0,	----
3744	0,	----
3745	26,	----
3746	27,	----
3747	0,	----
3748	16,	----
3749	17,	----
3750	18,	----
3751	19,	----
3752	20,	----
3753	21,	----
3754	22,	----
3755	23,	----
3756	8,	----
3757	9,	----
3758	10,	----
3759	11,	----
3760	12,	----
3761	13,	----
3762	14,	----
3763	15,	----
3764	24,	----
3765	25,	----
3766	2,	----
3767	3,	----
3768	};	----
3769	static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3770	RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3771	MipsSubRegIdxRanges, MipsRegEncodingTable);	----
3772		----
3773	switch (DwarfFlavour) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3774	default:	0
3775	llvm_unreachable("Unknown DWARF flavour");	0
3776	case 0:	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3777	RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3778	break;	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3779	}	----
3780	switch (EHFlavour) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3781	default:	0
3782	llvm_unreachable("Unknown DWARF flavour");	0
3783	case 0:	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3784	RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3785	break;	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3786	}	----
3787	switch (DwarfFlavour) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3788	default:	0
3789	llvm_unreachable("Unknown DWARF flavour");	0
3790	case 0:	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3791	RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3792	break;	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3793	}	----
3794	switch (EHFlavour) {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3795	default:	0
3796	llvm_unreachable("Unknown DWARF flavour");	0
3797	case 0:	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3798	RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3799	break;	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3800	}	----
3801	}	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
3802		----
3803	} // end namespace llvm	----
3804		----
3805	#endif // GET_REGINFO_MC_DESC	----
3806		----
3807	/===- TableGen'erated file -------------------------------------- C++ --===\	----
3808	\|* *\|	----
3809	\|* Register Information Header Fragment *\|	----
3810	\|* *\|	----
3811	\|* Automatically generated file, do not edit! *\|	----
3812	\|* *\|	----
3813	\===----------------------------------------------------------------------===/	----
3814		----
3815		----
3816	#ifdef GET_REGINFO_HEADER	----
3817	#undef GET_REGINFO_HEADER	----
3818		----
3819	#include "llvm/CodeGen/TargetRegisterInfo.h"	----
3820		----
3821	namespace llvm {	----
3822		----
3823	class MipsFrameLowering;	----
3824		----
3825	struct MipsGenRegisterInfo : public TargetRegisterInfo {	----
3826	explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,	----
3827	unsigned PC = 0, unsigned HwMode = 0);	----
3828	unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;	----
3829	LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	----
3830	LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	----
3831	const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;	----
3832	const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;	----
3833	const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;	----
3834	unsigned getRegUnitWeight(unsigned RegUnit) const override;	----
3835	unsigned getNumRegPressureSets() const override;	----
3836	const char *getRegPressureSetName(unsigned Idx) const override;	----
3837	unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;	----
3838	const int getRegClassPressureSets(const TargetRegisterClass RC) const override;	----
3839	const int *getRegUnitPressureSets(unsigned RegUnit) const override;	----
3840	ArrayRef getRegMaskNames() const override;	----
3841	ArrayRef getRegMasks() const override;	----
3842	bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;	----
3843	bool isFixedRegister(const MachineFunction &, MCRegister) const override;	----
3844	bool isArgumentRegister(const MachineFunction &, MCRegister) const override;	----
3845	bool isConstantPhysReg(MCRegister PhysReg) const override final;	----
3846	/// Devirtualized TargetFrameLowering.	----
3847	static const MipsFrameLowering *getFrameLowering(	----
3848	const MachineFunction &MF);	----
3849	};	----
3850		----
3851	namespace Mips { // Register classes	----
3852	extern const TargetRegisterClass MSA128F16RegClass;	----
3853	extern const TargetRegisterClass CCRRegClass;	----
3854	extern const TargetRegisterClass COP0RegClass;	----
3855	extern const TargetRegisterClass COP2RegClass;	----
3856	extern const TargetRegisterClass COP3RegClass;	----
3857	extern const TargetRegisterClass DSPRRegClass;	----
3858	extern const TargetRegisterClass FGR32RegClass;	----
3859	extern const TargetRegisterClass FGRCCRegClass;	----
3860	extern const TargetRegisterClass GPR32RegClass;	----
3861	extern const TargetRegisterClass HWRegsRegClass;	----
3862	extern const TargetRegisterClass MSACtrlRegClass;	----
3863	extern const TargetRegisterClass GPR32NONZERORegClass;	----
3864	extern const TargetRegisterClass CPU16RegsPlusSPRegClass;	----
3865	extern const TargetRegisterClass CPU16RegsRegClass;	----
3866	extern const TargetRegisterClass FCCRegClass;	----
3867	extern const TargetRegisterClass GPRMM16RegClass;	----
3868	extern const TargetRegisterClass GPRMM16MovePRegClass;	----
3869	extern const TargetRegisterClass GPRMM16ZeroRegClass;	----
3870	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;	----
3871	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;	----
3872	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;	----
3873	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;	----
3874	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;	----
3875	extern const TargetRegisterClass HI32DSPRegClass;	----
3876	extern const TargetRegisterClass LO32DSPRegClass;	----
3877	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	----
3878	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;	----
3879	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	----
3880	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	----
3881	extern const TargetRegisterClass CPURARegRegClass;	----
3882	extern const TargetRegisterClass CPUSPRegRegClass;	----
3883	extern const TargetRegisterClass DSPCCRegClass;	----
3884	extern const TargetRegisterClass GP32RegClass;	----
3885	extern const TargetRegisterClass GPR32ZERORegClass;	----
3886	extern const TargetRegisterClass HI32RegClass;	----
3887	extern const TargetRegisterClass LO32RegClass;	----
3888	extern const TargetRegisterClass SP32RegClass;	----
3889	extern const TargetRegisterClass FGR64RegClass;	----
3890	extern const TargetRegisterClass GPR64RegClass;	----
3891	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;	----
3892	extern const TargetRegisterClass AFGR64RegClass;	----
3893	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;	----
3894	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;	----
3895	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;	----
3896	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;	----
3897	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;	----
3898	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;	----
3899	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;	----
3900	extern const TargetRegisterClass ACC64DSPRegClass;	----
3901	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;	----
3902	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;	----
3903	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	----
3904	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;	----
3905	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	----
3906	extern const TargetRegisterClass OCTEON_MPLRegClass;	----
3907	extern const TargetRegisterClass OCTEON_PRegClass;	----
3908	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	----
3909	extern const TargetRegisterClass ACC64RegClass;	----
3910	extern const TargetRegisterClass GP64RegClass;	----
3911	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;	----
3912	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;	----
3913	extern const TargetRegisterClass HI64RegClass;	----
3914	extern const TargetRegisterClass LO64RegClass;	----
3915	extern const TargetRegisterClass SP64RegClass;	----
3916	extern const TargetRegisterClass MSA128BRegClass;	----
3917	extern const TargetRegisterClass MSA128DRegClass;	----
3918	extern const TargetRegisterClass MSA128HRegClass;	----
3919	extern const TargetRegisterClass MSA128WRegClass;	----
3920	extern const TargetRegisterClass MSA128WEvensRegClass;	----
3921	extern const TargetRegisterClass ACC128RegClass;	----
3922	} // end namespace Mips	----
3923		----
3924	} // end namespace llvm	----
3925		----
3926	#endif // GET_REGINFO_HEADER	----
3927		----
3928	/===- TableGen'erated file -------------------------------------- C++ --===\	----
3929	\|* *\|	----
3930	\|* Target Register and Register Classes Information *\|	----
3931	\|* *\|	----
3932	\|* Automatically generated file, do not edit! *\|	----
3933	\|* *\|	----
3934	\===----------------------------------------------------------------------===/	----
3935		----
3936		----
3937	#ifdef GET_REGINFO_TARGET_DESC	----
3938	#undef GET_REGINFO_TARGET_DESC	----
3939		----
3940	namespace llvm {	----
3941		----
3942	extern const MCRegisterClass MipsMCRegisterClasses[];	----
3943		----
3944	static const MVT::SimpleValueType VTLists[] = {	----
3945	/* 0 */ MVT::i32, MVT::Other,	----
3946	/* 2 */ MVT::i64, MVT::Other,	----
3947	/* 4 */ MVT::f16, MVT::Other,	----
3948	/* 6 */ MVT::f32, MVT::Other,	----
3949	/* 8 */ MVT::f64, MVT::Other,	----
3950	/* 10 */ MVT::v16i8, MVT::Other,	----
3951	/* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,	----
3952	/* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,	----
3953	/* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,	----
3954	/* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,	----
3955	/* 24 */ MVT::Untyped, MVT::Other,	----
3956	};	----
3957		----
3958	static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };	----
3959		----
3960		----
3961	static const LaneBitmask SubRegIndexLaneMaskTable[] = {	----
3962	LaneBitmask::getAll(),	----
3963	LaneBitmask(0x0000000000000001), // sub_32	----
3964	LaneBitmask(0x0000000000000041), // sub_64	----
3965	LaneBitmask(0x0000000000000002), // sub_dsp16_19	----
3966	LaneBitmask(0x0000000000000004), // sub_dsp20	----
3967	LaneBitmask(0x0000000000000008), // sub_dsp21	----
3968	LaneBitmask(0x0000000000000010), // sub_dsp22	----
3969	LaneBitmask(0x0000000000000020), // sub_dsp23	----
3970	LaneBitmask(0x0000000000000040), // sub_hi	----
3971	LaneBitmask(0x0000000000000001), // sub_lo	----
3972	LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32	----
3973	LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32	----
3974	};	----
3975		----
3976		----
3977		----
3978	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {	----
3979	// Mode = 0 (Default)	----
3980	{ 16, 16, 128, VTLists+4 }, // MSA128F16	----
3981	{ 32, 32, 32, VTLists+0 }, // CCR	----
3982	{ 32, 32, 32, VTLists+0 }, // COP0	----
3983	{ 32, 32, 32, VTLists+0 }, // COP2	----
3984	{ 32, 32, 32, VTLists+0 }, // COP3	----
3985	{ 32, 32, 32, VTLists+12 }, // DSPR	----
3986	{ 32, 32, 32, VTLists+6 }, // FGR32	----
3987	{ 32, 32, 32, VTLists+0 }, // FGRCC	----
3988	{ 32, 32, 32, VTLists+0 }, // GPR32	----
3989	{ 32, 32, 32, VTLists+0 }, // HWRegs	----
3990	{ 32, 32, 32, VTLists+0 }, // MSACtrl	----
3991	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO	----
3992	{ 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP	----
3993	{ 32, 32, 32, VTLists+0 }, // CPU16Regs	----
3994	{ 32, 32, 32, VTLists+0 }, // FCC	----
3995	{ 32, 32, 32, VTLists+0 }, // GPRMM16	----
3996	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP	----
3997	{ 32, 32, 32, VTLists+0 }, // GPRMM16Zero	----
3998	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero	----
3999	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP	----
4000	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond	----
4001	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP	----
4002	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero	----
4003	{ 32, 32, 32, VTLists+0 }, // HI32DSP	----
4004	{ 32, 32, 32, VTLists+0 }, // LO32DSP	----
4005	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond	----
4006	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst	----
4007	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
4008	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
4009	{ 32, 32, 32, VTLists+0 }, // CPURAReg	----
4010	{ 32, 32, 32, VTLists+0 }, // CPUSPReg	----
4011	{ 32, 32, 32, VTLists+12 }, // DSPCC	----
4012	{ 32, 32, 32, VTLists+0 }, // GP32	----
4013	{ 32, 32, 32, VTLists+0 }, // GPR32ZERO	----
4014	{ 32, 32, 32, VTLists+0 }, // HI32	----
4015	{ 32, 32, 32, VTLists+0 }, // LO32	----
4016	{ 32, 32, 32, VTLists+0 }, // SP32	----
4017	{ 64, 64, 64, VTLists+8 }, // FGR64	----
4018	{ 64, 64, 64, VTLists+2 }, // GPR64	----
4019	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO	----
4020	{ 64, 64, 64, VTLists+8 }, // AFGR64	----
4021	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP	----
4022	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs	----
4023	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP	----
4024	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero	----
4025	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	----
4026	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	----
4027	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	----
4028	{ 64, 64, 64, VTLists+24 }, // ACC64DSP	----
4029	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	----
4030	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	----
4031	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	----
4032	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	----
4033	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
4034	{ 64, 64, 64, VTLists+2 }, // OCTEON_MPL	----
4035	{ 64, 64, 64, VTLists+2 }, // OCTEON_P	----
4036	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
4037	{ 64, 64, 64, VTLists+24 }, // ACC64	----
4038	{ 64, 64, 64, VTLists+2 }, // GP64	----
4039	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg	----
4040	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO	----
4041	{ 64, 64, 64, VTLists+2 }, // HI64	----
4042	{ 64, 64, 64, VTLists+2 }, // LO64	----
4043	{ 64, 64, 64, VTLists+2 }, // SP64	----
4044	{ 128, 128, 128, VTLists+10 }, // MSA128B	----
4045	{ 128, 128, 128, VTLists+21 }, // MSA128D	----
4046	{ 128, 128, 128, VTLists+15 }, // MSA128H	----
4047	{ 128, 128, 128, VTLists+18 }, // MSA128W	----
4048	{ 128, 128, 128, VTLists+18 }, // MSA128WEvens	----
4049	{ 128, 128, 128, VTLists+24 }, // ACC128	----
4050	};	----
4051		----
4052	static const TargetRegisterClass *const NullRegClasses[] = { nullptr };	----
4053		----
4054	static const uint32_t MSA128F16SubClassMask[] = {	----
4055	0x00000001, 0x00000000, 0x0000001f,	----
4056	};	----
4057		----
4058	static const uint32_t CCRSubClassMask[] = {	----
4059	0x00000002, 0x00000000, 0x00000000,	----
4060	};	----
4061		----
4062	static const uint32_t COP0SubClassMask[] = {	----
4063	0x00000004, 0x00000000, 0x00000000,	----
4064	};	----
4065		----
4066	static const uint32_t COP2SubClassMask[] = {	----
4067	0x00000008, 0x00000000, 0x00000000,	----
4068	};	----
4069		----
4070	static const uint32_t COP3SubClassMask[] = {	----
4071	0x00000010, 0x00000000, 0x00000000,	----
4072	};	----
4073		----
4074	static const uint32_t DSPRSubClassMask[] = {	----
4075	0x7e7fb920, 0x00000013, 0x00000000,	----
4076	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	----
4077	};	----
4078		----
4079	static const uint32_t FGR32SubClassMask[] = {	----
4080	0x000000c0, 0x00000000, 0x00000000,	----
4081	0x00000000, 0x00000100, 0x00000000, // sub_hi	----
4082	0x00000001, 0x00000120, 0x0000001f, // sub_lo	----
4083	};	----
4084		----
4085	static const uint32_t FGRCCSubClassMask[] = {	----
4086	0x000000c0, 0x00000000, 0x00000000,	----
4087	0x00000000, 0x00000100, 0x00000000, // sub_hi	----
4088	0x00000001, 0x00000120, 0x0000001f, // sub_lo	----
4089	};	----
4090		----
4091	static const uint32_t GPR32SubClassMask[] = {	----
4092	0x7e7fb900, 0x00000013, 0x00000000,	----
4093	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	----
4094	};	----
4095		----
4096	static const uint32_t HWRegsSubClassMask[] = {	----
4097	0x00000200, 0x00000000, 0x00000000,	----
4098	};	----
4099		----
4100	static const uint32_t MSACtrlSubClassMask[] = {	----
4101	0x00000400, 0x00000000, 0x00000000,	----
4102	};	----
4103		----
4104	static const uint32_t GPR32NONZEROSubClassMask[] = {	----
4105	0x7e3cb800, 0x00000011, 0x00000000,	----
4106	0x00000000, 0x8d3ae680, 0x00000000, // sub_32	----
4107	};	----
4108		----
4109	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {	----
4110	0x5e24b000, 0x00000010, 0x00000000,	----
4111	0x00000000, 0x813a2600, 0x00000000, // sub_32	----
4112	};	----
4113		----
4114	static const uint32_t CPU16RegsSubClassMask[] = {	----
4115	0x1e24a000, 0x00000000, 0x00000000,	----
4116	0x00000000, 0x013a2400, 0x00000000, // sub_32	----
4117	};	----
4118		----
4119	static const uint32_t FCCSubClassMask[] = {	----
4120	0x00004000, 0x00000000, 0x00000000,	----
4121	};	----
4122		----
4123	static const uint32_t GPRMM16SubClassMask[] = {	----
4124	0x1e248000, 0x00000000, 0x00000000,	----
4125	0x00000000, 0x013a2400, 0x00000000, // sub_32	----
4126	};	----
4127		----
4128	static const uint32_t GPRMM16MovePSubClassMask[] = {	----
4129	0x08690000, 0x00000002, 0x00000000,	----
4130	0x00000000, 0x10264800, 0x00000000, // sub_32	----
4131	};	----
4132		----
4133	static const uint32_t GPRMM16ZeroSubClassMask[] = {	----
4134	0x1e460000, 0x00000002, 0x00000000,	----
4135	0x00000000, 0x113c3000, 0x00000000, // sub_32	----
4136	};	----
4137		----
4138	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	----
4139	0x1e040000, 0x00000000, 0x00000000,	----
4140	0x00000000, 0x01382000, 0x00000000, // sub_32	----
4141	};	----
4142		----
4143	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	----
4144	0x08280000, 0x00000000, 0x00000000,	----
4145	0x00000000, 0x00224000, 0x00000000, // sub_32	----
4146	};	----
4147		----
4148	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {	----
4149	0x12100000, 0x00000000, 0x00000000,	----
4150	0x00000000, 0x01088000, 0x00000000, // sub_32	----
4151	};	----
4152		----
4153	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	----
4154	0x08200000, 0x00000000, 0x00000000,	----
4155	0x00000000, 0x00220000, 0x00000000, // sub_32	----
4156	};	----
4157		----
4158	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	----
4159	0x08400000, 0x00000002, 0x00000000,	----
4160	0x00000000, 0x10240000, 0x00000000, // sub_32	----
4161	};	----
4162		----
4163	static const uint32_t HI32DSPSubClassMask[] = {	----
4164	0x00800000, 0x00000004, 0x00000000,	----
4165	0x00000000, 0x20000000, 0x00000000, // sub_32	----
4166	0x00000000, 0x02010000, 0x00000000, // sub_hi	----
4167	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	----
4168	};	----
4169		----
4170	static const uint32_t LO32DSPSubClassMask[] = {	----
4171	0x01000000, 0x00000008, 0x00000000,	----
4172	0x00000000, 0x40000000, 0x00000020, // sub_32	----
4173	0x00000000, 0x02010000, 0x00000000, // sub_lo	----
4174	};	----
4175		----
4176	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	----
4177	0x12000000, 0x00000000, 0x00000000,	----
4178	0x00000000, 0x01080000, 0x00000000, // sub_32	----
4179	};	----
4180		----
4181	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {	----
4182	0x14000000, 0x00000000, 0x00000000,	----
4183	0x00000000, 0x01100000, 0x00000000, // sub_32	----
4184	};	----
4185		----
4186	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	----
4187	0x08000000, 0x00000000, 0x00000000,	----
4188	0x00000000, 0x00200000, 0x00000000, // sub_32	----
4189	};	----
4190		----
4191	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	----
4192	0x10000000, 0x00000000, 0x00000000,	----
4193	0x00000000, 0x01000000, 0x00000000, // sub_32	----
4194	};	----
4195		----
4196	static const uint32_t CPURARegSubClassMask[] = {	----
4197	0x20000000, 0x00000000, 0x00000000,	----
4198	0x00000000, 0x08000000, 0x00000000, // sub_32	----
4199	};	----
4200		----
4201	static const uint32_t CPUSPRegSubClassMask[] = {	----
4202	0x40000000, 0x00000010, 0x00000000,	----
4203	0x00000000, 0x80000000, 0x00000000, // sub_32	----
4204	};	----
4205		----
4206	static const uint32_t DSPCCSubClassMask[] = {	----
4207	0x80000000, 0x00000000, 0x00000000,	----
4208	};	----
4209		----
4210	static const uint32_t GP32SubClassMask[] = {	----
4211	0x00000000, 0x00000001, 0x00000000,	----
4212	0x00000000, 0x04000000, 0x00000000, // sub_32	----
4213	};	----
4214		----
4215	static const uint32_t GPR32ZEROSubClassMask[] = {	----
4216	0x00000000, 0x00000002, 0x00000000,	----
4217	0x00000000, 0x10000000, 0x00000000, // sub_32	----
4218	};	----
4219		----
4220	static const uint32_t HI32SubClassMask[] = {	----
4221	0x00000000, 0x00000004, 0x00000000,	----
4222	0x00000000, 0x20000000, 0x00000000, // sub_32	----
4223	0x00000000, 0x02000000, 0x00000000, // sub_hi	----
4224	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	----
4225	};	----
4226		----
4227	static const uint32_t LO32SubClassMask[] = {	----
4228	0x00000000, 0x00000008, 0x00000000,	----
4229	0x00000000, 0x40000000, 0x00000020, // sub_32	----
4230	0x00000000, 0x02000000, 0x00000000, // sub_lo	----
4231	};	----
4232		----
4233	static const uint32_t SP32SubClassMask[] = {	----
4234	0x00000000, 0x00000010, 0x00000000,	----
4235	0x00000000, 0x80000000, 0x00000000, // sub_32	----
4236	};	----
4237		----
4238	static const uint32_t FGR64SubClassMask[] = {	----
4239	0x00000000, 0x00000020, 0x00000000,	----
4240	0x00000001, 0x00000000, 0x0000001f, // sub_64	----
4241	};	----
4242		----
4243	static const uint32_t GPR64SubClassMask[] = {	----
4244	0x00000000, 0x9d3efec0, 0x00000000,	----
4245	};	----
4246		----
4247	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {	----
4248	0x00000000, 0x8d3ae680, 0x00000000,	----
4249	};	----
4250		----
4251	static const uint32_t AFGR64SubClassMask[] = {	----
4252	0x00000000, 0x00000100, 0x00000000,	----
4253	};	----
4254		----
4255	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {	----
4256	0x00000000, 0x813a2600, 0x00000000,	----
4257	};	----
4258		----
4259	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {	----
4260	0x00000000, 0x013a2400, 0x00000000,	----
4261	};	----
4262		----
4263	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {	----
4264	0x00000000, 0x10264800, 0x00000000,	----
4265	};	----
4266		----
4267	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {	----
4268	0x00000000, 0x113c3000, 0x00000000,	----
4269	};	----
4270		----
4271	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	----
4272	0x00000000, 0x01382000, 0x00000000,	----
4273	};	----
4274		----
4275	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	----
4276	0x00000000, 0x00224000, 0x00000000,	----
4277	};	----
4278		----
4279	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {	----
4280	0x00000000, 0x01088000, 0x00000000,	----
4281	};	----
4282		----
4283	static const uint32_t ACC64DSPSubClassMask[] = {	----
4284	0x00000000, 0x02010000, 0x00000000,	----
4285	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	----
4286	};	----
4287		----
4288	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	----
4289	0x00000000, 0x00220000, 0x00000000,	----
4290	};	----
4291		----
4292	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	----
4293	0x00000000, 0x10240000, 0x00000000,	----
4294	};	----
4295		----
4296	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	----
4297	0x00000000, 0x01080000, 0x00000000,	----
4298	};	----
4299		----
4300	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {	----
4301	0x00000000, 0x01100000, 0x00000000,	----
4302	};	----
4303		----
4304	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	----
4305	0x00000000, 0x00200000, 0x00000000,	----
4306	};	----
4307		----
4308	static const uint32_t OCTEON_MPLSubClassMask[] = {	----
4309	0x00000000, 0x00400000, 0x00000000,	----
4310	};	----
4311		----
4312	static const uint32_t OCTEON_PSubClassMask[] = {	----
4313	0x00000000, 0x00800000, 0x00000000,	----
4314	};	----
4315		----
4316	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	----
4317	0x00000000, 0x01000000, 0x00000000,	----
4318	};	----
4319		----
4320	static const uint32_t ACC64SubClassMask[] = {	----
4321	0x00000000, 0x02000000, 0x00000000,	----
4322	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	----
4323	};	----
4324		----
4325	static const uint32_t GP64SubClassMask[] = {	----
4326	0x00000000, 0x04000000, 0x00000000,	----
4327	};	----
4328		----
4329	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {	----
4330	0x00000000, 0x08000000, 0x00000000,	----
4331	};	----
4332		----
4333	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {	----
4334	0x00000000, 0x10000000, 0x00000000,	----
4335	};	----
4336		----
4337	static const uint32_t HI64SubClassMask[] = {	----
4338	0x00000000, 0x20000000, 0x00000000,	----
4339	0x00000000, 0x00000000, 0x00000020, // sub_hi	----
4340	};	----
4341		----
4342	static const uint32_t LO64SubClassMask[] = {	----
4343	0x00000000, 0x40000000, 0x00000000,	----
4344	0x00000000, 0x00000000, 0x00000020, // sub_lo	----
4345	};	----
4346		----
4347	static const uint32_t SP64SubClassMask[] = {	----
4348	0x00000000, 0x80000000, 0x00000000,	----
4349	};	----
4350		----
4351	static const uint32_t MSA128BSubClassMask[] = {	----
4352	0x00000000, 0x00000000, 0x0000001f,	----
4353	};	----
4354		----
4355	static const uint32_t MSA128DSubClassMask[] = {	----
4356	0x00000000, 0x00000000, 0x0000001f,	----
4357	};	----
4358		----
4359	static const uint32_t MSA128HSubClassMask[] = {	----
4360	0x00000000, 0x00000000, 0x0000001f,	----
4361	};	----
4362		----
4363	static const uint32_t MSA128WSubClassMask[] = {	----
4364	0x00000000, 0x00000000, 0x0000001f,	----
4365	};	----
4366		----
4367	static const uint32_t MSA128WEvensSubClassMask[] = {	----
4368	0x00000000, 0x00000000, 0x00000010,	----
4369	};	----
4370		----
4371	static const uint32_t ACC128SubClassMask[] = {	----
4372	0x00000000, 0x00000000, 0x00000020,	----
4373	};	----
4374		----
4375	static const uint16_t SuperRegIdxSeqs[] = {	----
4376	/* 0 */ 1, 0,	----
4377	/* 2 */ 2, 0,	----
4378	/* 4 */ 8, 0,	----
4379	/* 6 */ 1, 9, 0,	----
4380	/* 9 */ 8, 9, 0,	----
4381	/* 12 */ 1, 8, 10, 0,	----
4382	/* 16 */ 11, 0,	----
4383	};	----
4384		----
4385	static const TargetRegisterClass *const FGR32Superclasses[] = {	----
4386	&Mips::FGRCCRegClass,	----
4387	nullptr	----
4388	};	----
4389		----
4390	static const TargetRegisterClass *const FGRCCSuperclasses[] = {	----
4391	&Mips::FGR32RegClass,	----
4392	nullptr	----
4393	};	----
4394		----
4395	static const TargetRegisterClass *const GPR32Superclasses[] = {	----
4396	&Mips::DSPRRegClass,	----
4397	nullptr	----
4398	};	----
4399		----
4400	static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {	----
4401	&Mips::DSPRRegClass,	----
4402	&Mips::GPR32RegClass,	----
4403	nullptr	----
4404	};	----
4405		----
4406	static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {	----
4407	&Mips::DSPRRegClass,	----
4408	&Mips::GPR32RegClass,	----
4409	&Mips::GPR32NONZERORegClass,	----
4410	nullptr	----
4411	};	----
4412		----
4413	static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {	----
4414	&Mips::DSPRRegClass,	----
4415	&Mips::GPR32RegClass,	----
4416	&Mips::GPR32NONZERORegClass,	----
4417	&Mips::CPU16RegsPlusSPRegClass,	----
4418	nullptr	----
4419	};	----
4420		----
4421	static const TargetRegisterClass *const GPRMM16Superclasses[] = {	----
4422	&Mips::DSPRRegClass,	----
4423	&Mips::GPR32RegClass,	----
4424	&Mips::GPR32NONZERORegClass,	----
4425	&Mips::CPU16RegsPlusSPRegClass,	----
4426	&Mips::CPU16RegsRegClass,	----
4427	nullptr	----
4428	};	----
4429		----
4430	static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {	----
4431	&Mips::DSPRRegClass,	----
4432	&Mips::GPR32RegClass,	----
4433	nullptr	----
4434	};	----
4435		----
4436	static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {	----
4437	&Mips::DSPRRegClass,	----
4438	&Mips::GPR32RegClass,	----
4439	nullptr	----
4440	};	----
4441		----
4442	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	----
4443	&Mips::DSPRRegClass,	----
4444	&Mips::GPR32RegClass,	----
4445	&Mips::GPR32NONZERORegClass,	----
4446	&Mips::CPU16RegsPlusSPRegClass,	----
4447	&Mips::CPU16RegsRegClass,	----
4448	&Mips::GPRMM16RegClass,	----
4449	&Mips::GPRMM16ZeroRegClass,	----
4450	nullptr	----
4451	};	----
4452		----
4453	static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	----
4454	&Mips::DSPRRegClass,	----
4455	&Mips::GPR32RegClass,	----
4456	&Mips::GPR32NONZERORegClass,	----
4457	&Mips::GPRMM16MovePRegClass,	----
4458	nullptr	----
4459	};	----
4460		----
4461	static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {	----
4462	&Mips::DSPRRegClass,	----
4463	&Mips::GPR32RegClass,	----
4464	&Mips::GPR32NONZERORegClass,	----
4465	nullptr	----
4466	};	----
4467		----
4468	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	----
4469	&Mips::DSPRRegClass,	----
4470	&Mips::GPR32RegClass,	----
4471	&Mips::GPR32NONZERORegClass,	----
4472	&Mips::CPU16RegsPlusSPRegClass,	----
4473	&Mips::CPU16RegsRegClass,	----
4474	&Mips::GPRMM16RegClass,	----
4475	&Mips::GPRMM16MovePRegClass,	----
4476	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	----
4477	nullptr	----
4478	};	----
4479		----
4480	static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	----
4481	&Mips::DSPRRegClass,	----
4482	&Mips::GPR32RegClass,	----
4483	&Mips::GPRMM16MovePRegClass,	----
4484	&Mips::GPRMM16ZeroRegClass,	----
4485	nullptr	----
4486	};	----
4487		----
4488	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	----
4489	&Mips::DSPRRegClass,	----
4490	&Mips::GPR32RegClass,	----
4491	&Mips::GPR32NONZERORegClass,	----
4492	&Mips::CPU16RegsPlusSPRegClass,	----
4493	&Mips::CPU16RegsRegClass,	----
4494	&Mips::GPRMM16RegClass,	----
4495	&Mips::GPRMM16ZeroRegClass,	----
4496	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	----
4497	&Mips::GPRMM16MovePPairSecondRegClass,	----
4498	nullptr	----
4499	};	----
4500		----
4501	static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {	----
4502	&Mips::DSPRRegClass,	----
4503	&Mips::GPR32RegClass,	----
4504	&Mips::GPR32NONZERORegClass,	----
4505	&Mips::CPU16RegsPlusSPRegClass,	----
4506	&Mips::CPU16RegsRegClass,	----
4507	&Mips::GPRMM16RegClass,	----
4508	&Mips::GPRMM16ZeroRegClass,	----
4509	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	----
4510	nullptr	----
4511	};	----
4512		----
4513	static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	----
4514	&Mips::DSPRRegClass,	----
4515	&Mips::GPR32RegClass,	----
4516	&Mips::GPR32NONZERORegClass,	----
4517	&Mips::CPU16RegsPlusSPRegClass,	----
4518	&Mips::CPU16RegsRegClass,	----
4519	&Mips::GPRMM16RegClass,	----
4520	&Mips::GPRMM16MovePRegClass,	----
4521	&Mips::GPRMM16ZeroRegClass,	----
4522	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	----
4523	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	----
4524	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	----
4525	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
4526	nullptr	----
4527	};	----
4528		----
4529	static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	----
4530	&Mips::DSPRRegClass,	----
4531	&Mips::GPR32RegClass,	----
4532	&Mips::GPR32NONZERORegClass,	----
4533	&Mips::CPU16RegsPlusSPRegClass,	----
4534	&Mips::CPU16RegsRegClass,	----
4535	&Mips::GPRMM16RegClass,	----
4536	&Mips::GPRMM16ZeroRegClass,	----
4537	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	----
4538	&Mips::GPRMM16MovePPairSecondRegClass,	----
4539	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	----
4540	&Mips::GPRMM16MovePPairFirstRegClass,	----
4541	nullptr	----
4542	};	----
4543		----
4544	static const TargetRegisterClass *const CPURARegSuperclasses[] = {	----
4545	&Mips::DSPRRegClass,	----
4546	&Mips::GPR32RegClass,	----
4547	&Mips::GPR32NONZERORegClass,	----
4548	nullptr	----
4549	};	----
4550		----
4551	static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {	----
4552	&Mips::DSPRRegClass,	----
4553	&Mips::GPR32RegClass,	----
4554	&Mips::GPR32NONZERORegClass,	----
4555	&Mips::CPU16RegsPlusSPRegClass,	----
4556	nullptr	----
4557	};	----
4558		----
4559	static const TargetRegisterClass *const GP32Superclasses[] = {	----
4560	&Mips::DSPRRegClass,	----
4561	&Mips::GPR32RegClass,	----
4562	&Mips::GPR32NONZERORegClass,	----
4563	nullptr	----
4564	};	----
4565		----
4566	static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {	----
4567	&Mips::DSPRRegClass,	----
4568	&Mips::GPR32RegClass,	----
4569	&Mips::GPRMM16MovePRegClass,	----
4570	&Mips::GPRMM16ZeroRegClass,	----
4571	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
4572	nullptr	----
4573	};	----
4574		----
4575	static const TargetRegisterClass *const HI32Superclasses[] = {	----
4576	&Mips::HI32DSPRegClass,	----
4577	nullptr	----
4578	};	----
4579		----
4580	static const TargetRegisterClass *const LO32Superclasses[] = {	----
4581	&Mips::LO32DSPRegClass,	----
4582	nullptr	----
4583	};	----
4584		----
4585	static const TargetRegisterClass *const SP32Superclasses[] = {	----
4586	&Mips::DSPRRegClass,	----
4587	&Mips::GPR32RegClass,	----
4588	&Mips::GPR32NONZERORegClass,	----
4589	&Mips::CPU16RegsPlusSPRegClass,	----
4590	&Mips::CPUSPRegRegClass,	----
4591	nullptr	----
4592	};	----
4593		----
4594	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {	----
4595	&Mips::GPR64RegClass,	----
4596	nullptr	----
4597	};	----
4598		----
4599	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {	----
4600	&Mips::GPR64RegClass,	----
4601	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4602	nullptr	----
4603	};	----
4604		----
4605	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {	----
4606	&Mips::GPR64RegClass,	----
4607	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4608	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4609	nullptr	----
4610	};	----
4611		----
4612	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {	----
4613	&Mips::GPR64RegClass,	----
4614	nullptr	----
4615	};	----
4616		----
4617	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {	----
4618	&Mips::GPR64RegClass,	----
4619	nullptr	----
4620	};	----
4621		----
4622	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	----
4623	&Mips::GPR64RegClass,	----
4624	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4625	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4626	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4627	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4628	nullptr	----
4629	};	----
4630		----
4631	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	----
4632	&Mips::GPR64RegClass,	----
4633	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4634	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
4635	nullptr	----
4636	};	----
4637		----
4638	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {	----
4639	&Mips::GPR64RegClass,	----
4640	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4641	nullptr	----
4642	};	----
4643		----
4644	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	----
4645	&Mips::GPR64RegClass,	----
4646	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4647	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4648	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4649	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
4650	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	----
4651	nullptr	----
4652	};	----
4653		----
4654	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	----
4655	&Mips::GPR64RegClass,	----
4656	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
4657	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4658	nullptr	----
4659	};	----
4660		----
4661	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	----
4662	&Mips::GPR64RegClass,	----
4663	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4664	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4665	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4666	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4667	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	----
4668	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	----
4669	nullptr	----
4670	};	----
4671		----
4672	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {	----
4673	&Mips::GPR64RegClass,	----
4674	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4675	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4676	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4677	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4678	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	----
4679	nullptr	----
4680	};	----
4681		----
4682	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	----
4683	&Mips::GPR64RegClass,	----
4684	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4685	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4686	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4687	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
4688	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4689	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	----
4690	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	----
4691	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	----
4692	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
4693	nullptr	----
4694	};	----
4695		----
4696	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	----
4697	&Mips::GPR64RegClass,	----
4698	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4699	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4700	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
4701	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4702	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	----
4703	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	----
4704	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	----
4705	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	----
4706	nullptr	----
4707	};	----
4708		----
4709	static const TargetRegisterClass *const ACC64Superclasses[] = {	----
4710	&Mips::ACC64DSPRegClass,	----
4711	nullptr	----
4712	};	----
4713		----
4714	static const TargetRegisterClass *const GP64Superclasses[] = {	----
4715	&Mips::GPR64RegClass,	----
4716	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4717	nullptr	----
4718	};	----
4719		----
4720	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {	----
4721	&Mips::GPR64RegClass,	----
4722	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4723	nullptr	----
4724	};	----
4725		----
4726	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {	----
4727	&Mips::GPR64RegClass,	----
4728	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
4729	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
4730	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
4731	nullptr	----
4732	};	----
4733		----
4734	static const TargetRegisterClass *const SP64Superclasses[] = {	----
4735	&Mips::GPR64RegClass,	----
4736	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
4737	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
4738	nullptr	----
4739	};	----
4740		----
4741	static const TargetRegisterClass *const MSA128BSuperclasses[] = {	----
4742	&Mips::MSA128F16RegClass,	----
4743	&Mips::MSA128DRegClass,	----
4744	&Mips::MSA128HRegClass,	----
4745	&Mips::MSA128WRegClass,	----
4746	nullptr	----
4747	};	----
4748		----
4749	static const TargetRegisterClass *const MSA128DSuperclasses[] = {	----
4750	&Mips::MSA128F16RegClass,	----
4751	&Mips::MSA128BRegClass,	----
4752	&Mips::MSA128HRegClass,	----
4753	&Mips::MSA128WRegClass,	----
4754	nullptr	----
4755	};	----
4756		----
4757	static const TargetRegisterClass *const MSA128HSuperclasses[] = {	----
4758	&Mips::MSA128F16RegClass,	----
4759	&Mips::MSA128BRegClass,	----
4760	&Mips::MSA128DRegClass,	----
4761	&Mips::MSA128WRegClass,	----
4762	nullptr	----
4763	};	----
4764		----
4765	static const TargetRegisterClass *const MSA128WSuperclasses[] = {	----
4766	&Mips::MSA128F16RegClass,	----
4767	&Mips::MSA128BRegClass,	----
4768	&Mips::MSA128DRegClass,	----
4769	&Mips::MSA128HRegClass,	----
4770	nullptr	----
4771	};	----
4772		----
4773	static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {	----
4774	&Mips::MSA128F16RegClass,	----
4775	&Mips::MSA128BRegClass,	----
4776	&Mips::MSA128DRegClass,	----
4777	&Mips::MSA128HRegClass,	----
4778	&Mips::MSA128WRegClass,	----
4779	nullptr	----
4780	};	----
4781		----
4782		----
4783	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {	0
4784	const auto & S = MF.getSubtarget();	0
4785	return S.isABI_O32() && !S.useOddSPReg();	0
4786	}	----
4787		----
4788	static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) {	0
4789	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };	----
4790	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];	0
4791	const ArrayRef Order[] = {	----
4792	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0
4793	ArrayRef(AltOrder1)	----
4794	};	0
4795	const unsigned Select = FGR32AltOrderSelect(MF);	0
4796	assert(Select < 2);	0
4797	return Order[Select];	0
4798	}	----
4799		----
4800	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {	0
4801	const auto & S = MF.getSubtarget();	0
4802	return S.isABI_O32() && !S.useOddSPReg();	0
4803	}	----
4804		----
4805	static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) {	0
4806	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };	----
4807	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];	0
4808	const ArrayRef Order[] = {	----
4809	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0
4810	ArrayRef(AltOrder1)	----
4811	};	0
4812	const unsigned Select = FGR64AltOrderSelect(MF);	0
4813	assert(Select < 2);	0
4814	return Order[Select];	0
4815	}	----
4816		----
4817	namespace Mips { // Register class instances	----
4818	extern const TargetRegisterClass MSA128F16RegClass = {	----
4819	&MipsMCRegisterClasses[MSA128F16RegClassID],	----
4820	MSA128F16SubClassMask,	----
4821	SuperRegIdxSeqs + 1,	----
4822	LaneBitmask(0x0000000000000041),	----
4823	0,	----
4824	false,	----
4825	0x00, /* TSFlags */	----
4826	true, /* HasDisjunctSubRegs */	----
4827	false, /* CoveredBySubRegs */	----
4828	NullRegClasses,	----
4829	nullptr	----
4830	};	----
4831		----
4832	extern const TargetRegisterClass CCRRegClass = {	----
4833	&MipsMCRegisterClasses[CCRRegClassID],	----
4834	CCRSubClassMask,	----
4835	SuperRegIdxSeqs + 1,	----
4836	LaneBitmask(0x0000000000000001),	----
4837	0,	----
4838	false,	----
4839	0x00, /* TSFlags */	----
4840	false, /* HasDisjunctSubRegs */	----
4841	false, /* CoveredBySubRegs */	----
4842	NullRegClasses,	----
4843	nullptr	----
4844	};	----
4845		----
4846	extern const TargetRegisterClass COP0RegClass = {	----
4847	&MipsMCRegisterClasses[COP0RegClassID],	----
4848	COP0SubClassMask,	----
4849	SuperRegIdxSeqs + 1,	----
4850	LaneBitmask(0x0000000000000001),	----
4851	0,	----
4852	false,	----
4853	0x00, /* TSFlags */	----
4854	false, /* HasDisjunctSubRegs */	----
4855	false, /* CoveredBySubRegs */	----
4856	NullRegClasses,	----
4857	nullptr	----
4858	};	----
4859		----
4860	extern const TargetRegisterClass COP2RegClass = {	----
4861	&MipsMCRegisterClasses[COP2RegClassID],	----
4862	COP2SubClassMask,	----
4863	SuperRegIdxSeqs + 1,	----
4864	LaneBitmask(0x0000000000000001),	----
4865	0,	----
4866	false,	----
4867	0x00, /* TSFlags */	----
4868	false, /* HasDisjunctSubRegs */	----
4869	false, /* CoveredBySubRegs */	----
4870	NullRegClasses,	----
4871	nullptr	----
4872	};	----
4873		----
4874	extern const TargetRegisterClass COP3RegClass = {	----
4875	&MipsMCRegisterClasses[COP3RegClassID],	----
4876	COP3SubClassMask,	----
4877	SuperRegIdxSeqs + 1,	----
4878	LaneBitmask(0x0000000000000001),	----
4879	0,	----
4880	false,	----
4881	0x00, /* TSFlags */	----
4882	false, /* HasDisjunctSubRegs */	----
4883	false, /* CoveredBySubRegs */	----
4884	NullRegClasses,	----
4885	nullptr	----
4886	};	----
4887		----
4888	extern const TargetRegisterClass DSPRRegClass = {	----
4889	&MipsMCRegisterClasses[DSPRRegClassID],	----
4890	DSPRSubClassMask,	----
4891	SuperRegIdxSeqs + 0,	----
4892	LaneBitmask(0x0000000000000001),	----
4893	0,	----
4894	false,	----
4895	0x00, /* TSFlags */	----
4896	false, /* HasDisjunctSubRegs */	----
4897	false, /* CoveredBySubRegs */	----
4898	NullRegClasses,	----
4899	nullptr	----
4900	};	----
4901		----
4902	extern const TargetRegisterClass FGR32RegClass = {	----
4903	&MipsMCRegisterClasses[FGR32RegClassID],	----
4904	FGR32SubClassMask,	----
4905	SuperRegIdxSeqs + 9,	----
4906	LaneBitmask(0x0000000000000001),	----
4907	0,	----
4908	false,	----
4909	0x00, /* TSFlags */	----
4910	false, /* HasDisjunctSubRegs */	----
4911	false, /* CoveredBySubRegs */	----
4912	FGR32Superclasses,	----
4913	FGR32GetRawAllocationOrder	----
4914	};	----
4915		----
4916	extern const TargetRegisterClass FGRCCRegClass = {	----
4917	&MipsMCRegisterClasses[FGRCCRegClassID],	----
4918	FGRCCSubClassMask,	----
4919	SuperRegIdxSeqs + 9,	----
4920	LaneBitmask(0x0000000000000001),	----
4921	0,	----
4922	false,	----
4923	0x00, /* TSFlags */	----
4924	false, /* HasDisjunctSubRegs */	----
4925	false, /* CoveredBySubRegs */	----
4926	FGRCCSuperclasses,	----
4927	nullptr	----
4928	};	----
4929		----
4930	extern const TargetRegisterClass GPR32RegClass = {	----
4931	&MipsMCRegisterClasses[GPR32RegClassID],	----
4932	GPR32SubClassMask,	----
4933	SuperRegIdxSeqs + 0,	----
4934	LaneBitmask(0x0000000000000001),	----
4935	0,	----
4936	false,	----
4937	0x00, /* TSFlags */	----
4938	false, /* HasDisjunctSubRegs */	----
4939	false, /* CoveredBySubRegs */	----
4940	GPR32Superclasses,	----
4941	nullptr	----
4942	};	----
4943		----
4944	extern const TargetRegisterClass HWRegsRegClass = {	----
4945	&MipsMCRegisterClasses[HWRegsRegClassID],	----
4946	HWRegsSubClassMask,	----
4947	SuperRegIdxSeqs + 1,	----
4948	LaneBitmask(0x0000000000000001),	----
4949	0,	----
4950	false,	----
4951	0x00, /* TSFlags */	----
4952	false, /* HasDisjunctSubRegs */	----
4953	false, /* CoveredBySubRegs */	----
4954	NullRegClasses,	----
4955	nullptr	----
4956	};	----
4957		----
4958	extern const TargetRegisterClass MSACtrlRegClass = {	----
4959	&MipsMCRegisterClasses[MSACtrlRegClassID],	----
4960	MSACtrlSubClassMask,	----
4961	SuperRegIdxSeqs + 1,	----
4962	LaneBitmask(0x0000000000000001),	----
4963	0,	----
4964	false,	----
4965	0x00, /* TSFlags */	----
4966	false, /* HasDisjunctSubRegs */	----
4967	false, /* CoveredBySubRegs */	----
4968	NullRegClasses,	----
4969	nullptr	----
4970	};	----
4971		----
4972	extern const TargetRegisterClass GPR32NONZERORegClass = {	----
4973	&MipsMCRegisterClasses[GPR32NONZERORegClassID],	----
4974	GPR32NONZEROSubClassMask,	----
4975	SuperRegIdxSeqs + 0,	----
4976	LaneBitmask(0x0000000000000001),	----
4977	0,	----
4978	false,	----
4979	0x00, /* TSFlags */	----
4980	false, /* HasDisjunctSubRegs */	----
4981	false, /* CoveredBySubRegs */	----
4982	GPR32NONZEROSuperclasses,	----
4983	nullptr	----
4984	};	----
4985		----
4986	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {	----
4987	&MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],	----
4988	CPU16RegsPlusSPSubClassMask,	----
4989	SuperRegIdxSeqs + 0,	----
4990	LaneBitmask(0x0000000000000001),	----
4991	0,	----
4992	false,	----
4993	0x00, /* TSFlags */	----
4994	false, /* HasDisjunctSubRegs */	----
4995	false, /* CoveredBySubRegs */	----
4996	CPU16RegsPlusSPSuperclasses,	----
4997	nullptr	----
4998	};	----
4999		----
5000	extern const TargetRegisterClass CPU16RegsRegClass = {	----
5001	&MipsMCRegisterClasses[CPU16RegsRegClassID],	----
5002	CPU16RegsSubClassMask,	----
5003	SuperRegIdxSeqs + 0,	----
5004	LaneBitmask(0x0000000000000001),	----
5005	0,	----
5006	false,	----
5007	0x00, /* TSFlags */	----
5008	false, /* HasDisjunctSubRegs */	----
5009	false, /* CoveredBySubRegs */	----
5010	CPU16RegsSuperclasses,	----
5011	nullptr	----
5012	};	----
5013		----
5014	extern const TargetRegisterClass FCCRegClass = {	----
5015	&MipsMCRegisterClasses[FCCRegClassID],	----
5016	FCCSubClassMask,	----
5017	SuperRegIdxSeqs + 1,	----
5018	LaneBitmask(0x0000000000000001),	----
5019	0,	----
5020	false,	----
5021	0x00, /* TSFlags */	----
5022	false, /* HasDisjunctSubRegs */	----
5023	false, /* CoveredBySubRegs */	----
5024	NullRegClasses,	----
5025	nullptr	----
5026	};	----
5027		----
5028	extern const TargetRegisterClass GPRMM16RegClass = {	----
5029	&MipsMCRegisterClasses[GPRMM16RegClassID],	----
5030	GPRMM16SubClassMask,	----
5031	SuperRegIdxSeqs + 0,	----
5032	LaneBitmask(0x0000000000000001),	----
5033	0,	----
5034	false,	----
5035	0x00, /* TSFlags */	----
5036	false, /* HasDisjunctSubRegs */	----
5037	false, /* CoveredBySubRegs */	----
5038	GPRMM16Superclasses,	----
5039	nullptr	----
5040	};	----
5041		----
5042	extern const TargetRegisterClass GPRMM16MovePRegClass = {	----
5043	&MipsMCRegisterClasses[GPRMM16MovePRegClassID],	----
5044	GPRMM16MovePSubClassMask,	----
5045	SuperRegIdxSeqs + 0,	----
5046	LaneBitmask(0x0000000000000001),	----
5047	0,	----
5048	false,	----
5049	0x00, /* TSFlags */	----
5050	false, /* HasDisjunctSubRegs */	----
5051	false, /* CoveredBySubRegs */	----
5052	GPRMM16MovePSuperclasses,	----
5053	nullptr	----
5054	};	----
5055		----
5056	extern const TargetRegisterClass GPRMM16ZeroRegClass = {	----
5057	&MipsMCRegisterClasses[GPRMM16ZeroRegClassID],	----
5058	GPRMM16ZeroSubClassMask,	----
5059	SuperRegIdxSeqs + 0,	----
5060	LaneBitmask(0x0000000000000001),	----
5061	0,	----
5062	false,	----
5063	0x00, /* TSFlags */	----
5064	false, /* HasDisjunctSubRegs */	----
5065	false, /* CoveredBySubRegs */	----
5066	GPRMM16ZeroSuperclasses,	----
5067	nullptr	----
5068	};	----
5069		----
5070	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {	----
5071	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],	----
5072	CPU16Regs_and_GPRMM16ZeroSubClassMask,	----
5073	SuperRegIdxSeqs + 0,	----
5074	LaneBitmask(0x0000000000000001),	----
5075	0,	----
5076	false,	----
5077	0x00, /* TSFlags */	----
5078	false, /* HasDisjunctSubRegs */	----
5079	false, /* CoveredBySubRegs */	----
5080	CPU16Regs_and_GPRMM16ZeroSuperclasses,	----
5081	nullptr	----
5082	};	----
5083		----
5084	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {	----
5085	&MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],	----
5086	GPR32NONZERO_and_GPRMM16MovePSubClassMask,	----
5087	SuperRegIdxSeqs + 0,	----
5088	LaneBitmask(0x0000000000000001),	----
5089	0,	----
5090	false,	----
5091	0x00, /* TSFlags */	----
5092	false, /* HasDisjunctSubRegs */	----
5093	false, /* CoveredBySubRegs */	----
5094	GPR32NONZERO_and_GPRMM16MovePSuperclasses,	----
5095	nullptr	----
5096	};	----
5097		----
5098	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {	----
5099	&MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],	----
5100	GPRMM16MovePPairSecondSubClassMask,	----
5101	SuperRegIdxSeqs + 0,	----
5102	LaneBitmask(0x0000000000000001),	----
5103	0,	----
5104	false,	----
5105	0x00, /* TSFlags */	----
5106	false, /* HasDisjunctSubRegs */	----
5107	false, /* CoveredBySubRegs */	----
5108	GPRMM16MovePPairSecondSuperclasses,	----
5109	nullptr	----
5110	};	----
5111		----
5112	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {	----
5113	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],	----
5114	CPU16Regs_and_GPRMM16MovePSubClassMask,	----
5115	SuperRegIdxSeqs + 0,	----
5116	LaneBitmask(0x0000000000000001),	----
5117	0,	----
5118	false,	----
5119	0x00, /* TSFlags */	----
5120	false, /* HasDisjunctSubRegs */	----
5121	false, /* CoveredBySubRegs */	----
5122	CPU16Regs_and_GPRMM16MovePSuperclasses,	----
5123	nullptr	----
5124	};	----
5125		----
5126	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	----
5127	&MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	----
5128	GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	----
5129	SuperRegIdxSeqs + 0,	----
5130	LaneBitmask(0x0000000000000001),	----
5131	0,	----
5132	false,	----
5133	0x00, /* TSFlags */	----
5134	false, /* HasDisjunctSubRegs */	----
5135	false, /* CoveredBySubRegs */	----
5136	GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	----
5137	nullptr	----
5138	};	----
5139		----
5140	extern const TargetRegisterClass HI32DSPRegClass = {	----
5141	&MipsMCRegisterClasses[HI32DSPRegClassID],	----
5142	HI32DSPSubClassMask,	----
5143	SuperRegIdxSeqs + 12,	----
5144	LaneBitmask(0x0000000000000001),	----
5145	0,	----
5146	false,	----
5147	0x00, /* TSFlags */	----
5148	false, /* HasDisjunctSubRegs */	----
5149	false, /* CoveredBySubRegs */	----
5150	NullRegClasses,	----
5151	nullptr	----
5152	};	----
5153		----
5154	extern const TargetRegisterClass LO32DSPRegClass = {	----
5155	&MipsMCRegisterClasses[LO32DSPRegClassID],	----
5156	LO32DSPSubClassMask,	----
5157	SuperRegIdxSeqs + 6,	----
5158	LaneBitmask(0x0000000000000001),	----
5159	0,	----
5160	false,	----
5161	0x00, /* TSFlags */	----
5162	false, /* HasDisjunctSubRegs */	----
5163	false, /* CoveredBySubRegs */	----
5164	NullRegClasses,	----
5165	nullptr	----
5166	};	----
5167		----
5168	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	----
5169	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	----
5170	CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	----
5171	SuperRegIdxSeqs + 0,	----
5172	LaneBitmask(0x0000000000000001),	----
5173	0,	----
5174	false,	----
5175	0x00, /* TSFlags */	----
5176	false, /* HasDisjunctSubRegs */	----
5177	false, /* CoveredBySubRegs */	----
5178	CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	----
5179	nullptr	----
5180	};	----
5181		----
5182	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {	----
5183	&MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],	----
5184	GPRMM16MovePPairFirstSubClassMask,	----
5185	SuperRegIdxSeqs + 0,	----
5186	LaneBitmask(0x0000000000000001),	----
5187	0,	----
5188	false,	----
5189	0x00, /* TSFlags */	----
5190	false, /* HasDisjunctSubRegs */	----
5191	false, /* CoveredBySubRegs */	----
5192	GPRMM16MovePPairFirstSuperclasses,	----
5193	nullptr	----
5194	};	----
5195		----
5196	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	----
5197	&MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	----
5198	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	----
5199	SuperRegIdxSeqs + 0,	----
5200	LaneBitmask(0x0000000000000001),	----
5201	0,	----
5202	false,	----
5203	0x00, /* TSFlags */	----
5204	false, /* HasDisjunctSubRegs */	----
5205	false, /* CoveredBySubRegs */	----
5206	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	----
5207	nullptr	----
5208	};	----
5209		----
5210	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	----
5211	&MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	----
5212	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	----
5213	SuperRegIdxSeqs + 0,	----
5214	LaneBitmask(0x0000000000000001),	----
5215	0,	----
5216	false,	----
5217	0x00, /* TSFlags */	----
5218	false, /* HasDisjunctSubRegs */	----
5219	false, /* CoveredBySubRegs */	----
5220	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	----
5221	nullptr	----
5222	};	----
5223		----
5224	extern const TargetRegisterClass CPURARegRegClass = {	----
5225	&MipsMCRegisterClasses[CPURARegRegClassID],	----
5226	CPURARegSubClassMask,	----
5227	SuperRegIdxSeqs + 0,	----
5228	LaneBitmask(0x0000000000000001),	----
5229	0,	----
5230	false,	----
5231	0x00, /* TSFlags */	----
5232	false, /* HasDisjunctSubRegs */	----
5233	false, /* CoveredBySubRegs */	----
5234	CPURARegSuperclasses,	----
5235	nullptr	----
5236	};	----
5237		----
5238	extern const TargetRegisterClass CPUSPRegRegClass = {	----
5239	&MipsMCRegisterClasses[CPUSPRegRegClassID],	----
5240	CPUSPRegSubClassMask,	----
5241	SuperRegIdxSeqs + 0,	----
5242	LaneBitmask(0x0000000000000001),	----
5243	0,	----
5244	false,	----
5245	0x00, /* TSFlags */	----
5246	false, /* HasDisjunctSubRegs */	----
5247	false, /* CoveredBySubRegs */	----
5248	CPUSPRegSuperclasses,	----
5249	nullptr	----
5250	};	----
5251		----
5252	extern const TargetRegisterClass DSPCCRegClass = {	----
5253	&MipsMCRegisterClasses[DSPCCRegClassID],	----
5254	DSPCCSubClassMask,	----
5255	SuperRegIdxSeqs + 1,	----
5256	LaneBitmask(0x0000000000000001),	----
5257	0,	----
5258	false,	----
5259	0x00, /* TSFlags */	----
5260	false, /* HasDisjunctSubRegs */	----
5261	false, /* CoveredBySubRegs */	----
5262	NullRegClasses,	----
5263	nullptr	----
5264	};	----
5265		----
5266	extern const TargetRegisterClass GP32RegClass = {	----
5267	&MipsMCRegisterClasses[GP32RegClassID],	----
5268	GP32SubClassMask,	----
5269	SuperRegIdxSeqs + 0,	----
5270	LaneBitmask(0x0000000000000001),	----
5271	0,	----
5272	false,	----
5273	0x00, /* TSFlags */	----
5274	false, /* HasDisjunctSubRegs */	----
5275	false, /* CoveredBySubRegs */	----
5276	GP32Superclasses,	----
5277	nullptr	----
5278	};	----
5279		----
5280	extern const TargetRegisterClass GPR32ZERORegClass = {	----
5281	&MipsMCRegisterClasses[GPR32ZERORegClassID],	----
5282	GPR32ZEROSubClassMask,	----
5283	SuperRegIdxSeqs + 0,	----
5284	LaneBitmask(0x0000000000000001),	----
5285	0,	----
5286	false,	----
5287	0x00, /* TSFlags */	----
5288	false, /* HasDisjunctSubRegs */	----
5289	false, /* CoveredBySubRegs */	----
5290	GPR32ZEROSuperclasses,	----
5291	nullptr	----
5292	};	----
5293		----
5294	extern const TargetRegisterClass HI32RegClass = {	----
5295	&MipsMCRegisterClasses[HI32RegClassID],	----
5296	HI32SubClassMask,	----
5297	SuperRegIdxSeqs + 12,	----
5298	LaneBitmask(0x0000000000000001),	----
5299	0,	----
5300	false,	----
5301	0x00, /* TSFlags */	----
5302	false, /* HasDisjunctSubRegs */	----
5303	false, /* CoveredBySubRegs */	----
5304	HI32Superclasses,	----
5305	nullptr	----
5306	};	----
5307		----
5308	extern const TargetRegisterClass LO32RegClass = {	----
5309	&MipsMCRegisterClasses[LO32RegClassID],	----
5310	LO32SubClassMask,	----
5311	SuperRegIdxSeqs + 6,	----
5312	LaneBitmask(0x0000000000000001),	----
5313	0,	----
5314	false,	----
5315	0x00, /* TSFlags */	----
5316	false, /* HasDisjunctSubRegs */	----
5317	false, /* CoveredBySubRegs */	----
5318	LO32Superclasses,	----
5319	nullptr	----
5320	};	----
5321		----
5322	extern const TargetRegisterClass SP32RegClass = {	----
5323	&MipsMCRegisterClasses[SP32RegClassID],	----
5324	SP32SubClassMask,	----
5325	SuperRegIdxSeqs + 0,	----
5326	LaneBitmask(0x0000000000000001),	----
5327	0,	----
5328	false,	----
5329	0x00, /* TSFlags */	----
5330	false, /* HasDisjunctSubRegs */	----
5331	false, /* CoveredBySubRegs */	----
5332	SP32Superclasses,	----
5333	nullptr	----
5334	};	----
5335		----
5336	extern const TargetRegisterClass FGR64RegClass = {	----
5337	&MipsMCRegisterClasses[FGR64RegClassID],	----
5338	FGR64SubClassMask,	----
5339	SuperRegIdxSeqs + 2,	----
5340	LaneBitmask(0x0000000000000041),	----
5341	0,	----
5342	false,	----
5343	0x00, /* TSFlags */	----
5344	true, /* HasDisjunctSubRegs */	----
5345	true, /* CoveredBySubRegs */	----
5346	NullRegClasses,	----
5347	FGR64GetRawAllocationOrder	----
5348	};	----
5349		----
5350	extern const TargetRegisterClass GPR64RegClass = {	----
5351	&MipsMCRegisterClasses[GPR64RegClassID],	----
5352	GPR64SubClassMask,	----
5353	SuperRegIdxSeqs + 1,	----
5354	LaneBitmask(0x0000000000000001),	----
5355	0,	----
5356	false,	----
5357	0x00, /* TSFlags */	----
5358	false, /* HasDisjunctSubRegs */	----
5359	false, /* CoveredBySubRegs */	----
5360	NullRegClasses,	----
5361	nullptr	----
5362	};	----
5363		----
5364	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {	----
5365	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],	----
5366	GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,	----
5367	SuperRegIdxSeqs + 1,	----
5368	LaneBitmask(0x0000000000000001),	----
5369	0,	----
5370	false,	----
5371	0x00, /* TSFlags */	----
5372	false, /* HasDisjunctSubRegs */	----
5373	false, /* CoveredBySubRegs */	----
5374	GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,	----
5375	nullptr	----
5376	};	----
5377		----
5378	extern const TargetRegisterClass AFGR64RegClass = {	----
5379	&MipsMCRegisterClasses[AFGR64RegClassID],	----
5380	AFGR64SubClassMask,	----
5381	SuperRegIdxSeqs + 1,	----
5382	LaneBitmask(0x0000000000000041),	----
5383	0,	----
5384	false,	----
5385	0x00, /* TSFlags */	----
5386	true, /* HasDisjunctSubRegs */	----
5387	true, /* CoveredBySubRegs */	----
5388	NullRegClasses,	----
5389	nullptr	----
5390	};	----
5391		----
5392	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {	----
5393	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],	----
5394	GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,	----
5395	SuperRegIdxSeqs + 1,	----
5396	LaneBitmask(0x0000000000000001),	----
5397	0,	----
5398	false,	----
5399	0x00, /* TSFlags */	----
5400	false, /* HasDisjunctSubRegs */	----
5401	false, /* CoveredBySubRegs */	----
5402	GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,	----
5403	nullptr	----
5404	};	----
5405		----
5406	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {	----
5407	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],	----
5408	GPR64_with_sub_32_in_CPU16RegsSubClassMask,	----
5409	SuperRegIdxSeqs + 1,	----
5410	LaneBitmask(0x0000000000000001),	----
5411	0,	----
5412	false,	----
5413	0x00, /* TSFlags */	----
5414	false, /* HasDisjunctSubRegs */	----
5415	false, /* CoveredBySubRegs */	----
5416	GPR64_with_sub_32_in_CPU16RegsSuperclasses,	----
5417	nullptr	----
5418	};	----
5419		----
5420	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {	----
5421	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],	----
5422	GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,	----
5423	SuperRegIdxSeqs + 1,	----
5424	LaneBitmask(0x0000000000000001),	----
5425	0,	----
5426	false,	----
5427	0x00, /* TSFlags */	----
5428	false, /* HasDisjunctSubRegs */	----
5429	false, /* CoveredBySubRegs */	----
5430	GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,	----
5431	nullptr	----
5432	};	----
5433		----
5434	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {	----
5435	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],	----
5436	GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,	----
5437	SuperRegIdxSeqs + 1,	----
5438	LaneBitmask(0x0000000000000001),	----
5439	0,	----
5440	false,	----
5441	0x00, /* TSFlags */	----
5442	false, /* HasDisjunctSubRegs */	----
5443	false, /* CoveredBySubRegs */	----
5444	GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,	----
5445	nullptr	----
5446	};	----
5447		----
5448	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {	----
5449	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],	----
5450	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,	----
5451	SuperRegIdxSeqs + 1,	----
5452	LaneBitmask(0x0000000000000001),	----
5453	0,	----
5454	false,	----
5455	0x00, /* TSFlags */	----
5456	false, /* HasDisjunctSubRegs */	----
5457	false, /* CoveredBySubRegs */	----
5458	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,	----
5459	nullptr	----
5460	};	----
5461		----
5462	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {	----
5463	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],	----
5464	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,	----
5465	SuperRegIdxSeqs + 1,	----
5466	LaneBitmask(0x0000000000000001),	----
5467	0,	----
5468	false,	----
5469	0x00, /* TSFlags */	----
5470	false, /* HasDisjunctSubRegs */	----
5471	false, /* CoveredBySubRegs */	----
5472	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,	----
5473	nullptr	----
5474	};	----
5475		----
5476	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {	----
5477	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],	----
5478	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,	----
5479	SuperRegIdxSeqs + 1,	----
5480	LaneBitmask(0x0000000000000001),	----
5481	0,	----
5482	false,	----
5483	0x00, /* TSFlags */	----
5484	false, /* HasDisjunctSubRegs */	----
5485	false, /* CoveredBySubRegs */	----
5486	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,	----
5487	nullptr	----
5488	};	----
5489		----
5490	extern const TargetRegisterClass ACC64DSPRegClass = {	----
5491	&MipsMCRegisterClasses[ACC64DSPRegClassID],	----
5492	ACC64DSPSubClassMask,	----
5493	SuperRegIdxSeqs + 16,	----
5494	LaneBitmask(0x0000000000000041),	----
5495	0,	----
5496	false,	----
5497	0x00, /* TSFlags */	----
5498	true, /* HasDisjunctSubRegs */	----
5499	true, /* CoveredBySubRegs */	----
5500	NullRegClasses,	----
5501	nullptr	----
5502	};	----
5503		----
5504	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {	----
5505	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],	----
5506	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,	----
5507	SuperRegIdxSeqs + 1,	----
5508	LaneBitmask(0x0000000000000001),	----
5509	0,	----
5510	false,	----
5511	0x00, /* TSFlags */	----
5512	false, /* HasDisjunctSubRegs */	----
5513	false, /* CoveredBySubRegs */	----
5514	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,	----
5515	nullptr	----
5516	};	----
5517		----
5518	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	----
5519	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	----
5520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	----
5521	SuperRegIdxSeqs + 1,	----
5522	LaneBitmask(0x0000000000000001),	----
5523	0,	----
5524	false,	----
5525	0x00, /* TSFlags */	----
5526	false, /* HasDisjunctSubRegs */	----
5527	false, /* CoveredBySubRegs */	----
5528	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	----
5529	nullptr	----
5530	};	----
5531		----
5532	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	----
5533	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	----
5534	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	----
5535	SuperRegIdxSeqs + 1,	----
5536	LaneBitmask(0x0000000000000001),	----
5537	0,	----
5538	false,	----
5539	0x00, /* TSFlags */	----
5540	false, /* HasDisjunctSubRegs */	----
5541	false, /* CoveredBySubRegs */	----
5542	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	----
5543	nullptr	----
5544	};	----
5545		----
5546	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {	----
5547	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],	----
5548	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,	----
5549	SuperRegIdxSeqs + 1,	----
5550	LaneBitmask(0x0000000000000001),	----
5551	0,	----
5552	false,	----
5553	0x00, /* TSFlags */	----
5554	false, /* HasDisjunctSubRegs */	----
5555	false, /* CoveredBySubRegs */	----
5556	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,	----
5557	nullptr	----
5558	};	----
5559		----
5560	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	----
5561	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	----
5562	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	----
5563	SuperRegIdxSeqs + 1,	----
5564	LaneBitmask(0x0000000000000001),	----
5565	0,	----
5566	false,	----
5567	0x00, /* TSFlags */	----
5568	false, /* HasDisjunctSubRegs */	----
5569	false, /* CoveredBySubRegs */	----
5570	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	----
5571	nullptr	----
5572	};	----
5573		----
5574	extern const TargetRegisterClass OCTEON_MPLRegClass = {	----
5575	&MipsMCRegisterClasses[OCTEON_MPLRegClassID],	----
5576	OCTEON_MPLSubClassMask,	----
5577	SuperRegIdxSeqs + 1,	----
5578	LaneBitmask(0x0000000000000001),	----
5579	0,	----
5580	false,	----
5581	0x00, /* TSFlags */	----
5582	false, /* HasDisjunctSubRegs */	----
5583	false, /* CoveredBySubRegs */	----
5584	NullRegClasses,	----
5585	nullptr	----
5586	};	----
5587		----
5588	extern const TargetRegisterClass OCTEON_PRegClass = {	----
5589	&MipsMCRegisterClasses[OCTEON_PRegClassID],	----
5590	OCTEON_PSubClassMask,	----
5591	SuperRegIdxSeqs + 1,	----
5592	LaneBitmask(0x0000000000000001),	----
5593	0,	----
5594	false,	----
5595	0x00, /* TSFlags */	----
5596	false, /* HasDisjunctSubRegs */	----
5597	false, /* CoveredBySubRegs */	----
5598	NullRegClasses,	----
5599	nullptr	----
5600	};	----
5601		----
5602	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	----
5603	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	----
5604	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	----
5605	SuperRegIdxSeqs + 1,	----
5606	LaneBitmask(0x0000000000000001),	----
5607	0,	----
5608	false,	----
5609	0x00, /* TSFlags */	----
5610	false, /* HasDisjunctSubRegs */	----
5611	false, /* CoveredBySubRegs */	----
5612	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	----
5613	nullptr	----
5614	};	----
5615		----
5616	extern const TargetRegisterClass ACC64RegClass = {	----
5617	&MipsMCRegisterClasses[ACC64RegClassID],	----
5618	ACC64SubClassMask,	----
5619	SuperRegIdxSeqs + 16,	----
5620	LaneBitmask(0x0000000000000041),	----
5621	0,	----
5622	false,	----
5623	0x00, /* TSFlags */	----
5624	true, /* HasDisjunctSubRegs */	----
5625	true, /* CoveredBySubRegs */	----
5626	ACC64Superclasses,	----
5627	nullptr	----
5628	};	----
5629		----
5630	extern const TargetRegisterClass GP64RegClass = {	----
5631	&MipsMCRegisterClasses[GP64RegClassID],	----
5632	GP64SubClassMask,	----
5633	SuperRegIdxSeqs + 1,	----
5634	LaneBitmask(0x0000000000000001),	----
5635	0,	----
5636	false,	----
5637	0x00, /* TSFlags */	----
5638	false, /* HasDisjunctSubRegs */	----
5639	false, /* CoveredBySubRegs */	----
5640	GP64Superclasses,	----
5641	nullptr	----
5642	};	----
5643		----
5644	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {	----
5645	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],	----
5646	GPR64_with_sub_32_in_CPURARegSubClassMask,	----
5647	SuperRegIdxSeqs + 1,	----
5648	LaneBitmask(0x0000000000000001),	----
5649	0,	----
5650	false,	----
5651	0x00, /* TSFlags */	----
5652	false, /* HasDisjunctSubRegs */	----
5653	false, /* CoveredBySubRegs */	----
5654	GPR64_with_sub_32_in_CPURARegSuperclasses,	----
5655	nullptr	----
5656	};	----
5657		----
5658	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {	----
5659	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],	----
5660	GPR64_with_sub_32_in_GPR32ZEROSubClassMask,	----
5661	SuperRegIdxSeqs + 1,	----
5662	LaneBitmask(0x0000000000000001),	----
5663	0,	----
5664	false,	----
5665	0x00, /* TSFlags */	----
5666	false, /* HasDisjunctSubRegs */	----
5667	false, /* CoveredBySubRegs */	----
5668	GPR64_with_sub_32_in_GPR32ZEROSuperclasses,	----
5669	nullptr	----
5670	};	----
5671		----
5672	extern const TargetRegisterClass HI64RegClass = {	----
5673	&MipsMCRegisterClasses[HI64RegClassID],	----
5674	HI64SubClassMask,	----
5675	SuperRegIdxSeqs + 4,	----
5676	LaneBitmask(0x0000000000000001),	----
5677	0,	----
5678	false,	----
5679	0x00, /* TSFlags */	----
5680	false, /* HasDisjunctSubRegs */	----
5681	false, /* CoveredBySubRegs */	----
5682	NullRegClasses,	----
5683	nullptr	----
5684	};	----
5685		----
5686	extern const TargetRegisterClass LO64RegClass = {	----
5687	&MipsMCRegisterClasses[LO64RegClassID],	----
5688	LO64SubClassMask,	----
5689	SuperRegIdxSeqs + 7,	----
5690	LaneBitmask(0x0000000000000001),	----
5691	0,	----
5692	false,	----
5693	0x00, /* TSFlags */	----
5694	false, /* HasDisjunctSubRegs */	----
5695	false, /* CoveredBySubRegs */	----
5696	NullRegClasses,	----
5697	nullptr	----
5698	};	----
5699		----
5700	extern const TargetRegisterClass SP64RegClass = {	----
5701	&MipsMCRegisterClasses[SP64RegClassID],	----
5702	SP64SubClassMask,	----
5703	SuperRegIdxSeqs + 1,	----
5704	LaneBitmask(0x0000000000000001),	----
5705	0,	----
5706	false,	----
5707	0x00, /* TSFlags */	----
5708	false, /* HasDisjunctSubRegs */	----
5709	false, /* CoveredBySubRegs */	----
5710	SP64Superclasses,	----
5711	nullptr	----
5712	};	----
5713		----
5714	extern const TargetRegisterClass MSA128BRegClass = {	----
5715	&MipsMCRegisterClasses[MSA128BRegClassID],	----
5716	MSA128BSubClassMask,	----
5717	SuperRegIdxSeqs + 1,	----
5718	LaneBitmask(0x0000000000000041),	----
5719	0,	----
5720	false,	----
5721	0x00, /* TSFlags */	----
5722	true, /* HasDisjunctSubRegs */	----
5723	false, /* CoveredBySubRegs */	----
5724	MSA128BSuperclasses,	----
5725	nullptr	----
5726	};	----
5727		----
5728	extern const TargetRegisterClass MSA128DRegClass = {	----
5729	&MipsMCRegisterClasses[MSA128DRegClassID],	----
5730	MSA128DSubClassMask,	----
5731	SuperRegIdxSeqs + 1,	----
5732	LaneBitmask(0x0000000000000041),	----
5733	0,	----
5734	false,	----
5735	0x00, /* TSFlags */	----
5736	true, /* HasDisjunctSubRegs */	----
5737	false, /* CoveredBySubRegs */	----
5738	MSA128DSuperclasses,	----
5739	nullptr	----
5740	};	----
5741		----
5742	extern const TargetRegisterClass MSA128HRegClass = {	----
5743	&MipsMCRegisterClasses[MSA128HRegClassID],	----
5744	MSA128HSubClassMask,	----
5745	SuperRegIdxSeqs + 1,	----
5746	LaneBitmask(0x0000000000000041),	----
5747	0,	----
5748	false,	----
5749	0x00, /* TSFlags */	----
5750	true, /* HasDisjunctSubRegs */	----
5751	false, /* CoveredBySubRegs */	----
5752	MSA128HSuperclasses,	----
5753	nullptr	----
5754	};	----
5755		----
5756	extern const TargetRegisterClass MSA128WRegClass = {	----
5757	&MipsMCRegisterClasses[MSA128WRegClassID],	----
5758	MSA128WSubClassMask,	----
5759	SuperRegIdxSeqs + 1,	----
5760	LaneBitmask(0x0000000000000041),	----
5761	0,	----
5762	false,	----
5763	0x00, /* TSFlags */	----
5764	true, /* HasDisjunctSubRegs */	----
5765	false, /* CoveredBySubRegs */	----
5766	MSA128WSuperclasses,	----
5767	nullptr	----
5768	};	----
5769		----
5770	extern const TargetRegisterClass MSA128WEvensRegClass = {	----
5771	&MipsMCRegisterClasses[MSA128WEvensRegClassID],	----
5772	MSA128WEvensSubClassMask,	----
5773	SuperRegIdxSeqs + 1,	----
5774	LaneBitmask(0x0000000000000041),	----
5775	0,	----
5776	false,	----
5777	0x00, /* TSFlags */	----
5778	true, /* HasDisjunctSubRegs */	----
5779	false, /* CoveredBySubRegs */	----
5780	MSA128WEvensSuperclasses,	----
5781	nullptr	----
5782	};	----
5783		----
5784	extern const TargetRegisterClass ACC128RegClass = {	----
5785	&MipsMCRegisterClasses[ACC128RegClassID],	----
5786	ACC128SubClassMask,	----
5787	SuperRegIdxSeqs + 1,	----
5788	LaneBitmask(0x0000000000000041),	----
5789	0,	----
5790	false,	----
5791	0x00, /* TSFlags */	----
5792	true, /* HasDisjunctSubRegs */	----
5793	true, /* CoveredBySubRegs */	----
5794	NullRegClasses,	----
5795	nullptr	----
5796	};	----
5797		----
5798	} // end namespace Mips	----
5799		----
5800	namespace {	----
5801	const TargetRegisterClass *const RegisterClasses[] = {	----
5802	&Mips::MSA128F16RegClass,	----
5803	&Mips::CCRRegClass,	----
5804	&Mips::COP0RegClass,	----
5805	&Mips::COP2RegClass,	----
5806	&Mips::COP3RegClass,	----
5807	&Mips::DSPRRegClass,	----
5808	&Mips::FGR32RegClass,	----
5809	&Mips::FGRCCRegClass,	----
5810	&Mips::GPR32RegClass,	----
5811	&Mips::HWRegsRegClass,	----
5812	&Mips::MSACtrlRegClass,	----
5813	&Mips::GPR32NONZERORegClass,	----
5814	&Mips::CPU16RegsPlusSPRegClass,	----
5815	&Mips::CPU16RegsRegClass,	----
5816	&Mips::FCCRegClass,	----
5817	&Mips::GPRMM16RegClass,	----
5818	&Mips::GPRMM16MovePRegClass,	----
5819	&Mips::GPRMM16ZeroRegClass,	----
5820	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	----
5821	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	----
5822	&Mips::GPRMM16MovePPairSecondRegClass,	----
5823	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	----
5824	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
5825	&Mips::HI32DSPRegClass,	----
5826	&Mips::LO32DSPRegClass,	----
5827	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	----
5828	&Mips::GPRMM16MovePPairFirstRegClass,	----
5829	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	----
5830	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	----
5831	&Mips::CPURARegRegClass,	----
5832	&Mips::CPUSPRegRegClass,	----
5833	&Mips::DSPCCRegClass,	----
5834	&Mips::GP32RegClass,	----
5835	&Mips::GPR32ZERORegClass,	----
5836	&Mips::HI32RegClass,	----
5837	&Mips::LO32RegClass,	----
5838	&Mips::SP32RegClass,	----
5839	&Mips::FGR64RegClass,	----
5840	&Mips::GPR64RegClass,	----
5841	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	----
5842	&Mips::AFGR64RegClass,	----
5843	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	----
5844	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	----
5845	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	----
5846	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	----
5847	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	----
5848	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	----
5849	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	----
5850	&Mips::ACC64DSPRegClass,	----
5851	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	----
5852	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	----
5853	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	----
5854	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	----
5855	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	----
5856	&Mips::OCTEON_MPLRegClass,	----
5857	&Mips::OCTEON_PRegClass,	----
5858	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	----
5859	&Mips::ACC64RegClass,	----
5860	&Mips::GP64RegClass,	----
5861	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,	----
5862	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,	----
5863	&Mips::HI64RegClass,	----
5864	&Mips::LO64RegClass,	----
5865	&Mips::SP64RegClass,	----
5866	&Mips::MSA128BRegClass,	----
5867	&Mips::MSA128DRegClass,	----
5868	&Mips::MSA128HRegClass,	----
5869	&Mips::MSA128WRegClass,	----
5870	&Mips::MSA128WEvensRegClass,	----
5871	&Mips::ACC128RegClass,	----
5872	};	----
5873	} // end anonymous namespace	----
5874		----
5875	static const uint8_t CostPerUseTable[] = {	----
5876	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };	----
5877		----
5878		----
5879	static const bool InAllocatableClassTable[] = {	----
5880	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };	----
5881		----
5882		----
5883	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors	----
5884	CostPerUseTable, 1, InAllocatableClassTable};	----
5885		----
5886	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {	0
5887	static const uint8_t RowMap[11] = {	----
5888	0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,	----
5889	};	----
5890	static const uint8_t Rows[2][11] = {	----
5891	{ Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },	----
5892	{ Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },	----
5893	};	----
5894		----
5895	--IdxA; assert(IdxA < 11); (void) IdxA;	0
5896	--IdxB; assert(IdxB < 11);	0
5897	return Rows[RowMap[IdxA]][IdxB];	0
5898	}	----
5899		----
5900	struct MaskRolOp {	----
5901	LaneBitmask Mask;	----
5902	uint8_t RotateLeft;	----
5903	};	----
5904	static const MaskRolOp LaneMaskComposeSequences[] = {	----
5905	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0	----
5906	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2	----
5907	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4	----
5908	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6	----
5909	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8	----
5910	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10	----
5911	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12	----
5912	};	----
5913	static const uint8_t CompositeSequences[] = {	----
5914	0, // to sub_32	----
5915	0, // to sub_64	----
5916	2, // to sub_dsp16_19	----
5917	4, // to sub_dsp20	----
5918	6, // to sub_dsp21	----
5919	8, // to sub_dsp22	----
5920	10, // to sub_dsp23	----
5921	12, // to sub_hi	----
5922	0, // to sub_lo	----
5923	12, // to sub_hi_then_sub_32	----
5924	0 // to sub_32_sub_hi_then_sub_32	----
5925	};	----
5926		----
5927	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0
5928	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0
5929	LaneBitmask Result;	0
5930	for (const MaskRolOp *Ops =	0
5931	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0
5932	Ops->Mask.any(); ++Ops) {	0
5933	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();	0
5934	if (unsigned S = Ops->RotateLeft)	0
5935	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));	0
5936	else	----
5937	Result \|= LaneBitmask(M);	0
5938	}	----
5939	return Result;	0
5940	}	----
5941		----
5942	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0
5943	LaneMask &= getSubRegIndexLaneMask(IdxA);	0
5944	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0
5945	LaneBitmask Result;	0
5946	for (const MaskRolOp *Ops =	0
5947	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0
5948	Ops->Mask.any(); ++Ops) {	0
5949	LaneBitmask::Type M = LaneMask.getAsInteger();	0
5950	if (unsigned S = Ops->RotateLeft)	0
5951	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));	0
5952	else	----
5953	Result \|= LaneBitmask(M);	0
5954	}	----
5955	return Result;	0
5956	}	----
5957		----
5958	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {	0
5959	static const uint8_t Table[70][11] = {	----
5960	{ // MSA128F16	----
5961	0, // sub_32	----
5962	1, // sub_64 -> MSA128F16	----
5963	0, // sub_dsp16_19	----
5964	0, // sub_dsp20	----
5965	0, // sub_dsp21	----
5966	0, // sub_dsp22	----
5967	0, // sub_dsp23	----
5968	1, // sub_hi -> MSA128F16	----
5969	1, // sub_lo -> MSA128F16	----
5970	0, // sub_hi_then_sub_32	----
5971	0, // sub_32_sub_hi_then_sub_32	----
5972	},	----
5973	{ // CCR	----
5974	0, // sub_32	----
5975	0, // sub_64	----
5976	0, // sub_dsp16_19	----
5977	0, // sub_dsp20	----
5978	0, // sub_dsp21	----
5979	0, // sub_dsp22	----
5980	0, // sub_dsp23	----
5981	0, // sub_hi	----
5982	0, // sub_lo	----
5983	0, // sub_hi_then_sub_32	----
5984	0, // sub_32_sub_hi_then_sub_32	----
5985	},	----
5986	{ // COP0	----
5987	0, // sub_32	----
5988	0, // sub_64	----
5989	0, // sub_dsp16_19	----
5990	0, // sub_dsp20	----
5991	0, // sub_dsp21	----
5992	0, // sub_dsp22	----
5993	0, // sub_dsp23	----
5994	0, // sub_hi	----
5995	0, // sub_lo	----
5996	0, // sub_hi_then_sub_32	----
5997	0, // sub_32_sub_hi_then_sub_32	----
5998	},	----
5999	{ // COP2	----
6000	0, // sub_32	----
6001	0, // sub_64	----
6002	0, // sub_dsp16_19	----
6003	0, // sub_dsp20	----
6004	0, // sub_dsp21	----
6005	0, // sub_dsp22	----
6006	0, // sub_dsp23	----
6007	0, // sub_hi	----
6008	0, // sub_lo	----
6009	0, // sub_hi_then_sub_32	----
6010	0, // sub_32_sub_hi_then_sub_32	----
6011	},	----
6012	{ // COP3	----
6013	0, // sub_32	----
6014	0, // sub_64	----
6015	0, // sub_dsp16_19	----
6016	0, // sub_dsp20	----
6017	0, // sub_dsp21	----
6018	0, // sub_dsp22	----
6019	0, // sub_dsp23	----
6020	0, // sub_hi	----
6021	0, // sub_lo	----
6022	0, // sub_hi_then_sub_32	----
6023	0, // sub_32_sub_hi_then_sub_32	----
6024	},	----
6025	{ // DSPR	----
6026	0, // sub_32	----
6027	0, // sub_64	----
6028	0, // sub_dsp16_19	----
6029	0, // sub_dsp20	----
6030	0, // sub_dsp21	----
6031	0, // sub_dsp22	----
6032	0, // sub_dsp23	----
6033	0, // sub_hi	----
6034	0, // sub_lo	----
6035	0, // sub_hi_then_sub_32	----
6036	0, // sub_32_sub_hi_then_sub_32	----
6037	},	----
6038	{ // FGR32	----
6039	0, // sub_32	----
6040	0, // sub_64	----
6041	0, // sub_dsp16_19	----
6042	0, // sub_dsp20	----
6043	0, // sub_dsp21	----
6044	0, // sub_dsp22	----
6045	0, // sub_dsp23	----
6046	0, // sub_hi	----
6047	0, // sub_lo	----
6048	0, // sub_hi_then_sub_32	----
6049	0, // sub_32_sub_hi_then_sub_32	----
6050	},	----
6051	{ // FGRCC	----
6052	0, // sub_32	----
6053	0, // sub_64	----
6054	0, // sub_dsp16_19	----
6055	0, // sub_dsp20	----
6056	0, // sub_dsp21	----
6057	0, // sub_dsp22	----
6058	0, // sub_dsp23	----
6059	0, // sub_hi	----
6060	0, // sub_lo	----
6061	0, // sub_hi_then_sub_32	----
6062	0, // sub_32_sub_hi_then_sub_32	----
6063	},	----
6064	{ // GPR32	----
6065	0, // sub_32	----
6066	0, // sub_64	----
6067	0, // sub_dsp16_19	----
6068	0, // sub_dsp20	----
6069	0, // sub_dsp21	----
6070	0, // sub_dsp22	----
6071	0, // sub_dsp23	----
6072	0, // sub_hi	----
6073	0, // sub_lo	----
6074	0, // sub_hi_then_sub_32	----
6075	0, // sub_32_sub_hi_then_sub_32	----
6076	},	----
6077	{ // HWRegs	----
6078	0, // sub_32	----
6079	0, // sub_64	----
6080	0, // sub_dsp16_19	----
6081	0, // sub_dsp20	----
6082	0, // sub_dsp21	----
6083	0, // sub_dsp22	----
6084	0, // sub_dsp23	----
6085	0, // sub_hi	----
6086	0, // sub_lo	----
6087	0, // sub_hi_then_sub_32	----
6088	0, // sub_32_sub_hi_then_sub_32	----
6089	},	----
6090	{ // MSACtrl	----
6091	0, // sub_32	----
6092	0, // sub_64	----
6093	0, // sub_dsp16_19	----
6094	0, // sub_dsp20	----
6095	0, // sub_dsp21	----
6096	0, // sub_dsp22	----
6097	0, // sub_dsp23	----
6098	0, // sub_hi	----
6099	0, // sub_lo	----
6100	0, // sub_hi_then_sub_32	----
6101	0, // sub_32_sub_hi_then_sub_32	----
6102	},	----
6103	{ // GPR32NONZERO	----
6104	0, // sub_32	----
6105	0, // sub_64	----
6106	0, // sub_dsp16_19	----
6107	0, // sub_dsp20	----
6108	0, // sub_dsp21	----
6109	0, // sub_dsp22	----
6110	0, // sub_dsp23	----
6111	0, // sub_hi	----
6112	0, // sub_lo	----
6113	0, // sub_hi_then_sub_32	----
6114	0, // sub_32_sub_hi_then_sub_32	----
6115	},	----
6116	{ // CPU16RegsPlusSP	----
6117	0, // sub_32	----
6118	0, // sub_64	----
6119	0, // sub_dsp16_19	----
6120	0, // sub_dsp20	----
6121	0, // sub_dsp21	----
6122	0, // sub_dsp22	----
6123	0, // sub_dsp23	----
6124	0, // sub_hi	----
6125	0, // sub_lo	----
6126	0, // sub_hi_then_sub_32	----
6127	0, // sub_32_sub_hi_then_sub_32	----
6128	},	----
6129	{ // CPU16Regs	----
6130	0, // sub_32	----
6131	0, // sub_64	----
6132	0, // sub_dsp16_19	----
6133	0, // sub_dsp20	----
6134	0, // sub_dsp21	----
6135	0, // sub_dsp22	----
6136	0, // sub_dsp23	----
6137	0, // sub_hi	----
6138	0, // sub_lo	----
6139	0, // sub_hi_then_sub_32	----
6140	0, // sub_32_sub_hi_then_sub_32	----
6141	},	----
6142	{ // FCC	----
6143	0, // sub_32	----
6144	0, // sub_64	----
6145	0, // sub_dsp16_19	----
6146	0, // sub_dsp20	----
6147	0, // sub_dsp21	----
6148	0, // sub_dsp22	----
6149	0, // sub_dsp23	----
6150	0, // sub_hi	----
6151	0, // sub_lo	----
6152	0, // sub_hi_then_sub_32	----
6153	0, // sub_32_sub_hi_then_sub_32	----
6154	},	----
6155	{ // GPRMM16	----
6156	0, // sub_32	----
6157	0, // sub_64	----
6158	0, // sub_dsp16_19	----
6159	0, // sub_dsp20	----
6160	0, // sub_dsp21	----
6161	0, // sub_dsp22	----
6162	0, // sub_dsp23	----
6163	0, // sub_hi	----
6164	0, // sub_lo	----
6165	0, // sub_hi_then_sub_32	----
6166	0, // sub_32_sub_hi_then_sub_32	----
6167	},	----
6168	{ // GPRMM16MoveP	----
6169	0, // sub_32	----
6170	0, // sub_64	----
6171	0, // sub_dsp16_19	----
6172	0, // sub_dsp20	----
6173	0, // sub_dsp21	----
6174	0, // sub_dsp22	----
6175	0, // sub_dsp23	----
6176	0, // sub_hi	----
6177	0, // sub_lo	----
6178	0, // sub_hi_then_sub_32	----
6179	0, // sub_32_sub_hi_then_sub_32	----
6180	},	----
6181	{ // GPRMM16Zero	----
6182	0, // sub_32	----
6183	0, // sub_64	----
6184	0, // sub_dsp16_19	----
6185	0, // sub_dsp20	----
6186	0, // sub_dsp21	----
6187	0, // sub_dsp22	----
6188	0, // sub_dsp23	----
6189	0, // sub_hi	----
6190	0, // sub_lo	----
6191	0, // sub_hi_then_sub_32	----
6192	0, // sub_32_sub_hi_then_sub_32	----
6193	},	----
6194	{ // CPU16Regs_and_GPRMM16Zero	----
6195	0, // sub_32	----
6196	0, // sub_64	----
6197	0, // sub_dsp16_19	----
6198	0, // sub_dsp20	----
6199	0, // sub_dsp21	----
6200	0, // sub_dsp22	----
6201	0, // sub_dsp23	----
6202	0, // sub_hi	----
6203	0, // sub_lo	----
6204	0, // sub_hi_then_sub_32	----
6205	0, // sub_32_sub_hi_then_sub_32	----
6206	},	----
6207	{ // GPR32NONZERO_and_GPRMM16MoveP	----
6208	0, // sub_32	----
6209	0, // sub_64	----
6210	0, // sub_dsp16_19	----
6211	0, // sub_dsp20	----
6212	0, // sub_dsp21	----
6213	0, // sub_dsp22	----
6214	0, // sub_dsp23	----
6215	0, // sub_hi	----
6216	0, // sub_lo	----
6217	0, // sub_hi_then_sub_32	----
6218	0, // sub_32_sub_hi_then_sub_32	----
6219	},	----
6220	{ // GPRMM16MovePPairSecond	----
6221	0, // sub_32	----
6222	0, // sub_64	----
6223	0, // sub_dsp16_19	----
6224	0, // sub_dsp20	----
6225	0, // sub_dsp21	----
6226	0, // sub_dsp22	----
6227	0, // sub_dsp23	----
6228	0, // sub_hi	----
6229	0, // sub_lo	----
6230	0, // sub_hi_then_sub_32	----
6231	0, // sub_32_sub_hi_then_sub_32	----
6232	},	----
6233	{ // CPU16Regs_and_GPRMM16MoveP	----
6234	0, // sub_32	----
6235	0, // sub_64	----
6236	0, // sub_dsp16_19	----
6237	0, // sub_dsp20	----
6238	0, // sub_dsp21	----
6239	0, // sub_dsp22	----
6240	0, // sub_dsp23	----
6241	0, // sub_hi	----
6242	0, // sub_lo	----
6243	0, // sub_hi_then_sub_32	----
6244	0, // sub_32_sub_hi_then_sub_32	----
6245	},	----
6246	{ // GPRMM16MoveP_and_GPRMM16Zero	----
6247	0, // sub_32	----
6248	0, // sub_64	----
6249	0, // sub_dsp16_19	----
6250	0, // sub_dsp20	----
6251	0, // sub_dsp21	----
6252	0, // sub_dsp22	----
6253	0, // sub_dsp23	----
6254	0, // sub_hi	----
6255	0, // sub_lo	----
6256	0, // sub_hi_then_sub_32	----
6257	0, // sub_32_sub_hi_then_sub_32	----
6258	},	----
6259	{ // HI32DSP	----
6260	0, // sub_32	----
6261	0, // sub_64	----
6262	0, // sub_dsp16_19	----
6263	0, // sub_dsp20	----
6264	0, // sub_dsp21	----
6265	0, // sub_dsp22	----
6266	0, // sub_dsp23	----
6267	0, // sub_hi	----
6268	0, // sub_lo	----
6269	0, // sub_hi_then_sub_32	----
6270	0, // sub_32_sub_hi_then_sub_32	----
6271	},	----
6272	{ // LO32DSP	----
6273	0, // sub_32	----
6274	0, // sub_64	----
6275	0, // sub_dsp16_19	----
6276	0, // sub_dsp20	----
6277	0, // sub_dsp21	----
6278	0, // sub_dsp22	----
6279	0, // sub_dsp23	----
6280	0, // sub_hi	----
6281	0, // sub_lo	----
6282	0, // sub_hi_then_sub_32	----
6283	0, // sub_32_sub_hi_then_sub_32	----
6284	},	----
6285	{ // CPU16Regs_and_GPRMM16MovePPairSecond	----
6286	0, // sub_32	----
6287	0, // sub_64	----
6288	0, // sub_dsp16_19	----
6289	0, // sub_dsp20	----
6290	0, // sub_dsp21	----
6291	0, // sub_dsp22	----
6292	0, // sub_dsp23	----
6293	0, // sub_hi	----
6294	0, // sub_lo	----
6295	0, // sub_hi_then_sub_32	----
6296	0, // sub_32_sub_hi_then_sub_32	----
6297	},	----
6298	{ // GPRMM16MovePPairFirst	----
6299	0, // sub_32	----
6300	0, // sub_64	----
6301	0, // sub_dsp16_19	----
6302	0, // sub_dsp20	----
6303	0, // sub_dsp21	----
6304	0, // sub_dsp22	----
6305	0, // sub_dsp23	----
6306	0, // sub_hi	----
6307	0, // sub_lo	----
6308	0, // sub_hi_then_sub_32	----
6309	0, // sub_32_sub_hi_then_sub_32	----
6310	},	----
6311	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
6312	0, // sub_32	----
6313	0, // sub_64	----
6314	0, // sub_dsp16_19	----
6315	0, // sub_dsp20	----
6316	0, // sub_dsp21	----
6317	0, // sub_dsp22	----
6318	0, // sub_dsp23	----
6319	0, // sub_hi	----
6320	0, // sub_lo	----
6321	0, // sub_hi_then_sub_32	----
6322	0, // sub_32_sub_hi_then_sub_32	----
6323	},	----
6324	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
6325	0, // sub_32	----
6326	0, // sub_64	----
6327	0, // sub_dsp16_19	----
6328	0, // sub_dsp20	----
6329	0, // sub_dsp21	----
6330	0, // sub_dsp22	----
6331	0, // sub_dsp23	----
6332	0, // sub_hi	----
6333	0, // sub_lo	----
6334	0, // sub_hi_then_sub_32	----
6335	0, // sub_32_sub_hi_then_sub_32	----
6336	},	----
6337	{ // CPURAReg	----
6338	0, // sub_32	----
6339	0, // sub_64	----
6340	0, // sub_dsp16_19	----
6341	0, // sub_dsp20	----
6342	0, // sub_dsp21	----
6343	0, // sub_dsp22	----
6344	0, // sub_dsp23	----
6345	0, // sub_hi	----
6346	0, // sub_lo	----
6347	0, // sub_hi_then_sub_32	----
6348	0, // sub_32_sub_hi_then_sub_32	----
6349	},	----
6350	{ // CPUSPReg	----
6351	0, // sub_32	----
6352	0, // sub_64	----
6353	0, // sub_dsp16_19	----
6354	0, // sub_dsp20	----
6355	0, // sub_dsp21	----
6356	0, // sub_dsp22	----
6357	0, // sub_dsp23	----
6358	0, // sub_hi	----
6359	0, // sub_lo	----
6360	0, // sub_hi_then_sub_32	----
6361	0, // sub_32_sub_hi_then_sub_32	----
6362	},	----
6363	{ // DSPCC	----
6364	0, // sub_32	----
6365	0, // sub_64	----
6366	0, // sub_dsp16_19	----
6367	0, // sub_dsp20	----
6368	0, // sub_dsp21	----
6369	0, // sub_dsp22	----
6370	0, // sub_dsp23	----
6371	0, // sub_hi	----
6372	0, // sub_lo	----
6373	0, // sub_hi_then_sub_32	----
6374	0, // sub_32_sub_hi_then_sub_32	----
6375	},	----
6376	{ // GP32	----
6377	0, // sub_32	----
6378	0, // sub_64	----
6379	0, // sub_dsp16_19	----
6380	0, // sub_dsp20	----
6381	0, // sub_dsp21	----
6382	0, // sub_dsp22	----
6383	0, // sub_dsp23	----
6384	0, // sub_hi	----
6385	0, // sub_lo	----
6386	0, // sub_hi_then_sub_32	----
6387	0, // sub_32_sub_hi_then_sub_32	----
6388	},	----
6389	{ // GPR32ZERO	----
6390	0, // sub_32	----
6391	0, // sub_64	----
6392	0, // sub_dsp16_19	----
6393	0, // sub_dsp20	----
6394	0, // sub_dsp21	----
6395	0, // sub_dsp22	----
6396	0, // sub_dsp23	----
6397	0, // sub_hi	----
6398	0, // sub_lo	----
6399	0, // sub_hi_then_sub_32	----
6400	0, // sub_32_sub_hi_then_sub_32	----
6401	},	----
6402	{ // HI32	----
6403	0, // sub_32	----
6404	0, // sub_64	----
6405	0, // sub_dsp16_19	----
6406	0, // sub_dsp20	----
6407	0, // sub_dsp21	----
6408	0, // sub_dsp22	----
6409	0, // sub_dsp23	----
6410	0, // sub_hi	----
6411	0, // sub_lo	----
6412	0, // sub_hi_then_sub_32	----
6413	0, // sub_32_sub_hi_then_sub_32	----
6414	},	----
6415	{ // LO32	----
6416	0, // sub_32	----
6417	0, // sub_64	----
6418	0, // sub_dsp16_19	----
6419	0, // sub_dsp20	----
6420	0, // sub_dsp21	----
6421	0, // sub_dsp22	----
6422	0, // sub_dsp23	----
6423	0, // sub_hi	----
6424	0, // sub_lo	----
6425	0, // sub_hi_then_sub_32	----
6426	0, // sub_32_sub_hi_then_sub_32	----
6427	},	----
6428	{ // SP32	----
6429	0, // sub_32	----
6430	0, // sub_64	----
6431	0, // sub_dsp16_19	----
6432	0, // sub_dsp20	----
6433	0, // sub_dsp21	----
6434	0, // sub_dsp22	----
6435	0, // sub_dsp23	----
6436	0, // sub_hi	----
6437	0, // sub_lo	----
6438	0, // sub_hi_then_sub_32	----
6439	0, // sub_32_sub_hi_then_sub_32	----
6440	},	----
6441	{ // FGR64	----
6442	0, // sub_32	----
6443	0, // sub_64	----
6444	0, // sub_dsp16_19	----
6445	0, // sub_dsp20	----
6446	0, // sub_dsp21	----
6447	0, // sub_dsp22	----
6448	0, // sub_dsp23	----
6449	38, // sub_hi -> FGR64	----
6450	38, // sub_lo -> FGR64	----
6451	0, // sub_hi_then_sub_32	----
6452	0, // sub_32_sub_hi_then_sub_32	----
6453	},	----
6454	{ // GPR64	----
6455	39, // sub_32 -> GPR64	----
6456	0, // sub_64	----
6457	0, // sub_dsp16_19	----
6458	0, // sub_dsp20	----
6459	0, // sub_dsp21	----
6460	0, // sub_dsp22	----
6461	0, // sub_dsp23	----
6462	0, // sub_hi	----
6463	0, // sub_lo	----
6464	0, // sub_hi_then_sub_32	----
6465	0, // sub_32_sub_hi_then_sub_32	----
6466	},	----
6467	{ // GPR64_with_sub_32_in_GPR32NONZERO	----
6468	40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO	----
6469	0, // sub_64	----
6470	0, // sub_dsp16_19	----
6471	0, // sub_dsp20	----
6472	0, // sub_dsp21	----
6473	0, // sub_dsp22	----
6474	0, // sub_dsp23	----
6475	0, // sub_hi	----
6476	0, // sub_lo	----
6477	0, // sub_hi_then_sub_32	----
6478	0, // sub_32_sub_hi_then_sub_32	----
6479	},	----
6480	{ // AFGR64	----
6481	0, // sub_32	----
6482	0, // sub_64	----
6483	0, // sub_dsp16_19	----
6484	0, // sub_dsp20	----
6485	0, // sub_dsp21	----
6486	0, // sub_dsp22	----
6487	0, // sub_dsp23	----
6488	41, // sub_hi -> AFGR64	----
6489	41, // sub_lo -> AFGR64	----
6490	0, // sub_hi_then_sub_32	----
6491	0, // sub_32_sub_hi_then_sub_32	----
6492	},	----
6493	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	----
6494	42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP	----
6495	0, // sub_64	----
6496	0, // sub_dsp16_19	----
6497	0, // sub_dsp20	----
6498	0, // sub_dsp21	----
6499	0, // sub_dsp22	----
6500	0, // sub_dsp23	----
6501	0, // sub_hi	----
6502	0, // sub_lo	----
6503	0, // sub_hi_then_sub_32	----
6504	0, // sub_32_sub_hi_then_sub_32	----
6505	},	----
6506	{ // GPR64_with_sub_32_in_CPU16Regs	----
6507	43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs	----
6508	0, // sub_64	----
6509	0, // sub_dsp16_19	----
6510	0, // sub_dsp20	----
6511	0, // sub_dsp21	----
6512	0, // sub_dsp22	----
6513	0, // sub_dsp23	----
6514	0, // sub_hi	----
6515	0, // sub_lo	----
6516	0, // sub_hi_then_sub_32	----
6517	0, // sub_32_sub_hi_then_sub_32	----
6518	},	----
6519	{ // GPR64_with_sub_32_in_GPRMM16MoveP	----
6520	44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP	----
6521	0, // sub_64	----
6522	0, // sub_dsp16_19	----
6523	0, // sub_dsp20	----
6524	0, // sub_dsp21	----
6525	0, // sub_dsp22	----
6526	0, // sub_dsp23	----
6527	0, // sub_hi	----
6528	0, // sub_lo	----
6529	0, // sub_hi_then_sub_32	----
6530	0, // sub_32_sub_hi_then_sub_32	----
6531	},	----
6532	{ // GPR64_with_sub_32_in_GPRMM16Zero	----
6533	45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero	----
6534	0, // sub_64	----
6535	0, // sub_dsp16_19	----
6536	0, // sub_dsp20	----
6537	0, // sub_dsp21	----
6538	0, // sub_dsp22	----
6539	0, // sub_dsp23	----
6540	0, // sub_hi	----
6541	0, // sub_lo	----
6542	0, // sub_hi_then_sub_32	----
6543	0, // sub_32_sub_hi_then_sub_32	----
6544	},	----
6545	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	----
6546	46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	----
6547	0, // sub_64	----
6548	0, // sub_dsp16_19	----
6549	0, // sub_dsp20	----
6550	0, // sub_dsp21	----
6551	0, // sub_dsp22	----
6552	0, // sub_dsp23	----
6553	0, // sub_hi	----
6554	0, // sub_lo	----
6555	0, // sub_hi_then_sub_32	----
6556	0, // sub_32_sub_hi_then_sub_32	----
6557	},	----
6558	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	----
6559	47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	----
6560	0, // sub_64	----
6561	0, // sub_dsp16_19	----
6562	0, // sub_dsp20	----
6563	0, // sub_dsp21	----
6564	0, // sub_dsp22	----
6565	0, // sub_dsp23	----
6566	0, // sub_hi	----
6567	0, // sub_lo	----
6568	0, // sub_hi_then_sub_32	----
6569	0, // sub_32_sub_hi_then_sub_32	----
6570	},	----
6571	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	----
6572	48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond	----
6573	0, // sub_64	----
6574	0, // sub_dsp16_19	----
6575	0, // sub_dsp20	----
6576	0, // sub_dsp21	----
6577	0, // sub_dsp22	----
6578	0, // sub_dsp23	----
6579	0, // sub_hi	----
6580	0, // sub_lo	----
6581	0, // sub_hi_then_sub_32	----
6582	0, // sub_32_sub_hi_then_sub_32	----
6583	},	----
6584	{ // ACC64DSP	----
6585	0, // sub_32	----
6586	0, // sub_64	----
6587	0, // sub_dsp16_19	----
6588	0, // sub_dsp20	----
6589	0, // sub_dsp21	----
6590	0, // sub_dsp22	----
6591	0, // sub_dsp23	----
6592	49, // sub_hi -> ACC64DSP	----
6593	49, // sub_lo -> ACC64DSP	----
6594	0, // sub_hi_then_sub_32	----
6595	0, // sub_32_sub_hi_then_sub_32	----
6596	},	----
6597	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	----
6598	50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	----
6599	0, // sub_64	----
6600	0, // sub_dsp16_19	----
6601	0, // sub_dsp20	----
6602	0, // sub_dsp21	----
6603	0, // sub_dsp22	----
6604	0, // sub_dsp23	----
6605	0, // sub_hi	----
6606	0, // sub_lo	----
6607	0, // sub_hi_then_sub_32	----
6608	0, // sub_32_sub_hi_then_sub_32	----
6609	},	----
6610	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	----
6611	51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	----
6612	0, // sub_64	----
6613	0, // sub_dsp16_19	----
6614	0, // sub_dsp20	----
6615	0, // sub_dsp21	----
6616	0, // sub_dsp22	----
6617	0, // sub_dsp23	----
6618	0, // sub_hi	----
6619	0, // sub_lo	----
6620	0, // sub_hi_then_sub_32	----
6621	0, // sub_32_sub_hi_then_sub_32	----
6622	},	----
6623	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	----
6624	52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	----
6625	0, // sub_64	----
6626	0, // sub_dsp16_19	----
6627	0, // sub_dsp20	----
6628	0, // sub_dsp21	----
6629	0, // sub_dsp22	----
6630	0, // sub_dsp23	----
6631	0, // sub_hi	----
6632	0, // sub_lo	----
6633	0, // sub_hi_then_sub_32	----
6634	0, // sub_32_sub_hi_then_sub_32	----
6635	},	----
6636	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	----
6637	53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst	----
6638	0, // sub_64	----
6639	0, // sub_dsp16_19	----
6640	0, // sub_dsp20	----
6641	0, // sub_dsp21	----
6642	0, // sub_dsp22	----
6643	0, // sub_dsp23	----
6644	0, // sub_hi	----
6645	0, // sub_lo	----
6646	0, // sub_hi_then_sub_32	----
6647	0, // sub_32_sub_hi_then_sub_32	----
6648	},	----
6649	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
6650	54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
6651	0, // sub_64	----
6652	0, // sub_dsp16_19	----
6653	0, // sub_dsp20	----
6654	0, // sub_dsp21	----
6655	0, // sub_dsp22	----
6656	0, // sub_dsp23	----
6657	0, // sub_hi	----
6658	0, // sub_lo	----
6659	0, // sub_hi_then_sub_32	----
6660	0, // sub_32_sub_hi_then_sub_32	----
6661	},	----
6662	{ // OCTEON_MPL	----
6663	0, // sub_32	----
6664	0, // sub_64	----
6665	0, // sub_dsp16_19	----
6666	0, // sub_dsp20	----
6667	0, // sub_dsp21	----
6668	0, // sub_dsp22	----
6669	0, // sub_dsp23	----
6670	0, // sub_hi	----
6671	0, // sub_lo	----
6672	0, // sub_hi_then_sub_32	----
6673	0, // sub_32_sub_hi_then_sub_32	----
6674	},	----
6675	{ // OCTEON_P	----
6676	0, // sub_32	----
6677	0, // sub_64	----
6678	0, // sub_dsp16_19	----
6679	0, // sub_dsp20	----
6680	0, // sub_dsp21	----
6681	0, // sub_dsp22	----
6682	0, // sub_dsp23	----
6683	0, // sub_hi	----
6684	0, // sub_lo	----
6685	0, // sub_hi_then_sub_32	----
6686	0, // sub_32_sub_hi_then_sub_32	----
6687	},	----
6688	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
6689	57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
6690	0, // sub_64	----
6691	0, // sub_dsp16_19	----
6692	0, // sub_dsp20	----
6693	0, // sub_dsp21	----
6694	0, // sub_dsp22	----
6695	0, // sub_dsp23	----
6696	0, // sub_hi	----
6697	0, // sub_lo	----
6698	0, // sub_hi_then_sub_32	----
6699	0, // sub_32_sub_hi_then_sub_32	----
6700	},	----
6701	{ // ACC64	----
6702	0, // sub_32	----
6703	0, // sub_64	----
6704	0, // sub_dsp16_19	----
6705	0, // sub_dsp20	----
6706	0, // sub_dsp21	----
6707	0, // sub_dsp22	----
6708	0, // sub_dsp23	----
6709	58, // sub_hi -> ACC64	----
6710	58, // sub_lo -> ACC64	----
6711	0, // sub_hi_then_sub_32	----
6712	0, // sub_32_sub_hi_then_sub_32	----
6713	},	----
6714	{ // GP64	----
6715	59, // sub_32 -> GP64	----
6716	0, // sub_64	----
6717	0, // sub_dsp16_19	----
6718	0, // sub_dsp20	----
6719	0, // sub_dsp21	----
6720	0, // sub_dsp22	----
6721	0, // sub_dsp23	----
6722	0, // sub_hi	----
6723	0, // sub_lo	----
6724	0, // sub_hi_then_sub_32	----
6725	0, // sub_32_sub_hi_then_sub_32	----
6726	},	----
6727	{ // GPR64_with_sub_32_in_CPURAReg	----
6728	60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg	----
6729	0, // sub_64	----
6730	0, // sub_dsp16_19	----
6731	0, // sub_dsp20	----
6732	0, // sub_dsp21	----
6733	0, // sub_dsp22	----
6734	0, // sub_dsp23	----
6735	0, // sub_hi	----
6736	0, // sub_lo	----
6737	0, // sub_hi_then_sub_32	----
6738	0, // sub_32_sub_hi_then_sub_32	----
6739	},	----
6740	{ // GPR64_with_sub_32_in_GPR32ZERO	----
6741	61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO	----
6742	0, // sub_64	----
6743	0, // sub_dsp16_19	----
6744	0, // sub_dsp20	----
6745	0, // sub_dsp21	----
6746	0, // sub_dsp22	----
6747	0, // sub_dsp23	----
6748	0, // sub_hi	----
6749	0, // sub_lo	----
6750	0, // sub_hi_then_sub_32	----
6751	0, // sub_32_sub_hi_then_sub_32	----
6752	},	----
6753	{ // HI64	----
6754	62, // sub_32 -> HI64	----
6755	0, // sub_64	----
6756	0, // sub_dsp16_19	----
6757	0, // sub_dsp20	----
6758	0, // sub_dsp21	----
6759	0, // sub_dsp22	----
6760	0, // sub_dsp23	----
6761	0, // sub_hi	----
6762	0, // sub_lo	----
6763	0, // sub_hi_then_sub_32	----
6764	0, // sub_32_sub_hi_then_sub_32	----
6765	},	----
6766	{ // LO64	----
6767	63, // sub_32 -> LO64	----
6768	0, // sub_64	----
6769	0, // sub_dsp16_19	----
6770	0, // sub_dsp20	----
6771	0, // sub_dsp21	----
6772	0, // sub_dsp22	----
6773	0, // sub_dsp23	----
6774	0, // sub_hi	----
6775	0, // sub_lo	----
6776	0, // sub_hi_then_sub_32	----
6777	0, // sub_32_sub_hi_then_sub_32	----
6778	},	----
6779	{ // SP64	----
6780	64, // sub_32 -> SP64	----
6781	0, // sub_64	----
6782	0, // sub_dsp16_19	----
6783	0, // sub_dsp20	----
6784	0, // sub_dsp21	----
6785	0, // sub_dsp22	----
6786	0, // sub_dsp23	----
6787	0, // sub_hi	----
6788	0, // sub_lo	----
6789	0, // sub_hi_then_sub_32	----
6790	0, // sub_32_sub_hi_then_sub_32	----
6791	},	----
6792	{ // MSA128B	----
6793	0, // sub_32	----
6794	65, // sub_64 -> MSA128B	----
6795	0, // sub_dsp16_19	----
6796	0, // sub_dsp20	----
6797	0, // sub_dsp21	----
6798	0, // sub_dsp22	----
6799	0, // sub_dsp23	----
6800	65, // sub_hi -> MSA128B	----
6801	65, // sub_lo -> MSA128B	----
6802	0, // sub_hi_then_sub_32	----
6803	0, // sub_32_sub_hi_then_sub_32	----
6804	},	----
6805	{ // MSA128D	----
6806	0, // sub_32	----
6807	66, // sub_64 -> MSA128D	----
6808	0, // sub_dsp16_19	----
6809	0, // sub_dsp20	----
6810	0, // sub_dsp21	----
6811	0, // sub_dsp22	----
6812	0, // sub_dsp23	----
6813	66, // sub_hi -> MSA128D	----
6814	66, // sub_lo -> MSA128D	----
6815	0, // sub_hi_then_sub_32	----
6816	0, // sub_32_sub_hi_then_sub_32	----
6817	},	----
6818	{ // MSA128H	----
6819	0, // sub_32	----
6820	67, // sub_64 -> MSA128H	----
6821	0, // sub_dsp16_19	----
6822	0, // sub_dsp20	----
6823	0, // sub_dsp21	----
6824	0, // sub_dsp22	----
6825	0, // sub_dsp23	----
6826	67, // sub_hi -> MSA128H	----
6827	67, // sub_lo -> MSA128H	----
6828	0, // sub_hi_then_sub_32	----
6829	0, // sub_32_sub_hi_then_sub_32	----
6830	},	----
6831	{ // MSA128W	----
6832	0, // sub_32	----
6833	68, // sub_64 -> MSA128W	----
6834	0, // sub_dsp16_19	----
6835	0, // sub_dsp20	----
6836	0, // sub_dsp21	----
6837	0, // sub_dsp22	----
6838	0, // sub_dsp23	----
6839	68, // sub_hi -> MSA128W	----
6840	68, // sub_lo -> MSA128W	----
6841	0, // sub_hi_then_sub_32	----
6842	0, // sub_32_sub_hi_then_sub_32	----
6843	},	----
6844	{ // MSA128WEvens	----
6845	0, // sub_32	----
6846	69, // sub_64 -> MSA128WEvens	----
6847	0, // sub_dsp16_19	----
6848	0, // sub_dsp20	----
6849	0, // sub_dsp21	----
6850	0, // sub_dsp22	----
6851	0, // sub_dsp23	----
6852	69, // sub_hi -> MSA128WEvens	----
6853	69, // sub_lo -> MSA128WEvens	----
6854	0, // sub_hi_then_sub_32	----
6855	0, // sub_32_sub_hi_then_sub_32	----
6856	},	----
6857	{ // ACC128	----
6858	70, // sub_32 -> ACC128	----
6859	0, // sub_64	----
6860	0, // sub_dsp16_19	----
6861	0, // sub_dsp20	----
6862	0, // sub_dsp21	----
6863	0, // sub_dsp22	----
6864	0, // sub_dsp23	----
6865	70, // sub_hi -> ACC128	----
6866	70, // sub_lo -> ACC128	----
6867	70, // sub_hi_then_sub_32 -> ACC128	----
6868	70, // sub_32_sub_hi_then_sub_32 -> ACC128	----
6869	},	----
6870	};	----
6871	assert(RC && "Missing regclass");	0
6872	if (!Idx) return RC;	0
6873	--Idx;	0
6874	assert(Idx < 11 && "Bad subreg");	0
6875	unsigned TV = Table[RC->getID()][Idx];	0
6876	return TV ? getRegClass(TV - 1) : nullptr;	0
6877	}	----
6878		----
6879	const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {	0
6880	static const uint8_t Table[70][11] = {	----
6881	{ // MSA128F16	----
6882	0, // MSA128F16:sub_32	----
6883	38, // MSA128F16:sub_64 -> FGR64	----
6884	0, // MSA128F16:sub_dsp16_19	----
6885	0, // MSA128F16:sub_dsp20	----
6886	0, // MSA128F16:sub_dsp21	----
6887	0, // MSA128F16:sub_dsp22	----
6888	0, // MSA128F16:sub_dsp23	----
6889	0, // MSA128F16:sub_hi	----
6890	7, // MSA128F16:sub_lo -> FGR32	----
6891	0, // MSA128F16:sub_hi_then_sub_32	----
6892	0, // MSA128F16:sub_32_sub_hi_then_sub_32	----
6893	},	----
6894	{ // CCR	----
6895	0, // CCR:sub_32	----
6896	0, // CCR:sub_64	----
6897	0, // CCR:sub_dsp16_19	----
6898	0, // CCR:sub_dsp20	----
6899	0, // CCR:sub_dsp21	----
6900	0, // CCR:sub_dsp22	----
6901	0, // CCR:sub_dsp23	----
6902	0, // CCR:sub_hi	----
6903	0, // CCR:sub_lo	----
6904	0, // CCR:sub_hi_then_sub_32	----
6905	0, // CCR:sub_32_sub_hi_then_sub_32	----
6906	},	----
6907	{ // COP0	----
6908	0, // COP0:sub_32	----
6909	0, // COP0:sub_64	----
6910	0, // COP0:sub_dsp16_19	----
6911	0, // COP0:sub_dsp20	----
6912	0, // COP0:sub_dsp21	----
6913	0, // COP0:sub_dsp22	----
6914	0, // COP0:sub_dsp23	----
6915	0, // COP0:sub_hi	----
6916	0, // COP0:sub_lo	----
6917	0, // COP0:sub_hi_then_sub_32	----
6918	0, // COP0:sub_32_sub_hi_then_sub_32	----
6919	},	----
6920	{ // COP2	----
6921	0, // COP2:sub_32	----
6922	0, // COP2:sub_64	----
6923	0, // COP2:sub_dsp16_19	----
6924	0, // COP2:sub_dsp20	----
6925	0, // COP2:sub_dsp21	----
6926	0, // COP2:sub_dsp22	----
6927	0, // COP2:sub_dsp23	----
6928	0, // COP2:sub_hi	----
6929	0, // COP2:sub_lo	----
6930	0, // COP2:sub_hi_then_sub_32	----
6931	0, // COP2:sub_32_sub_hi_then_sub_32	----
6932	},	----
6933	{ // COP3	----
6934	0, // COP3:sub_32	----
6935	0, // COP3:sub_64	----
6936	0, // COP3:sub_dsp16_19	----
6937	0, // COP3:sub_dsp20	----
6938	0, // COP3:sub_dsp21	----
6939	0, // COP3:sub_dsp22	----
6940	0, // COP3:sub_dsp23	----
6941	0, // COP3:sub_hi	----
6942	0, // COP3:sub_lo	----
6943	0, // COP3:sub_hi_then_sub_32	----
6944	0, // COP3:sub_32_sub_hi_then_sub_32	----
6945	},	----
6946	{ // DSPR	----
6947	0, // DSPR:sub_32	----
6948	0, // DSPR:sub_64	----
6949	0, // DSPR:sub_dsp16_19	----
6950	0, // DSPR:sub_dsp20	----
6951	0, // DSPR:sub_dsp21	----
6952	0, // DSPR:sub_dsp22	----
6953	0, // DSPR:sub_dsp23	----
6954	0, // DSPR:sub_hi	----
6955	0, // DSPR:sub_lo	----
6956	0, // DSPR:sub_hi_then_sub_32	----
6957	0, // DSPR:sub_32_sub_hi_then_sub_32	----
6958	},	----
6959	{ // FGR32	----
6960	0, // FGR32:sub_32	----
6961	0, // FGR32:sub_64	----
6962	0, // FGR32:sub_dsp16_19	----
6963	0, // FGR32:sub_dsp20	----
6964	0, // FGR32:sub_dsp21	----
6965	0, // FGR32:sub_dsp22	----
6966	0, // FGR32:sub_dsp23	----
6967	0, // FGR32:sub_hi	----
6968	0, // FGR32:sub_lo	----
6969	0, // FGR32:sub_hi_then_sub_32	----
6970	0, // FGR32:sub_32_sub_hi_then_sub_32	----
6971	},	----
6972	{ // FGRCC	----
6973	0, // FGRCC:sub_32	----
6974	0, // FGRCC:sub_64	----
6975	0, // FGRCC:sub_dsp16_19	----
6976	0, // FGRCC:sub_dsp20	----
6977	0, // FGRCC:sub_dsp21	----
6978	0, // FGRCC:sub_dsp22	----
6979	0, // FGRCC:sub_dsp23	----
6980	0, // FGRCC:sub_hi	----
6981	0, // FGRCC:sub_lo	----
6982	0, // FGRCC:sub_hi_then_sub_32	----
6983	0, // FGRCC:sub_32_sub_hi_then_sub_32	----
6984	},	----
6985	{ // GPR32	----
6986	0, // GPR32:sub_32	----
6987	0, // GPR32:sub_64	----
6988	0, // GPR32:sub_dsp16_19	----
6989	0, // GPR32:sub_dsp20	----
6990	0, // GPR32:sub_dsp21	----
6991	0, // GPR32:sub_dsp22	----
6992	0, // GPR32:sub_dsp23	----
6993	0, // GPR32:sub_hi	----
6994	0, // GPR32:sub_lo	----
6995	0, // GPR32:sub_hi_then_sub_32	----
6996	0, // GPR32:sub_32_sub_hi_then_sub_32	----
6997	},	----
6998	{ // HWRegs	----
6999	0, // HWRegs:sub_32	----
7000	0, // HWRegs:sub_64	----
7001	0, // HWRegs:sub_dsp16_19	----
7002	0, // HWRegs:sub_dsp20	----
7003	0, // HWRegs:sub_dsp21	----
7004	0, // HWRegs:sub_dsp22	----
7005	0, // HWRegs:sub_dsp23	----
7006	0, // HWRegs:sub_hi	----
7007	0, // HWRegs:sub_lo	----
7008	0, // HWRegs:sub_hi_then_sub_32	----
7009	0, // HWRegs:sub_32_sub_hi_then_sub_32	----
7010	},	----
7011	{ // MSACtrl	----
7012	0, // MSACtrl:sub_32	----
7013	0, // MSACtrl:sub_64	----
7014	0, // MSACtrl:sub_dsp16_19	----
7015	0, // MSACtrl:sub_dsp20	----
7016	0, // MSACtrl:sub_dsp21	----
7017	0, // MSACtrl:sub_dsp22	----
7018	0, // MSACtrl:sub_dsp23	----
7019	0, // MSACtrl:sub_hi	----
7020	0, // MSACtrl:sub_lo	----
7021	0, // MSACtrl:sub_hi_then_sub_32	----
7022	0, // MSACtrl:sub_32_sub_hi_then_sub_32	----
7023	},	----
7024	{ // GPR32NONZERO	----
7025	0, // GPR32NONZERO:sub_32	----
7026	0, // GPR32NONZERO:sub_64	----
7027	0, // GPR32NONZERO:sub_dsp16_19	----
7028	0, // GPR32NONZERO:sub_dsp20	----
7029	0, // GPR32NONZERO:sub_dsp21	----
7030	0, // GPR32NONZERO:sub_dsp22	----
7031	0, // GPR32NONZERO:sub_dsp23	----
7032	0, // GPR32NONZERO:sub_hi	----
7033	0, // GPR32NONZERO:sub_lo	----
7034	0, // GPR32NONZERO:sub_hi_then_sub_32	----
7035	0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32	----
7036	},	----
7037	{ // CPU16RegsPlusSP	----
7038	0, // CPU16RegsPlusSP:sub_32	----
7039	0, // CPU16RegsPlusSP:sub_64	----
7040	0, // CPU16RegsPlusSP:sub_dsp16_19	----
7041	0, // CPU16RegsPlusSP:sub_dsp20	----
7042	0, // CPU16RegsPlusSP:sub_dsp21	----
7043	0, // CPU16RegsPlusSP:sub_dsp22	----
7044	0, // CPU16RegsPlusSP:sub_dsp23	----
7045	0, // CPU16RegsPlusSP:sub_hi	----
7046	0, // CPU16RegsPlusSP:sub_lo	----
7047	0, // CPU16RegsPlusSP:sub_hi_then_sub_32	----
7048	0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	----
7049	},	----
7050	{ // CPU16Regs	----
7051	0, // CPU16Regs:sub_32	----
7052	0, // CPU16Regs:sub_64	----
7053	0, // CPU16Regs:sub_dsp16_19	----
7054	0, // CPU16Regs:sub_dsp20	----
7055	0, // CPU16Regs:sub_dsp21	----
7056	0, // CPU16Regs:sub_dsp22	----
7057	0, // CPU16Regs:sub_dsp23	----
7058	0, // CPU16Regs:sub_hi	----
7059	0, // CPU16Regs:sub_lo	----
7060	0, // CPU16Regs:sub_hi_then_sub_32	----
7061	0, // CPU16Regs:sub_32_sub_hi_then_sub_32	----
7062	},	----
7063	{ // FCC	----
7064	0, // FCC:sub_32	----
7065	0, // FCC:sub_64	----
7066	0, // FCC:sub_dsp16_19	----
7067	0, // FCC:sub_dsp20	----
7068	0, // FCC:sub_dsp21	----
7069	0, // FCC:sub_dsp22	----
7070	0, // FCC:sub_dsp23	----
7071	0, // FCC:sub_hi	----
7072	0, // FCC:sub_lo	----
7073	0, // FCC:sub_hi_then_sub_32	----
7074	0, // FCC:sub_32_sub_hi_then_sub_32	----
7075	},	----
7076	{ // GPRMM16	----
7077	0, // GPRMM16:sub_32	----
7078	0, // GPRMM16:sub_64	----
7079	0, // GPRMM16:sub_dsp16_19	----
7080	0, // GPRMM16:sub_dsp20	----
7081	0, // GPRMM16:sub_dsp21	----
7082	0, // GPRMM16:sub_dsp22	----
7083	0, // GPRMM16:sub_dsp23	----
7084	0, // GPRMM16:sub_hi	----
7085	0, // GPRMM16:sub_lo	----
7086	0, // GPRMM16:sub_hi_then_sub_32	----
7087	0, // GPRMM16:sub_32_sub_hi_then_sub_32	----
7088	},	----
7089	{ // GPRMM16MoveP	----
7090	0, // GPRMM16MoveP:sub_32	----
7091	0, // GPRMM16MoveP:sub_64	----
7092	0, // GPRMM16MoveP:sub_dsp16_19	----
7093	0, // GPRMM16MoveP:sub_dsp20	----
7094	0, // GPRMM16MoveP:sub_dsp21	----
7095	0, // GPRMM16MoveP:sub_dsp22	----
7096	0, // GPRMM16MoveP:sub_dsp23	----
7097	0, // GPRMM16MoveP:sub_hi	----
7098	0, // GPRMM16MoveP:sub_lo	----
7099	0, // GPRMM16MoveP:sub_hi_then_sub_32	----
7100	0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7101	},	----
7102	{ // GPRMM16Zero	----
7103	0, // GPRMM16Zero:sub_32	----
7104	0, // GPRMM16Zero:sub_64	----
7105	0, // GPRMM16Zero:sub_dsp16_19	----
7106	0, // GPRMM16Zero:sub_dsp20	----
7107	0, // GPRMM16Zero:sub_dsp21	----
7108	0, // GPRMM16Zero:sub_dsp22	----
7109	0, // GPRMM16Zero:sub_dsp23	----
7110	0, // GPRMM16Zero:sub_hi	----
7111	0, // GPRMM16Zero:sub_lo	----
7112	0, // GPRMM16Zero:sub_hi_then_sub_32	----
7113	0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7114	},	----
7115	{ // CPU16Regs_and_GPRMM16Zero	----
7116	0, // CPU16Regs_and_GPRMM16Zero:sub_32	----
7117	0, // CPU16Regs_and_GPRMM16Zero:sub_64	----
7118	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	----
7119	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20	----
7120	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21	----
7121	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22	----
7122	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23	----
7123	0, // CPU16Regs_and_GPRMM16Zero:sub_hi	----
7124	0, // CPU16Regs_and_GPRMM16Zero:sub_lo	----
7125	0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	----
7126	0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7127	},	----
7128	{ // GPR32NONZERO_and_GPRMM16MoveP	----
7129	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32	----
7130	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64	----
7131	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	----
7132	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	----
7133	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	----
7134	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	----
7135	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	----
7136	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi	----
7137	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo	----
7138	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	----
7139	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7140	},	----
7141	{ // GPRMM16MovePPairSecond	----
7142	0, // GPRMM16MovePPairSecond:sub_32	----
7143	0, // GPRMM16MovePPairSecond:sub_64	----
7144	0, // GPRMM16MovePPairSecond:sub_dsp16_19	----
7145	0, // GPRMM16MovePPairSecond:sub_dsp20	----
7146	0, // GPRMM16MovePPairSecond:sub_dsp21	----
7147	0, // GPRMM16MovePPairSecond:sub_dsp22	----
7148	0, // GPRMM16MovePPairSecond:sub_dsp23	----
7149	0, // GPRMM16MovePPairSecond:sub_hi	----
7150	0, // GPRMM16MovePPairSecond:sub_lo	----
7151	0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7152	0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7153	},	----
7154	{ // CPU16Regs_and_GPRMM16MoveP	----
7155	0, // CPU16Regs_and_GPRMM16MoveP:sub_32	----
7156	0, // CPU16Regs_and_GPRMM16MoveP:sub_64	----
7157	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	----
7158	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20	----
7159	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21	----
7160	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22	----
7161	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23	----
7162	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi	----
7163	0, // CPU16Regs_and_GPRMM16MoveP:sub_lo	----
7164	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	----
7165	0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7166	},	----
7167	{ // GPRMM16MoveP_and_GPRMM16Zero	----
7168	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32	----
7169	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64	----
7170	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	----
7171	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	----
7172	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	----
7173	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	----
7174	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	----
7175	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi	----
7176	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo	----
7177	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	----
7178	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7179	},	----
7180	{ // HI32DSP	----
7181	0, // HI32DSP:sub_32	----
7182	0, // HI32DSP:sub_64	----
7183	0, // HI32DSP:sub_dsp16_19	----
7184	0, // HI32DSP:sub_dsp20	----
7185	0, // HI32DSP:sub_dsp21	----
7186	0, // HI32DSP:sub_dsp22	----
7187	0, // HI32DSP:sub_dsp23	----
7188	0, // HI32DSP:sub_hi	----
7189	0, // HI32DSP:sub_lo	----
7190	0, // HI32DSP:sub_hi_then_sub_32	----
7191	0, // HI32DSP:sub_32_sub_hi_then_sub_32	----
7192	},	----
7193	{ // LO32DSP	----
7194	0, // LO32DSP:sub_32	----
7195	0, // LO32DSP:sub_64	----
7196	0, // LO32DSP:sub_dsp16_19	----
7197	0, // LO32DSP:sub_dsp20	----
7198	0, // LO32DSP:sub_dsp21	----
7199	0, // LO32DSP:sub_dsp22	----
7200	0, // LO32DSP:sub_dsp23	----
7201	0, // LO32DSP:sub_hi	----
7202	0, // LO32DSP:sub_lo	----
7203	0, // LO32DSP:sub_hi_then_sub_32	----
7204	0, // LO32DSP:sub_32_sub_hi_then_sub_32	----
7205	},	----
7206	{ // CPU16Regs_and_GPRMM16MovePPairSecond	----
7207	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32	----
7208	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	----
7209	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	----
7210	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	----
7211	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	----
7212	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	----
7213	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	----
7214	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	----
7215	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	----
7216	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7217	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7218	},	----
7219	{ // GPRMM16MovePPairFirst	----
7220	0, // GPRMM16MovePPairFirst:sub_32	----
7221	0, // GPRMM16MovePPairFirst:sub_64	----
7222	0, // GPRMM16MovePPairFirst:sub_dsp16_19	----
7223	0, // GPRMM16MovePPairFirst:sub_dsp20	----
7224	0, // GPRMM16MovePPairFirst:sub_dsp21	----
7225	0, // GPRMM16MovePPairFirst:sub_dsp22	----
7226	0, // GPRMM16MovePPairFirst:sub_dsp23	----
7227	0, // GPRMM16MovePPairFirst:sub_hi	----
7228	0, // GPRMM16MovePPairFirst:sub_lo	----
7229	0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32	----
7230	0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	----
7231	},	----
7232	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
7233	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32	----
7234	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	----
7235	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	----
7236	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	----
7237	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	----
7238	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	----
7239	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	----
7240	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	----
7241	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	----
7242	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	----
7243	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7244	},	----
7245	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
7246	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32	----
7247	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	----
7248	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	----
7249	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	----
7250	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	----
7251	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	----
7252	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	----
7253	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	----
7254	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	----
7255	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7256	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7257	},	----
7258	{ // CPURAReg	----
7259	0, // CPURAReg:sub_32	----
7260	0, // CPURAReg:sub_64	----
7261	0, // CPURAReg:sub_dsp16_19	----
7262	0, // CPURAReg:sub_dsp20	----
7263	0, // CPURAReg:sub_dsp21	----
7264	0, // CPURAReg:sub_dsp22	----
7265	0, // CPURAReg:sub_dsp23	----
7266	0, // CPURAReg:sub_hi	----
7267	0, // CPURAReg:sub_lo	----
7268	0, // CPURAReg:sub_hi_then_sub_32	----
7269	0, // CPURAReg:sub_32_sub_hi_then_sub_32	----
7270	},	----
7271	{ // CPUSPReg	----
7272	0, // CPUSPReg:sub_32	----
7273	0, // CPUSPReg:sub_64	----
7274	0, // CPUSPReg:sub_dsp16_19	----
7275	0, // CPUSPReg:sub_dsp20	----
7276	0, // CPUSPReg:sub_dsp21	----
7277	0, // CPUSPReg:sub_dsp22	----
7278	0, // CPUSPReg:sub_dsp23	----
7279	0, // CPUSPReg:sub_hi	----
7280	0, // CPUSPReg:sub_lo	----
7281	0, // CPUSPReg:sub_hi_then_sub_32	----
7282	0, // CPUSPReg:sub_32_sub_hi_then_sub_32	----
7283	},	----
7284	{ // DSPCC	----
7285	0, // DSPCC:sub_32	----
7286	0, // DSPCC:sub_64	----
7287	0, // DSPCC:sub_dsp16_19	----
7288	0, // DSPCC:sub_dsp20	----
7289	0, // DSPCC:sub_dsp21	----
7290	0, // DSPCC:sub_dsp22	----
7291	0, // DSPCC:sub_dsp23	----
7292	0, // DSPCC:sub_hi	----
7293	0, // DSPCC:sub_lo	----
7294	0, // DSPCC:sub_hi_then_sub_32	----
7295	0, // DSPCC:sub_32_sub_hi_then_sub_32	----
7296	},	----
7297	{ // GP32	----
7298	0, // GP32:sub_32	----
7299	0, // GP32:sub_64	----
7300	0, // GP32:sub_dsp16_19	----
7301	0, // GP32:sub_dsp20	----
7302	0, // GP32:sub_dsp21	----
7303	0, // GP32:sub_dsp22	----
7304	0, // GP32:sub_dsp23	----
7305	0, // GP32:sub_hi	----
7306	0, // GP32:sub_lo	----
7307	0, // GP32:sub_hi_then_sub_32	----
7308	0, // GP32:sub_32_sub_hi_then_sub_32	----
7309	},	----
7310	{ // GPR32ZERO	----
7311	0, // GPR32ZERO:sub_32	----
7312	0, // GPR32ZERO:sub_64	----
7313	0, // GPR32ZERO:sub_dsp16_19	----
7314	0, // GPR32ZERO:sub_dsp20	----
7315	0, // GPR32ZERO:sub_dsp21	----
7316	0, // GPR32ZERO:sub_dsp22	----
7317	0, // GPR32ZERO:sub_dsp23	----
7318	0, // GPR32ZERO:sub_hi	----
7319	0, // GPR32ZERO:sub_lo	----
7320	0, // GPR32ZERO:sub_hi_then_sub_32	----
7321	0, // GPR32ZERO:sub_32_sub_hi_then_sub_32	----
7322	},	----
7323	{ // HI32	----
7324	0, // HI32:sub_32	----
7325	0, // HI32:sub_64	----
7326	0, // HI32:sub_dsp16_19	----
7327	0, // HI32:sub_dsp20	----
7328	0, // HI32:sub_dsp21	----
7329	0, // HI32:sub_dsp22	----
7330	0, // HI32:sub_dsp23	----
7331	0, // HI32:sub_hi	----
7332	0, // HI32:sub_lo	----
7333	0, // HI32:sub_hi_then_sub_32	----
7334	0, // HI32:sub_32_sub_hi_then_sub_32	----
7335	},	----
7336	{ // LO32	----
7337	0, // LO32:sub_32	----
7338	0, // LO32:sub_64	----
7339	0, // LO32:sub_dsp16_19	----
7340	0, // LO32:sub_dsp20	----
7341	0, // LO32:sub_dsp21	----
7342	0, // LO32:sub_dsp22	----
7343	0, // LO32:sub_dsp23	----
7344	0, // LO32:sub_hi	----
7345	0, // LO32:sub_lo	----
7346	0, // LO32:sub_hi_then_sub_32	----
7347	0, // LO32:sub_32_sub_hi_then_sub_32	----
7348	},	----
7349	{ // SP32	----
7350	0, // SP32:sub_32	----
7351	0, // SP32:sub_64	----
7352	0, // SP32:sub_dsp16_19	----
7353	0, // SP32:sub_dsp20	----
7354	0, // SP32:sub_dsp21	----
7355	0, // SP32:sub_dsp22	----
7356	0, // SP32:sub_dsp23	----
7357	0, // SP32:sub_hi	----
7358	0, // SP32:sub_lo	----
7359	0, // SP32:sub_hi_then_sub_32	----
7360	0, // SP32:sub_32_sub_hi_then_sub_32	----
7361	},	----
7362	{ // FGR64	----
7363	0, // FGR64:sub_32	----
7364	0, // FGR64:sub_64	----
7365	0, // FGR64:sub_dsp16_19	----
7366	0, // FGR64:sub_dsp20	----
7367	0, // FGR64:sub_dsp21	----
7368	0, // FGR64:sub_dsp22	----
7369	0, // FGR64:sub_dsp23	----
7370	0, // FGR64:sub_hi	----
7371	7, // FGR64:sub_lo -> FGR32	----
7372	0, // FGR64:sub_hi_then_sub_32	----
7373	0, // FGR64:sub_32_sub_hi_then_sub_32	----
7374	},	----
7375	{ // GPR64	----
7376	9, // GPR64:sub_32 -> GPR32	----
7377	0, // GPR64:sub_64	----
7378	0, // GPR64:sub_dsp16_19	----
7379	0, // GPR64:sub_dsp20	----
7380	0, // GPR64:sub_dsp21	----
7381	0, // GPR64:sub_dsp22	----
7382	0, // GPR64:sub_dsp23	----
7383	0, // GPR64:sub_hi	----
7384	0, // GPR64:sub_lo	----
7385	0, // GPR64:sub_hi_then_sub_32	----
7386	0, // GPR64:sub_32_sub_hi_then_sub_32	----
7387	},	----
7388	{ // GPR64_with_sub_32_in_GPR32NONZERO	----
7389	12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO	----
7390	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64	----
7391	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19	----
7392	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20	----
7393	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21	----
7394	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22	----
7395	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23	----
7396	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi	----
7397	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo	----
7398	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32	----
7399	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32	----
7400	},	----
7401	{ // AFGR64	----
7402	0, // AFGR64:sub_32	----
7403	0, // AFGR64:sub_64	----
7404	0, // AFGR64:sub_dsp16_19	----
7405	0, // AFGR64:sub_dsp20	----
7406	0, // AFGR64:sub_dsp21	----
7407	0, // AFGR64:sub_dsp22	----
7408	0, // AFGR64:sub_dsp23	----
7409	8, // AFGR64:sub_hi -> FGRCC	----
7410	8, // AFGR64:sub_lo -> FGRCC	----
7411	0, // AFGR64:sub_hi_then_sub_32	----
7412	0, // AFGR64:sub_32_sub_hi_then_sub_32	----
7413	},	----
7414	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	----
7415	13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP	----
7416	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64	----
7417	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19	----
7418	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20	----
7419	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21	----
7420	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22	----
7421	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23	----
7422	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi	----
7423	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo	----
7424	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32	----
7425	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	----
7426	},	----
7427	{ // GPR64_with_sub_32_in_CPU16Regs	----
7428	14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs	----
7429	0, // GPR64_with_sub_32_in_CPU16Regs:sub_64	----
7430	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19	----
7431	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20	----
7432	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21	----
7433	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22	----
7434	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23	----
7435	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi	----
7436	0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo	----
7437	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32	----
7438	0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32	----
7439	},	----
7440	{ // GPR64_with_sub_32_in_GPRMM16MoveP	----
7441	17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP	----
7442	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64	----
7443	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19	----
7444	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20	----
7445	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21	----
7446	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22	----
7447	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23	----
7448	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi	----
7449	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo	----
7450	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32	----
7451	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7452	},	----
7453	{ // GPR64_with_sub_32_in_GPRMM16Zero	----
7454	18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero	----
7455	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64	----
7456	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19	----
7457	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20	----
7458	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21	----
7459	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22	----
7460	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23	----
7461	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi	----
7462	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo	----
7463	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32	----
7464	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7465	},	----
7466	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	----
7467	19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero	----
7468	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64	----
7469	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	----
7470	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20	----
7471	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21	----
7472	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22	----
7473	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23	----
7474	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi	----
7475	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo	----
7476	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	----
7477	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7478	},	----
7479	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	----
7480	20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP	----
7481	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64	----
7482	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	----
7483	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	----
7484	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	----
7485	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	----
7486	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	----
7487	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi	----
7488	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo	----
7489	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	----
7490	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7491	},	----
7492	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	----
7493	21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond	----
7494	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64	----
7495	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19	----
7496	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20	----
7497	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21	----
7498	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22	----
7499	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23	----
7500	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi	----
7501	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo	----
7502	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7503	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7504	},	----
7505	{ // ACC64DSP	----
7506	0, // ACC64DSP:sub_32	----
7507	0, // ACC64DSP:sub_64	----
7508	0, // ACC64DSP:sub_dsp16_19	----
7509	0, // ACC64DSP:sub_dsp20	----
7510	0, // ACC64DSP:sub_dsp21	----
7511	0, // ACC64DSP:sub_dsp22	----
7512	0, // ACC64DSP:sub_dsp23	----
7513	24, // ACC64DSP:sub_hi -> HI32DSP	----
7514	25, // ACC64DSP:sub_lo -> LO32DSP	----
7515	0, // ACC64DSP:sub_hi_then_sub_32	----
7516	0, // ACC64DSP:sub_32_sub_hi_then_sub_32	----
7517	},	----
7518	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	----
7519	22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP	----
7520	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64	----
7521	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	----
7522	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20	----
7523	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21	----
7524	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22	----
7525	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23	----
7526	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi	----
7527	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo	----
7528	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	----
7529	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	----
7530	},	----
7531	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	----
7532	23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero	----
7533	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64	----
7534	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	----
7535	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	----
7536	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	----
7537	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	----
7538	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	----
7539	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi	----
7540	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo	----
7541	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	----
7542	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7543	},	----
7544	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	----
7545	26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond	----
7546	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	----
7547	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	----
7548	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	----
7549	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	----
7550	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	----
7551	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	----
7552	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	----
7553	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	----
7554	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7555	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7556	},	----
7557	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	----
7558	27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst	----
7559	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64	----
7560	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19	----
7561	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20	----
7562	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21	----
7563	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22	----
7564	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23	----
7565	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi	----
7566	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo	----
7567	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32	----
7568	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	----
7569	},	----
7570	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
7571	28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
7572	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	----
7573	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	----
7574	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	----
7575	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	----
7576	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	----
7577	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	----
7578	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	----
7579	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	----
7580	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	----
7581	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	----
7582	},	----
7583	{ // OCTEON_MPL	----
7584	0, // OCTEON_MPL:sub_32	----
7585	0, // OCTEON_MPL:sub_64	----
7586	0, // OCTEON_MPL:sub_dsp16_19	----
7587	0, // OCTEON_MPL:sub_dsp20	----
7588	0, // OCTEON_MPL:sub_dsp21	----
7589	0, // OCTEON_MPL:sub_dsp22	----
7590	0, // OCTEON_MPL:sub_dsp23	----
7591	0, // OCTEON_MPL:sub_hi	----
7592	0, // OCTEON_MPL:sub_lo	----
7593	0, // OCTEON_MPL:sub_hi_then_sub_32	----
7594	0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32	----
7595	},	----
7596	{ // OCTEON_P	----
7597	0, // OCTEON_P:sub_32	----
7598	0, // OCTEON_P:sub_64	----
7599	0, // OCTEON_P:sub_dsp16_19	----
7600	0, // OCTEON_P:sub_dsp20	----
7601	0, // OCTEON_P:sub_dsp21	----
7602	0, // OCTEON_P:sub_dsp22	----
7603	0, // OCTEON_P:sub_dsp23	----
7604	0, // OCTEON_P:sub_hi	----
7605	0, // OCTEON_P:sub_lo	----
7606	0, // OCTEON_P:sub_hi_then_sub_32	----
7607	0, // OCTEON_P:sub_32_sub_hi_then_sub_32	----
7608	},	----
7609	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
7610	29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
7611	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	----
7612	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	----
7613	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	----
7614	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	----
7615	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	----
7616	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	----
7617	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	----
7618	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	----
7619	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	----
7620	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	----
7621	},	----
7622	{ // ACC64	----
7623	0, // ACC64:sub_32	----
7624	0, // ACC64:sub_64	----
7625	0, // ACC64:sub_dsp16_19	----
7626	0, // ACC64:sub_dsp20	----
7627	0, // ACC64:sub_dsp21	----
7628	0, // ACC64:sub_dsp22	----
7629	0, // ACC64:sub_dsp23	----
7630	35, // ACC64:sub_hi -> HI32	----
7631	36, // ACC64:sub_lo -> LO32	----
7632	0, // ACC64:sub_hi_then_sub_32	----
7633	0, // ACC64:sub_32_sub_hi_then_sub_32	----
7634	},	----
7635	{ // GP64	----
7636	33, // GP64:sub_32 -> GP32	----
7637	0, // GP64:sub_64	----
7638	0, // GP64:sub_dsp16_19	----
7639	0, // GP64:sub_dsp20	----
7640	0, // GP64:sub_dsp21	----
7641	0, // GP64:sub_dsp22	----
7642	0, // GP64:sub_dsp23	----
7643	0, // GP64:sub_hi	----
7644	0, // GP64:sub_lo	----
7645	0, // GP64:sub_hi_then_sub_32	----
7646	0, // GP64:sub_32_sub_hi_then_sub_32	----
7647	},	----
7648	{ // GPR64_with_sub_32_in_CPURAReg	----
7649	30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg	----
7650	0, // GPR64_with_sub_32_in_CPURAReg:sub_64	----
7651	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19	----
7652	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20	----
7653	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21	----
7654	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22	----
7655	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23	----
7656	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi	----
7657	0, // GPR64_with_sub_32_in_CPURAReg:sub_lo	----
7658	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32	----
7659	0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32	----
7660	},	----
7661	{ // GPR64_with_sub_32_in_GPR32ZERO	----
7662	34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO	----
7663	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64	----
7664	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19	----
7665	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20	----
7666	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21	----
7667	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22	----
7668	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23	----
7669	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi	----
7670	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo	----
7671	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32	----
7672	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32	----
7673	},	----
7674	{ // HI64	----
7675	35, // HI64:sub_32 -> HI32	----
7676	0, // HI64:sub_64	----
7677	0, // HI64:sub_dsp16_19	----
7678	0, // HI64:sub_dsp20	----
7679	0, // HI64:sub_dsp21	----
7680	0, // HI64:sub_dsp22	----
7681	0, // HI64:sub_dsp23	----
7682	0, // HI64:sub_hi	----
7683	0, // HI64:sub_lo	----
7684	0, // HI64:sub_hi_then_sub_32	----
7685	0, // HI64:sub_32_sub_hi_then_sub_32	----
7686	},	----
7687	{ // LO64	----
7688	36, // LO64:sub_32 -> LO32	----
7689	0, // LO64:sub_64	----
7690	0, // LO64:sub_dsp16_19	----
7691	0, // LO64:sub_dsp20	----
7692	0, // LO64:sub_dsp21	----
7693	0, // LO64:sub_dsp22	----
7694	0, // LO64:sub_dsp23	----
7695	0, // LO64:sub_hi	----
7696	0, // LO64:sub_lo	----
7697	0, // LO64:sub_hi_then_sub_32	----
7698	0, // LO64:sub_32_sub_hi_then_sub_32	----
7699	},	----
7700	{ // SP64	----
7701	31, // SP64:sub_32 -> CPUSPReg	----
7702	0, // SP64:sub_64	----
7703	0, // SP64:sub_dsp16_19	----
7704	0, // SP64:sub_dsp20	----
7705	0, // SP64:sub_dsp21	----
7706	0, // SP64:sub_dsp22	----
7707	0, // SP64:sub_dsp23	----
7708	0, // SP64:sub_hi	----
7709	0, // SP64:sub_lo	----
7710	0, // SP64:sub_hi_then_sub_32	----
7711	0, // SP64:sub_32_sub_hi_then_sub_32	----
7712	},	----
7713	{ // MSA128B	----
7714	0, // MSA128B:sub_32	----
7715	38, // MSA128B:sub_64 -> FGR64	----
7716	0, // MSA128B:sub_dsp16_19	----
7717	0, // MSA128B:sub_dsp20	----
7718	0, // MSA128B:sub_dsp21	----
7719	0, // MSA128B:sub_dsp22	----
7720	0, // MSA128B:sub_dsp23	----
7721	0, // MSA128B:sub_hi	----
7722	7, // MSA128B:sub_lo -> FGR32	----
7723	0, // MSA128B:sub_hi_then_sub_32	----
7724	0, // MSA128B:sub_32_sub_hi_then_sub_32	----
7725	},	----
7726	{ // MSA128D	----
7727	0, // MSA128D:sub_32	----
7728	38, // MSA128D:sub_64 -> FGR64	----
7729	0, // MSA128D:sub_dsp16_19	----
7730	0, // MSA128D:sub_dsp20	----
7731	0, // MSA128D:sub_dsp21	----
7732	0, // MSA128D:sub_dsp22	----
7733	0, // MSA128D:sub_dsp23	----
7734	0, // MSA128D:sub_hi	----
7735	7, // MSA128D:sub_lo -> FGR32	----
7736	0, // MSA128D:sub_hi_then_sub_32	----
7737	0, // MSA128D:sub_32_sub_hi_then_sub_32	----
7738	},	----
7739	{ // MSA128H	----
7740	0, // MSA128H:sub_32	----
7741	38, // MSA128H:sub_64 -> FGR64	----
7742	0, // MSA128H:sub_dsp16_19	----
7743	0, // MSA128H:sub_dsp20	----
7744	0, // MSA128H:sub_dsp21	----
7745	0, // MSA128H:sub_dsp22	----
7746	0, // MSA128H:sub_dsp23	----
7747	0, // MSA128H:sub_hi	----
7748	7, // MSA128H:sub_lo -> FGR32	----
7749	0, // MSA128H:sub_hi_then_sub_32	----
7750	0, // MSA128H:sub_32_sub_hi_then_sub_32	----
7751	},	----
7752	{ // MSA128W	----
7753	0, // MSA128W:sub_32	----
7754	38, // MSA128W:sub_64 -> FGR64	----
7755	0, // MSA128W:sub_dsp16_19	----
7756	0, // MSA128W:sub_dsp20	----
7757	0, // MSA128W:sub_dsp21	----
7758	0, // MSA128W:sub_dsp22	----
7759	0, // MSA128W:sub_dsp23	----
7760	0, // MSA128W:sub_hi	----
7761	7, // MSA128W:sub_lo -> FGR32	----
7762	0, // MSA128W:sub_hi_then_sub_32	----
7763	0, // MSA128W:sub_32_sub_hi_then_sub_32	----
7764	},	----
7765	{ // MSA128WEvens	----
7766	0, // MSA128WEvens:sub_32	----
7767	38, // MSA128WEvens:sub_64 -> FGR64	----
7768	0, // MSA128WEvens:sub_dsp16_19	----
7769	0, // MSA128WEvens:sub_dsp20	----
7770	0, // MSA128WEvens:sub_dsp21	----
7771	0, // MSA128WEvens:sub_dsp22	----
7772	0, // MSA128WEvens:sub_dsp23	----
7773	0, // MSA128WEvens:sub_hi	----
7774	8, // MSA128WEvens:sub_lo -> FGRCC	----
7775	0, // MSA128WEvens:sub_hi_then_sub_32	----
7776	0, // MSA128WEvens:sub_32_sub_hi_then_sub_32	----
7777	},	----
7778	{ // ACC128	----
7779	36, // ACC128:sub_32 -> LO32	----
7780	0, // ACC128:sub_64	----
7781	0, // ACC128:sub_dsp16_19	----
7782	0, // ACC128:sub_dsp20	----
7783	0, // ACC128:sub_dsp21	----
7784	0, // ACC128:sub_dsp22	----
7785	0, // ACC128:sub_dsp23	----
7786	62, // ACC128:sub_hi -> HI64	----
7787	63, // ACC128:sub_lo -> LO64	----
7788	35, // ACC128:sub_hi_then_sub_32 -> HI32	----
7789	58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64	----
7790	},	----
7791	};	----
7792	assert(RC && "Missing regclass");	0
7793	if (!Idx) return RC;	0
7794	--Idx;	0
7795	assert(Idx < 11 && "Bad subreg");	0
7796	unsigned TV = Table[RC->getID()][Idx];	0
7797	return TV ? getRegClass(TV - 1) : nullptr;	0
7798	}	----
7799		----
7800	/// Get the weight in units of pressure for this register class.	----
7801	const RegClassWeight &MipsGenRegisterInfo::	0
7802	getRegClassWeight(const TargetRegisterClass *RC) const {	----
7803	static const RegClassWeight RCWeightTable[] = {	----
7804	{2, 64}, // MSA128F16	----
7805	{0, 0}, // CCR	----
7806	{0, 0}, // COP0	----
7807	{0, 0}, // COP2	----
7808	{0, 0}, // COP3	----
7809	{1, 32}, // DSPR	----
7810	{1, 32}, // FGR32	----
7811	{1, 32}, // FGRCC	----
7812	{1, 32}, // GPR32	----
7813	{0, 0}, // HWRegs	----
7814	{0, 0}, // MSACtrl	----
7815	{1, 31}, // GPR32NONZERO	----
7816	{1, 9}, // CPU16RegsPlusSP	----
7817	{1, 8}, // CPU16Regs	----
7818	{0, 0}, // FCC	----
7819	{1, 8}, // GPRMM16	----
7820	{1, 8}, // GPRMM16MoveP	----
7821	{1, 8}, // GPRMM16Zero	----
7822	{1, 7}, // CPU16Regs_and_GPRMM16Zero	----
7823	{1, 7}, // GPR32NONZERO_and_GPRMM16MoveP	----
7824	{1, 5}, // GPRMM16MovePPairSecond	----
7825	{1, 4}, // CPU16Regs_and_GPRMM16MoveP	----
7826	{1, 4}, // GPRMM16MoveP_and_GPRMM16Zero	----
7827	{1, 4}, // HI32DSP	----
7828	{1, 4}, // LO32DSP	----
7829	{1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond	----
7830	{1, 3}, // GPRMM16MovePPairFirst	----
7831	{1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
7832	{1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
7833	{1, 1}, // CPURAReg	----
7834	{1, 1}, // CPUSPReg	----
7835	{1, 1}, // DSPCC	----
7836	{1, 1}, // GP32	----
7837	{1, 1}, // GPR32ZERO	----
7838	{1, 1}, // HI32	----
7839	{1, 1}, // LO32	----
7840	{1, 1}, // SP32	----
7841	{2, 64}, // FGR64	----
7842	{1, 32}, // GPR64	----
7843	{1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO	----
7844	{2, 32}, // AFGR64	----
7845	{1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP	----
7846	{1, 8}, // GPR64_with_sub_32_in_CPU16Regs	----
7847	{1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP	----
7848	{1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero	----
7849	{1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	----
7850	{1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	----
7851	{1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	----
7852	{2, 8}, // ACC64DSP	----
7853	{1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	----
7854	{1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	----
7855	{1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	----
7856	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	----
7857	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	----
7858	{0, 0}, // OCTEON_MPL	----
7859	{0, 0}, // OCTEON_P	----
7860	{1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	----
7861	{2, 2}, // ACC64	----
7862	{1, 1}, // GP64	----
7863	{1, 1}, // GPR64_with_sub_32_in_CPURAReg	----
7864	{1, 1}, // GPR64_with_sub_32_in_GPR32ZERO	----
7865	{1, 1}, // HI64	----
7866	{1, 1}, // LO64	----
7867	{1, 1}, // SP64	----
7868	{2, 64}, // MSA128B	----
7869	{2, 64}, // MSA128D	----
7870	{2, 64}, // MSA128H	----
7871	{2, 64}, // MSA128W	----
7872	{2, 32}, // MSA128WEvens	----
7873	{2, 2}, // ACC128	----
7874	};	----
7875	return RCWeightTable[RC->getID()];	0
7876	}	----
7877		----
7878	/// Get the weight in units of pressure for this register unit.	----
7879	unsigned MipsGenRegisterInfo::	0
7880	getRegUnitWeight(unsigned RegUnit) const {	----
7881	assert(RegUnit < 321 && "invalid register unit");	0
7882	// All register units have unit weight.	----
7883	return 1;	0
7884	}	----
7885		----
7886		----
7887	// Get the number of dimensions of register pressure.	----
7888	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {	4	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
7889	return 20;	4	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
7890	}	----
7891		----
7892	// Get the name of this register unit pressure set.	----
7893	const char *MipsGenRegisterInfo::	0
7894	getRegPressureSetName(unsigned Idx) const {	----
7895	static const char *PressureNameTable[] = {	----
7896	"DSPCC",	----
7897	"GPR32ZERO",	----
7898	"GPR64_with_sub_32_in_CPURAReg",	----
7899	"HI32",	----
7900	"GPRMM16MovePPairFirst",	----
7901	"CPU16Regs_and_GPRMM16MoveP",	----
7902	"HI32DSP",	----
7903	"LO32DSP",	----
7904	"GPRMM16MovePPairSecond",	----
7905	"GPRMM16MoveP",	----
7906	"ACC64DSP",	----
7907	"CPU16Regs",	----
7908	"GPRMM16Zero_with_GPRMM16MovePPairSecond",	----
7909	"CPU16Regs_with_GPRMM16MovePPairSecond",	----
7910	"CPU16Regs_with_GPRMM16MoveP",	----
7911	"DSPR",	----
7912	"FGR32",	----
7913	"MSA128WEvens",	----
7914	"FGR32_with_MSA128WEvens",	----
7915	"MSA128F16",	----
7916	};	----
7917	return PressureNameTable[Idx];	0
7918	}	----
7919		----
7920	// Get the register unit pressure limit for this dimension.	----
7921	// This limit must be adjusted dynamically for reserved registers.	----
7922	unsigned MipsGenRegisterInfo::	0
7923	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {	----
7924	static const uint8_t PressureLimitTable[] = {	----
7925	1, // 0: DSPCC	----
7926	1, // 1: GPR32ZERO	----
7927	1, // 2: GPR64_with_sub_32_in_CPURAReg	----
7928	2, // 3: HI32	----
7929	3, // 4: GPRMM16MovePPairFirst	----
7930	5, // 5: CPU16Regs_and_GPRMM16MoveP	----
7931	5, // 6: HI32DSP	----
7932	5, // 7: LO32DSP	----
7933	6, // 8: GPRMM16MovePPairSecond	----
7934	8, // 9: GPRMM16MoveP	----
7935	8, // 10: ACC64DSP	----
7936	10, // 11: CPU16Regs	----
7937	10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond	----
7938	11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond	----
7939	13, // 14: CPU16Regs_with_GPRMM16MoveP	----
7940	32, // 15: DSPR	----
7941	32, // 16: FGR32	----
7942	32, // 17: MSA128WEvens	----
7943	48, // 18: FGR32_with_MSA128WEvens	----
7944	64, // 19: MSA128F16	----
7945	};	----
7946	return PressureLimitTable[Idx];	0
7947	}	----
7948		----
7949	/// Table of pressure sets per register class or unit.	----
7950	static const int RCSetsTable[] = {	----
7951	/* 0 */ 0, -1,	----
7952	/* 2 */ 6, 10, -1,	----
7953	/* 5 */ 3, 6, 7, 10, -1,	----
7954	/* 10 */ 2, 15, -1,	----
7955	/* 13 */ 8, 12, 13, 15, -1,	----
7956	/* 18 */ 9, 14, 15, -1,	----
7957	/* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,	----
7958	/* 30 */ 5, 9, 11, 13, 14, 15, -1,	----
7959	/* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,	----
7960	/* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,	----
7961	/* 53 */ 16, 18, 19, -1,	----
7962	/* 57 */ 16, 17, 18, 19, -1,	----
7963	};	----
7964		----
7965	/// Get the dimensions of register pressure impacted by this register class.	----
7966	/// Returns a -1 terminated array of pressure set IDs	----
7967	const int *MipsGenRegisterInfo::	0
7968	getRegClassPressureSets(const TargetRegisterClass *RC) const {	----
7969	static const uint8_t RCSetStartTable[] = {	----
7970	55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};	----
7971	return &RCSetsTable[RCSetStartTable[RC->getID()]];	0
7972	}	----
7973		----
7974	/// Get the dimensions of register pressure impacted by this register unit.	----
7975	/// Returns a -1 terminated array of pressure set IDs	----
7976	const int *MipsGenRegisterInfo::	0
7977	getRegUnitPressureSets(unsigned RegUnit) const {	----
7978	assert(RegUnit < 321 && "invalid register unit");	0
7979	static const uint8_t RUSetStartTable[] = {	----
7980	11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};	----
7981	return &RCSetsTable[RUSetStartTable[RegUnit]];	0
7982	}	----
7983		----
7984	extern const MCRegisterDesc MipsRegDesc[];	----
7985	extern const int16_t MipsRegDiffLists[];	----
7986	extern const LaneBitmask MipsLaneMaskLists[];	----
7987	extern const char MipsRegStrings[];	----
7988	extern const char MipsRegClassStrings[];	----
7989	extern const MCPhysReg MipsRegUnitRoots[][2];	----
7990	extern const uint16_t MipsSubRegIdxLists[];	----
7991	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];	----
7992	extern const uint16_t MipsRegEncodingTable[];	----
7993	// Mips Dwarf<->LLVM register mappings.	----
7994	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];	----
7995	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;	----
7996		----
7997	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];	----
7998	extern const unsigned MipsEHFlavour0Dwarf2LSize;	----
7999		----
8000	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];	----
8001	extern const unsigned MipsDwarfFlavour0L2DwarfSize;	----
8002		----
8003	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];	----
8004	extern const unsigned MipsEHFlavour0L2DwarfSize;	----
8005		----
8006	MipsGenRegisterInfo::	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8007	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,	----
8008	unsigned PC, unsigned HwMode)	----
8009	: TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,	----
8010	SubRegIndexNameTable, SubRegIndexLaneMaskTable,	----
8011	LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8012	InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8013	MipsMCRegisterClasses, 70,	----
8014	MipsRegUnitRoots,	----
8015	321,	----
8016	MipsRegDiffLists,	----
8017	MipsLaneMaskLists,	----
8018	MipsRegStrings,	----
8019	MipsRegClassStrings,	----
8020	MipsSubRegIdxLists,	----
8021	12,	----
8022	MipsSubRegIdxRanges,	----
8023	MipsRegEncodingTable);	----
8024		----
8025	switch (DwarfFlavour) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8026	default:	0
8027	llvm_unreachable("Unknown DWARF flavour");	0
8028	case 0:	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8029	mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8030	break;	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8031	}	----
8032	switch (EHFlavour) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8033	default:	0
8034	llvm_unreachable("Unknown DWARF flavour");	0
8035	case 0:	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8036	mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8037	break;	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8038	}	----
8039	switch (DwarfFlavour) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8040	default:	0
8041	llvm_unreachable("Unknown DWARF flavour");	0
8042	case 0:	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8043	mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8044	break;	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8045	}	----
8046	switch (EHFlavour) {	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8047	default:	0
8048	llvm_unreachable("Unknown DWARF flavour");	0
8049	case 0:	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8050	mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8051	break;	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8052	}	----
8053	}	10	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8054		----
8055	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };	----
8056	static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	----
8057	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };	----
8058	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	----
8059	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };	----
8060	static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };	----
8061	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };	----
8062	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };	----
8063	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };	----
8064	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };	----
8065	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	----
8066	static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };	----
8067	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	----
8068	static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };	----
8069	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	----
8070	static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	----
8071	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	----
8072	static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };	----
8073	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	----
8074	static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	----
8075	static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	----
8076	static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	----
8077		----
8078		----
8079	ArrayRef MipsGenRegisterInfo::getRegMasks() const {	0
8080	static const uint32_t *const Masks[] = {	----
8081	CSR_Interrupt_32_RegMask,	----
8082	CSR_Interrupt_32R6_RegMask,	----
8083	CSR_Interrupt_64_RegMask,	----
8084	CSR_Interrupt_64R6_RegMask,	----
8085	CSR_Mips16RetHelper_RegMask,	----
8086	CSR_N32_RegMask,	----
8087	CSR_N64_RegMask,	----
8088	CSR_O32_RegMask,	----
8089	CSR_O32_FP64_RegMask,	----
8090	CSR_O32_FPXX_RegMask,	----
8091	CSR_SingleFloatOnly_RegMask,	----
8092	};	----
8093	return ArrayRef(Masks);	0
8094	}	----
8095		----
8096	bool MipsGenRegisterInfo::	0
8097	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {	----
8098	return	----
8099	false;	0
8100	}	----
8101		----
8102	bool MipsGenRegisterInfo::	0
8103	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {	----
8104	return	----
8105	false;	0
8106	}	----
8107		----
8108	bool MipsGenRegisterInfo::	0
8109	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {	----
8110	return	----
8111	false;	0
8112	}	----
8113		----
8114	bool MipsGenRegisterInfo::	0
8115	isConstantPhysReg(MCRegister PhysReg) const {	----
8116	return	----
8117	PhysReg == Mips::ZERO \|\|	0
8118	PhysReg == Mips::ZERO_64 \|\|	0
8119	false;	0
8120	}	----
8121		----
8122	ArrayRef MipsGenRegisterInfo::getRegMaskNames() const {	0
8123	static const char *Names[] = {	----
8124	"CSR_Interrupt_32",	----
8125	"CSR_Interrupt_32R6",	----
8126	"CSR_Interrupt_64",	----
8127	"CSR_Interrupt_64R6",	----
8128	"CSR_Mips16RetHelper",	----
8129	"CSR_N32",	----
8130	"CSR_N64",	----
8131	"CSR_O32",	----
8132	"CSR_O32_FP64",	----
8133	"CSR_O32_FPXX",	----
8134	"CSR_SingleFloatOnly",	----
8135	};	----
8136	return ArrayRef(Names);	0
8137	}	----
8138		----
8139	const MipsFrameLowering *	----
8140	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {	0
8141	return static_cast(	----
8142	MF.getSubtarget().getFrameLowering());	0
8143	}	----
8144		----
8145	} // end namespace llvm	----
8146		----
8147	#endif // GET_REGINFO_TARGET_DESC	----
8148		----
8149		----

Functions Report

Function name	Number of hits
_ZN4llvmL22InitMipsMCRegisterInfoEPNS_14MCRegisterInfoEjjjj	2
_ZN4llvmL19FGR32AltOrderSelectERKNS_15MachineFunctionE	0
_ZN4llvmL26FGR32GetRawAllocationOrderERKNS_15MachineFunctionE	0
_ZN4llvmL19FGR64AltOrderSelectERKNS_15MachineFunctionE	0
_ZN4llvmL26FGR64GetRawAllocationOrderERKNS_15MachineFunctionE	0
_ZNK4llvm19MipsGenRegisterInfo24composeSubRegIndicesImplEjj	0
_ZNK4llvm19MipsGenRegisterInfo30composeSubRegIndexLaneMaskImplEjNS_11LaneBitmaskE	0
_ZNK4llvm19MipsGenRegisterInfo37reverseComposeSubRegIndexLaneMaskImplEjNS_11LaneBitmaskE	0
_ZNK4llvm19MipsGenRegisterInfo21getSubClassWithSubRegEPKNS_19TargetRegisterClassEj	0
_ZNK4llvm19MipsGenRegisterInfo19getSubRegisterClassEPKNS_19TargetRegisterClassEj	0
_ZNK4llvm19MipsGenRegisterInfo17getRegClassWeightEPKNS_19TargetRegisterClassE	0
_ZNK4llvm19MipsGenRegisterInfo16getRegUnitWeightEj	0
_ZNK4llvm19MipsGenRegisterInfo21getNumRegPressureSetsEv	4
_ZNK4llvm19MipsGenRegisterInfo21getRegPressureSetNameEj	0
_ZNK4llvm19MipsGenRegisterInfo22getRegPressureSetLimitERKNS_15MachineFunctionEj	0
_ZNK4llvm19MipsGenRegisterInfo23getRegClassPressureSetsEPKNS_19TargetRegisterClassE	0
_ZNK4llvm19MipsGenRegisterInfo22getRegUnitPressureSetsEj	0
_ZN4llvm19MipsGenRegisterInfoC2Ejjjjj	10
_ZNK4llvm19MipsGenRegisterInfo11getRegMasksEv	0
_ZNK4llvm19MipsGenRegisterInfo24isGeneralPurposeRegisterERKNS_15MachineFunctionENS_10MCRegisterE	0
_ZNK4llvm19MipsGenRegisterInfo15isFixedRegisterERKNS_15MachineFunctionENS_10MCRegisterE	0
_ZNK4llvm19MipsGenRegisterInfo18isArgumentRegisterERKNS_15MachineFunctionENS_10MCRegisterE	0
_ZNK4llvm19MipsGenRegisterInfo17isConstantPhysRegENS_10MCRegisterE	0
_ZNK4llvm19MipsGenRegisterInfo15getRegMaskNamesEv	0
_ZN4llvm19MipsGenRegisterInfo16getFrameLoweringERKNS_15MachineFunctionE	0

Coverage Diff

Line Number	../DebugInfoTest/example_mips_dbg.ll BUT NOT ../DebugInfoTest/example_mips.ll	Line Number	../DebugInfoTest/example_mips.ll BUT NOT ../DebugInfoTest/example_mips_dbg.ll
1	/===- TableGen'erated file -------------------------------------- C++ --===\	1	/===- TableGen'erated file -------------------------------------- C++ --===\
2	\|* *\|	2	\|* *\|
3	\|* Target Register Enum Values *\|	3	\|* Target Register Enum Values *\|
4	\|* *\|	4	\|* *\|
5	\|* Automatically generated file, do not edit! *\|	5	\|* Automatically generated file, do not edit! *\|
6	\|* *\|	6	\|* *\|
7	\===----------------------------------------------------------------------===/	7	\===----------------------------------------------------------------------===/
8		8
9		9
10	#ifdef GET_REGINFO_ENUM	10	#ifdef GET_REGINFO_ENUM
11	#undef GET_REGINFO_ENUM	11	#undef GET_REGINFO_ENUM
12		12
13	namespace llvm {	13	namespace llvm {
14		14
15	class MCRegisterClass;	15	class MCRegisterClass;
16	extern const MCRegisterClass MipsMCRegisterClasses[];	16	extern const MCRegisterClass MipsMCRegisterClasses[];
17		17
18	namespace Mips {	18	namespace Mips {
19	enum {	19	enum {
20	NoRegister,	20	NoRegister,
21	AT = 1,	21	AT = 1,
22	DSPCCond = 2,	22	DSPCCond = 2,
23	DSPCarry = 3,	23	DSPCarry = 3,
24	DSPEFI = 4,	24	DSPEFI = 4,
25	DSPOutFlag = 5,	25	DSPOutFlag = 5,
26	DSPPos = 6,	26	DSPPos = 6,
27	DSPSCount = 7,	27	DSPSCount = 7,
28	FP = 8,	28	FP = 8,
29	GP = 9,	29	GP = 9,
30	MSAAccess = 10,	30	MSAAccess = 10,
31	MSACSR = 11,	31	MSACSR = 11,
32	MSAIR = 12,	32	MSAIR = 12,
33	MSAMap = 13,	33	MSAMap = 13,
34	MSAModify = 14,	34	MSAModify = 14,
35	MSARequest = 15,	35	MSARequest = 15,
36	MSASave = 16,	36	MSASave = 16,
37	MSAUnmap = 17,	37	MSAUnmap = 17,
38	PC = 18,	38	PC = 18,
39	RA = 19,	39	RA = 19,
40	SP = 20,	40	SP = 20,
41	ZERO = 21,	41	ZERO = 21,
42	A0 = 22,	42	A0 = 22,
43	A1 = 23,	43	A1 = 23,
44	A2 = 24,	44	A2 = 24,
45	A3 = 25,	45	A3 = 25,
46	AC0 = 26,	46	AC0 = 26,
47	AC1 = 27,	47	AC1 = 27,
48	AC2 = 28,	48	AC2 = 28,
49	AC3 = 29,	49	AC3 = 29,
50	AT_64 = 30,	50	AT_64 = 30,
51	COP00 = 31,	51	COP00 = 31,
52	COP01 = 32,	52	COP01 = 32,
53	COP02 = 33,	53	COP02 = 33,
54	COP03 = 34,	54	COP03 = 34,
55	COP04 = 35,	55	COP04 = 35,
56	COP05 = 36,	56	COP05 = 36,
57	COP06 = 37,	57	COP06 = 37,
58	COP07 = 38,	58	COP07 = 38,
59	COP08 = 39,	59	COP08 = 39,
60	COP09 = 40,	60	COP09 = 40,
61	COP20 = 41,	61	COP20 = 41,
62	COP21 = 42,	62	COP21 = 42,
63	COP22 = 43,	63	COP22 = 43,
64	COP23 = 44,	64	COP23 = 44,
65	COP24 = 45,	65	COP24 = 45,
66	COP25 = 46,	66	COP25 = 46,
67	COP26 = 47,	67	COP26 = 47,
68	COP27 = 48,	68	COP27 = 48,
69	COP28 = 49,	69	COP28 = 49,
70	COP29 = 50,	70	COP29 = 50,
71	COP30 = 51,	71	COP30 = 51,
72	COP31 = 52,	72	COP31 = 52,
73	COP32 = 53,	73	COP32 = 53,
74	COP33 = 54,	74	COP33 = 54,
75	COP34 = 55,	75	COP34 = 55,
76	COP35 = 56,	76	COP35 = 56,
77	COP36 = 57,	77	COP36 = 57,
78	COP37 = 58,	78	COP37 = 58,
79	COP38 = 59,	79	COP38 = 59,
80	COP39 = 60,	80	COP39 = 60,
81	COP010 = 61,	81	COP010 = 61,
82	COP011 = 62,	82	COP011 = 62,
83	COP012 = 63,	83	COP012 = 63,
84	COP013 = 64,	84	COP013 = 64,
85	COP014 = 65,	85	COP014 = 65,
86	COP015 = 66,	86	COP015 = 66,
87	COP016 = 67,	87	COP016 = 67,
88	COP017 = 68,	88	COP017 = 68,
89	COP018 = 69,	89	COP018 = 69,
90	COP019 = 70,	90	COP019 = 70,
91	COP020 = 71,	91	COP020 = 71,
92	COP021 = 72,	92	COP021 = 72,
93	COP022 = 73,	93	COP022 = 73,
94	COP023 = 74,	94	COP023 = 74,
95	COP024 = 75,	95	COP024 = 75,
96	COP025 = 76,	96	COP025 = 76,
97	COP026 = 77,	97	COP026 = 77,
98	COP027 = 78,	98	COP027 = 78,
99	COP028 = 79,	99	COP028 = 79,
100	COP029 = 80,	100	COP029 = 80,
101	COP030 = 81,	101	COP030 = 81,
102	COP031 = 82,	102	COP031 = 82,
103	COP210 = 83,	103	COP210 = 83,
104	COP211 = 84,	104	COP211 = 84,
105	COP212 = 85,	105	COP212 = 85,
106	COP213 = 86,	106	COP213 = 86,
107	COP214 = 87,	107	COP214 = 87,
108	COP215 = 88,	108	COP215 = 88,
109	COP216 = 89,	109	COP216 = 89,
110	COP217 = 90,	110	COP217 = 90,
111	COP218 = 91,	111	COP218 = 91,
112	COP219 = 92,	112	COP219 = 92,
113	COP220 = 93,	113	COP220 = 93,
114	COP221 = 94,	114	COP221 = 94,
115	COP222 = 95,	115	COP222 = 95,
116	COP223 = 96,	116	COP223 = 96,
117	COP224 = 97,	117	COP224 = 97,
118	COP225 = 98,	118	COP225 = 98,
119	COP226 = 99,	119	COP226 = 99,
120	COP227 = 100,	120	COP227 = 100,
121	COP228 = 101,	121	COP228 = 101,
122	COP229 = 102,	122	COP229 = 102,
123	COP230 = 103,	123	COP230 = 103,
124	COP231 = 104,	124	COP231 = 104,
125	COP310 = 105,	125	COP310 = 105,
126	COP311 = 106,	126	COP311 = 106,
127	COP312 = 107,	127	COP312 = 107,
128	COP313 = 108,	128	COP313 = 108,
129	COP314 = 109,	129	COP314 = 109,
130	COP315 = 110,	130	COP315 = 110,
131	COP316 = 111,	131	COP316 = 111,
132	COP317 = 112,	132	COP317 = 112,
133	COP318 = 113,	133	COP318 = 113,
134	COP319 = 114,	134	COP319 = 114,
135	COP320 = 115,	135	COP320 = 115,
136	COP321 = 116,	136	COP321 = 116,
137	COP322 = 117,	137	COP322 = 117,
138	COP323 = 118,	138	COP323 = 118,
139	COP324 = 119,	139	COP324 = 119,
140	COP325 = 120,	140	COP325 = 120,
141	COP326 = 121,	141	COP326 = 121,
142	COP327 = 122,	142	COP327 = 122,
143	COP328 = 123,	143	COP328 = 123,
144	COP329 = 124,	144	COP329 = 124,
145	COP330 = 125,	145	COP330 = 125,
146	COP331 = 126,	146	COP331 = 126,
147	D0 = 127,	147	D0 = 127,
148	D1 = 128,	148	D1 = 128,
149	D2 = 129,	149	D2 = 129,
150	D3 = 130,	150	D3 = 130,
151	D4 = 131,	151	D4 = 131,
152	D5 = 132,	152	D5 = 132,
153	D6 = 133,	153	D6 = 133,
154	D7 = 134,	154	D7 = 134,
155	D8 = 135,	155	D8 = 135,
156	D9 = 136,	156	D9 = 136,
157	D10 = 137,	157	D10 = 137,
158	D11 = 138,	158	D11 = 138,
159	D12 = 139,	159	D12 = 139,
160	D13 = 140,	160	D13 = 140,
161	D14 = 141,	161	D14 = 141,
162	D15 = 142,	162	D15 = 142,
163	DSPOutFlag20 = 143,	163	DSPOutFlag20 = 143,
164	DSPOutFlag21 = 144,	164	DSPOutFlag21 = 144,
165	DSPOutFlag22 = 145,	165	DSPOutFlag22 = 145,
166	DSPOutFlag23 = 146,	166	DSPOutFlag23 = 146,
167	F0 = 147,	167	F0 = 147,
168	F1 = 148,	168	F1 = 148,
169	F2 = 149,	169	F2 = 149,
170	F3 = 150,	170	F3 = 150,
171	F4 = 151,	171	F4 = 151,
172	F5 = 152,	172	F5 = 152,
173	F6 = 153,	173	F6 = 153,
174	F7 = 154,	174	F7 = 154,
175	F8 = 155,	175	F8 = 155,
176	F9 = 156,	176	F9 = 156,
177	F10 = 157,	177	F10 = 157,
178	F11 = 158,	178	F11 = 158,
179	F12 = 159,	179	F12 = 159,
180	F13 = 160,	180	F13 = 160,
181	F14 = 161,	181	F14 = 161,
182	F15 = 162,	182	F15 = 162,
183	F16 = 163,	183	F16 = 163,
184	F17 = 164,	184	F17 = 164,
185	F18 = 165,	185	F18 = 165,
186	F19 = 166,	186	F19 = 166,
187	F20 = 167,	187	F20 = 167,
188	F21 = 168,	188	F21 = 168,
189	F22 = 169,	189	F22 = 169,
190	F23 = 170,	190	F23 = 170,
191	F24 = 171,	191	F24 = 171,
192	F25 = 172,	192	F25 = 172,
193	F26 = 173,	193	F26 = 173,
194	F27 = 174,	194	F27 = 174,
195	F28 = 175,	195	F28 = 175,
196	F29 = 176,	196	F29 = 176,
197	F30 = 177,	197	F30 = 177,
198	F31 = 178,	198	F31 = 178,
199	FCC0 = 179,	199	FCC0 = 179,
200	FCC1 = 180,	200	FCC1 = 180,
201	FCC2 = 181,	201	FCC2 = 181,
202	FCC3 = 182,	202	FCC3 = 182,
203	FCC4 = 183,	203	FCC4 = 183,
204	FCC5 = 184,	204	FCC5 = 184,
205	FCC6 = 185,	205	FCC6 = 185,
206	FCC7 = 186,	206	FCC7 = 186,
207	FCR0 = 187,	207	FCR0 = 187,
208	FCR1 = 188,	208	FCR1 = 188,
209	FCR2 = 189,	209	FCR2 = 189,
210	FCR3 = 190,	210	FCR3 = 190,
211	FCR4 = 191,	211	FCR4 = 191,
212	FCR5 = 192,	212	FCR5 = 192,
213	FCR6 = 193,	213	FCR6 = 193,
214	FCR7 = 194,	214	FCR7 = 194,
215	FCR8 = 195,	215	FCR8 = 195,
216	FCR9 = 196,	216	FCR9 = 196,
217	FCR10 = 197,	217	FCR10 = 197,
218	FCR11 = 198,	218	FCR11 = 198,
219	FCR12 = 199,	219	FCR12 = 199,
220	FCR13 = 200,	220	FCR13 = 200,
221	FCR14 = 201,	221	FCR14 = 201,
222	FCR15 = 202,	222	FCR15 = 202,
223	FCR16 = 203,	223	FCR16 = 203,
224	FCR17 = 204,	224	FCR17 = 204,
225	FCR18 = 205,	225	FCR18 = 205,
226	FCR19 = 206,	226	FCR19 = 206,
227	FCR20 = 207,	227	FCR20 = 207,
228	FCR21 = 208,	228	FCR21 = 208,
229	FCR22 = 209,	229	FCR22 = 209,
230	FCR23 = 210,	230	FCR23 = 210,
231	FCR24 = 211,	231	FCR24 = 211,
232	FCR25 = 212,	232	FCR25 = 212,
233	FCR26 = 213,	233	FCR26 = 213,
234	FCR27 = 214,	234	FCR27 = 214,
235	FCR28 = 215,	235	FCR28 = 215,
236	FCR29 = 216,	236	FCR29 = 216,
237	FCR30 = 217,	237	FCR30 = 217,
238	FCR31 = 218,	238	FCR31 = 218,
239	FP_64 = 219,	239	FP_64 = 219,
240	F_HI0 = 220,	240	F_HI0 = 220,
241	F_HI1 = 221,	241	F_HI1 = 221,
242	F_HI2 = 222,	242	F_HI2 = 222,
243	F_HI3 = 223,	243	F_HI3 = 223,
244	F_HI4 = 224,	244	F_HI4 = 224,
245	F_HI5 = 225,	245	F_HI5 = 225,
246	F_HI6 = 226,	246	F_HI6 = 226,
247	F_HI7 = 227,	247	F_HI7 = 227,
248	F_HI8 = 228,	248	F_HI8 = 228,
249	F_HI9 = 229,	249	F_HI9 = 229,
250	F_HI10 = 230,	250	F_HI10 = 230,
251	F_HI11 = 231,	251	F_HI11 = 231,
252	F_HI12 = 232,	252	F_HI12 = 232,
253	F_HI13 = 233,	253	F_HI13 = 233,
254	F_HI14 = 234,	254	F_HI14 = 234,
255	F_HI15 = 235,	255	F_HI15 = 235,
256	F_HI16 = 236,	256	F_HI16 = 236,
257	F_HI17 = 237,	257	F_HI17 = 237,
258	F_HI18 = 238,	258	F_HI18 = 238,
259	F_HI19 = 239,	259	F_HI19 = 239,
260	F_HI20 = 240,	260	F_HI20 = 240,
261	F_HI21 = 241,	261	F_HI21 = 241,
262	F_HI22 = 242,	262	F_HI22 = 242,
263	F_HI23 = 243,	263	F_HI23 = 243,
264	F_HI24 = 244,	264	F_HI24 = 244,
265	F_HI25 = 245,	265	F_HI25 = 245,
266	F_HI26 = 246,	266	F_HI26 = 246,
267	F_HI27 = 247,	267	F_HI27 = 247,
268	F_HI28 = 248,	268	F_HI28 = 248,
269	F_HI29 = 249,	269	F_HI29 = 249,
270	F_HI30 = 250,	270	F_HI30 = 250,
271	F_HI31 = 251,	271	F_HI31 = 251,
272	GP_64 = 252,	272	GP_64 = 252,
273	HI0 = 253,	273	HI0 = 253,
274	HI1 = 254,	274	HI1 = 254,
275	HI2 = 255,	275	HI2 = 255,
276	HI3 = 256,	276	HI3 = 256,
277	HWR0 = 257,	277	HWR0 = 257,
278	HWR1 = 258,	278	HWR1 = 258,
279	HWR2 = 259,	279	HWR2 = 259,
280	HWR3 = 260,	280	HWR3 = 260,
281	HWR4 = 261,	281	HWR4 = 261,
282	HWR5 = 262,	282	HWR5 = 262,
283	HWR6 = 263,	283	HWR6 = 263,
284	HWR7 = 264,	284	HWR7 = 264,
285	HWR8 = 265,	285	HWR8 = 265,
286	HWR9 = 266,	286	HWR9 = 266,
287	HWR10 = 267,	287	HWR10 = 267,
288	HWR11 = 268,	288	HWR11 = 268,
289	HWR12 = 269,	289	HWR12 = 269,
290	HWR13 = 270,	290	HWR13 = 270,
291	HWR14 = 271,	291	HWR14 = 271,
292	HWR15 = 272,	292	HWR15 = 272,
293	HWR16 = 273,	293	HWR16 = 273,
294	HWR17 = 274,	294	HWR17 = 274,
295	HWR18 = 275,	295	HWR18 = 275,
296	HWR19 = 276,	296	HWR19 = 276,
297	HWR20 = 277,	297	HWR20 = 277,
298	HWR21 = 278,	298	HWR21 = 278,
299	HWR22 = 279,	299	HWR22 = 279,
300	HWR23 = 280,	300	HWR23 = 280,
301	HWR24 = 281,	301	HWR24 = 281,
302	HWR25 = 282,	302	HWR25 = 282,
303	HWR26 = 283,	303	HWR26 = 283,
304	HWR27 = 284,	304	HWR27 = 284,
305	HWR28 = 285,	305	HWR28 = 285,
306	HWR29 = 286,	306	HWR29 = 286,
307	HWR30 = 287,	307	HWR30 = 287,
308	HWR31 = 288,	308	HWR31 = 288,
309	K0 = 289,	309	K0 = 289,
310	K1 = 290,	310	K1 = 290,
311	LO0 = 291,	311	LO0 = 291,
312	LO1 = 292,	312	LO1 = 292,
313	LO2 = 293,	313	LO2 = 293,
314	LO3 = 294,	314	LO3 = 294,
315	MPL0 = 295,	315	MPL0 = 295,
316	MPL1 = 296,	316	MPL1 = 296,
317	MPL2 = 297,	317	MPL2 = 297,
318	MSA8 = 298,	318	MSA8 = 298,
319	MSA9 = 299,	319	MSA9 = 299,
320	MSA10 = 300,	320	MSA10 = 300,
321	MSA11 = 301,	321	MSA11 = 301,
322	MSA12 = 302,	322	MSA12 = 302,
323	MSA13 = 303,	323	MSA13 = 303,
324	MSA14 = 304,	324	MSA14 = 304,
325	MSA15 = 305,	325	MSA15 = 305,
326	MSA16 = 306,	326	MSA16 = 306,
327	MSA17 = 307,	327	MSA17 = 307,
328	MSA18 = 308,	328	MSA18 = 308,
329	MSA19 = 309,	329	MSA19 = 309,
330	MSA20 = 310,	330	MSA20 = 310,
331	MSA21 = 311,	331	MSA21 = 311,
332	MSA22 = 312,	332	MSA22 = 312,
333	MSA23 = 313,	333	MSA23 = 313,
334	MSA24 = 314,	334	MSA24 = 314,
335	MSA25 = 315,	335	MSA25 = 315,
336	MSA26 = 316,	336	MSA26 = 316,
337	MSA27 = 317,	337	MSA27 = 317,
338	MSA28 = 318,	338	MSA28 = 318,
339	MSA29 = 319,	339	MSA29 = 319,
340	MSA30 = 320,	340	MSA30 = 320,
341	MSA31 = 321,	341	MSA31 = 321,
342	P0 = 322,	342	P0 = 322,
343	P1 = 323,	343	P1 = 323,
344	P2 = 324,	344	P2 = 324,
345	RA_64 = 325,	345	RA_64 = 325,
346	S0 = 326,	346	S0 = 326,
347	S1 = 327,	347	S1 = 327,
348	S2 = 328,	348	S2 = 328,
349	S3 = 329,	349	S3 = 329,
350	S4 = 330,	350	S4 = 330,
351	S5 = 331,	351	S5 = 331,
352	S6 = 332,	352	S6 = 332,
353	S7 = 333,	353	S7 = 333,
354	SP_64 = 334,	354	SP_64 = 334,
355	T0 = 335,	355	T0 = 335,
356	T1 = 336,	356	T1 = 336,
357	T2 = 337,	357	T2 = 337,
358	T3 = 338,	358	T3 = 338,
359	T4 = 339,	359	T4 = 339,
360	T5 = 340,	360	T5 = 340,
361	T6 = 341,	361	T6 = 341,
362	T7 = 342,	362	T7 = 342,
363	T8 = 343,	363	T8 = 343,
364	T9 = 344,	364	T9 = 344,
365	V0 = 345,	365	V0 = 345,
366	V1 = 346,	366	V1 = 346,
367	W0 = 347,	367	W0 = 347,
368	W1 = 348,	368	W1 = 348,
369	W2 = 349,	369	W2 = 349,
370	W3 = 350,	370	W3 = 350,
371	W4 = 351,	371	W4 = 351,
372	W5 = 352,	372	W5 = 352,
373	W6 = 353,	373	W6 = 353,
374	W7 = 354,	374	W7 = 354,
375	W8 = 355,	375	W8 = 355,
376	W9 = 356,	376	W9 = 356,
377	W10 = 357,	377	W10 = 357,
378	W11 = 358,	378	W11 = 358,
379	W12 = 359,	379	W12 = 359,
380	W13 = 360,	380	W13 = 360,
381	W14 = 361,	381	W14 = 361,
382	W15 = 362,	382	W15 = 362,
383	W16 = 363,	383	W16 = 363,
384	W17 = 364,	384	W17 = 364,
385	W18 = 365,	385	W18 = 365,
386	W19 = 366,	386	W19 = 366,
387	W20 = 367,	387	W20 = 367,
388	W21 = 368,	388	W21 = 368,
389	W22 = 369,	389	W22 = 369,
390	W23 = 370,	390	W23 = 370,
391	W24 = 371,	391	W24 = 371,
392	W25 = 372,	392	W25 = 372,
393	W26 = 373,	393	W26 = 373,
394	W27 = 374,	394	W27 = 374,
395	W28 = 375,	395	W28 = 375,
396	W29 = 376,	396	W29 = 376,
397	W30 = 377,	397	W30 = 377,
398	W31 = 378,	398	W31 = 378,
399	ZERO_64 = 379,	399	ZERO_64 = 379,
400	A0_64 = 380,	400	A0_64 = 380,
401	A1_64 = 381,	401	A1_64 = 381,
402	A2_64 = 382,	402	A2_64 = 382,
403	A3_64 = 383,	403	A3_64 = 383,
404	AC0_64 = 384,	404	AC0_64 = 384,
405	D0_64 = 385,	405	D0_64 = 385,
406	D1_64 = 386,	406	D1_64 = 386,
407	D2_64 = 387,	407	D2_64 = 387,
408	D3_64 = 388,	408	D3_64 = 388,
409	D4_64 = 389,	409	D4_64 = 389,
410	D5_64 = 390,	410	D5_64 = 390,
411	D6_64 = 391,	411	D6_64 = 391,
412	D7_64 = 392,	412	D7_64 = 392,
413	D8_64 = 393,	413	D8_64 = 393,
414	D9_64 = 394,	414	D9_64 = 394,
415	D10_64 = 395,	415	D10_64 = 395,
416	D11_64 = 396,	416	D11_64 = 396,
417	D12_64 = 397,	417	D12_64 = 397,
418	D13_64 = 398,	418	D13_64 = 398,
419	D14_64 = 399,	419	D14_64 = 399,
420	D15_64 = 400,	420	D15_64 = 400,
421	D16_64 = 401,	421	D16_64 = 401,
422	D17_64 = 402,	422	D17_64 = 402,
423	D18_64 = 403,	423	D18_64 = 403,
424	D19_64 = 404,	424	D19_64 = 404,
425	D20_64 = 405,	425	D20_64 = 405,
426	D21_64 = 406,	426	D21_64 = 406,
427	D22_64 = 407,	427	D22_64 = 407,
428	D23_64 = 408,	428	D23_64 = 408,
429	D24_64 = 409,	429	D24_64 = 409,
430	D25_64 = 410,	430	D25_64 = 410,
431	D26_64 = 411,	431	D26_64 = 411,
432	D27_64 = 412,	432	D27_64 = 412,
433	D28_64 = 413,	433	D28_64 = 413,
434	D29_64 = 414,	434	D29_64 = 414,
435	D30_64 = 415,	435	D30_64 = 415,
436	D31_64 = 416,	436	D31_64 = 416,
437	DSPOutFlag16_19 = 417,	437	DSPOutFlag16_19 = 417,
438	HI0_64 = 418,	438	HI0_64 = 418,
439	K0_64 = 419,	439	K0_64 = 419,
440	K1_64 = 420,	440	K1_64 = 420,
441	LO0_64 = 421,	441	LO0_64 = 421,
442	S0_64 = 422,	442	S0_64 = 422,
443	S1_64 = 423,	443	S1_64 = 423,
444	S2_64 = 424,	444	S2_64 = 424,
445	S3_64 = 425,	445	S3_64 = 425,
446	S4_64 = 426,	446	S4_64 = 426,
447	S5_64 = 427,	447	S5_64 = 427,
448	S6_64 = 428,	448	S6_64 = 428,
449	S7_64 = 429,	449	S7_64 = 429,
450	T0_64 = 430,	450	T0_64 = 430,
451	T1_64 = 431,	451	T1_64 = 431,
452	T2_64 = 432,	452	T2_64 = 432,
453	T3_64 = 433,	453	T3_64 = 433,
454	T4_64 = 434,	454	T4_64 = 434,
455	T5_64 = 435,	455	T5_64 = 435,
456	T6_64 = 436,	456	T6_64 = 436,
457	T7_64 = 437,	457	T7_64 = 437,
458	T8_64 = 438,	458	T8_64 = 438,
459	T9_64 = 439,	459	T9_64 = 439,
460	V0_64 = 440,	460	V0_64 = 440,
461	V1_64 = 441,	461	V1_64 = 441,
462	NUM_TARGET_REGS // 442	462	NUM_TARGET_REGS // 442
463	};	463	};
464	} // end namespace Mips	464	} // end namespace Mips
465		465
466	// Register classes	466	// Register classes
467		467
468	namespace Mips {	468	namespace Mips {
469	enum {	469	enum {
470	MSA128F16RegClassID = 0,	470	MSA128F16RegClassID = 0,
471	CCRRegClassID = 1,	471	CCRRegClassID = 1,
472	COP0RegClassID = 2,	472	COP0RegClassID = 2,
473	COP2RegClassID = 3,	473	COP2RegClassID = 3,
474	COP3RegClassID = 4,	474	COP3RegClassID = 4,
475	DSPRRegClassID = 5,	475	DSPRRegClassID = 5,
476	FGR32RegClassID = 6,	476	FGR32RegClassID = 6,
477	FGRCCRegClassID = 7,	477	FGRCCRegClassID = 7,
478	GPR32RegClassID = 8,	478	GPR32RegClassID = 8,
479	HWRegsRegClassID = 9,	479	HWRegsRegClassID = 9,
480	MSACtrlRegClassID = 10,	480	MSACtrlRegClassID = 10,
481	GPR32NONZERORegClassID = 11,	481	GPR32NONZERORegClassID = 11,
482	CPU16RegsPlusSPRegClassID = 12,	482	CPU16RegsPlusSPRegClassID = 12,
483	CPU16RegsRegClassID = 13,	483	CPU16RegsRegClassID = 13,
484	FCCRegClassID = 14,	484	FCCRegClassID = 14,
485	GPRMM16RegClassID = 15,	485	GPRMM16RegClassID = 15,
486	GPRMM16MovePRegClassID = 16,	486	GPRMM16MovePRegClassID = 16,
487	GPRMM16ZeroRegClassID = 17,	487	GPRMM16ZeroRegClassID = 17,
488	CPU16Regs_and_GPRMM16ZeroRegClassID = 18,	488	CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
489	GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,	489	GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
490	GPRMM16MovePPairSecondRegClassID = 20,	490	GPRMM16MovePPairSecondRegClassID = 20,
491	CPU16Regs_and_GPRMM16MovePRegClassID = 21,	491	CPU16Regs_and_GPRMM16MovePRegClassID = 21,
492	GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,	492	GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
493	HI32DSPRegClassID = 23,	493	HI32DSPRegClassID = 23,
494	LO32DSPRegClassID = 24,	494	LO32DSPRegClassID = 24,
495	CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,	495	CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
496	GPRMM16MovePPairFirstRegClassID = 26,	496	GPRMM16MovePPairFirstRegClassID = 26,
497	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,	497	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
498	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,	498	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
499	CPURARegRegClassID = 29,	499	CPURARegRegClassID = 29,
500	CPUSPRegRegClassID = 30,	500	CPUSPRegRegClassID = 30,
501	DSPCCRegClassID = 31,	501	DSPCCRegClassID = 31,
502	GP32RegClassID = 32,	502	GP32RegClassID = 32,
503	GPR32ZERORegClassID = 33,	503	GPR32ZERORegClassID = 33,
504	HI32RegClassID = 34,	504	HI32RegClassID = 34,
505	LO32RegClassID = 35,	505	LO32RegClassID = 35,
506	SP32RegClassID = 36,	506	SP32RegClassID = 36,
507	FGR64RegClassID = 37,	507	FGR64RegClassID = 37,
508	GPR64RegClassID = 38,	508	GPR64RegClassID = 38,
509	GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,	509	GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
510	AFGR64RegClassID = 40,	510	AFGR64RegClassID = 40,
511	GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,	511	GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
512	GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,	512	GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
513	GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,	513	GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
514	GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,	514	GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
515	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,	515	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
516	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,	516	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
517	GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,	517	GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
518	ACC64DSPRegClassID = 48,	518	ACC64DSPRegClassID = 48,
519	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,	519	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,	520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
521	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,	521	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
522	GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,	522	GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
523	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,	523	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
524	OCTEON_MPLRegClassID = 54,	524	OCTEON_MPLRegClassID = 54,
525	OCTEON_PRegClassID = 55,	525	OCTEON_PRegClassID = 55,
526	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,	526	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
527	ACC64RegClassID = 57,	527	ACC64RegClassID = 57,
528	GP64RegClassID = 58,	528	GP64RegClassID = 58,
529	GPR64_with_sub_32_in_CPURARegRegClassID = 59,	529	GPR64_with_sub_32_in_CPURARegRegClassID = 59,
530	GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,	530	GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
531	HI64RegClassID = 61,	531	HI64RegClassID = 61,
532	LO64RegClassID = 62,	532	LO64RegClassID = 62,
533	SP64RegClassID = 63,	533	SP64RegClassID = 63,
534	MSA128BRegClassID = 64,	534	MSA128BRegClassID = 64,
535	MSA128DRegClassID = 65,	535	MSA128DRegClassID = 65,
536	MSA128HRegClassID = 66,	536	MSA128HRegClassID = 66,
537	MSA128WRegClassID = 67,	537	MSA128WRegClassID = 67,
538	MSA128WEvensRegClassID = 68,	538	MSA128WEvensRegClassID = 68,
539	ACC128RegClassID = 69,	539	ACC128RegClassID = 69,
540		540
541	};	541	};
542	} // end namespace Mips	542	} // end namespace Mips
543		543
544		544
545	// Subregister indices	545	// Subregister indices
546		546
547	namespace Mips {	547	namespace Mips {
548	enum : uint16_t {	548	enum : uint16_t {
549	NoSubRegister,	549	NoSubRegister,
550	sub_32, // 1	550	sub_32, // 1
551	sub_64, // 2	551	sub_64, // 2
552	sub_dsp16_19, // 3	552	sub_dsp16_19, // 3
553	sub_dsp20, // 4	553	sub_dsp20, // 4
554	sub_dsp21, // 5	554	sub_dsp21, // 5
555	sub_dsp22, // 6	555	sub_dsp22, // 6
556	sub_dsp23, // 7	556	sub_dsp23, // 7
557	sub_hi, // 8	557	sub_hi, // 8
558	sub_lo, // 9	558	sub_lo, // 9
559	sub_hi_then_sub_32, // 10	559	sub_hi_then_sub_32, // 10
560	sub_32_sub_hi_then_sub_32, // 11	560	sub_32_sub_hi_then_sub_32, // 11
561	NUM_TARGET_SUBREGS	561	NUM_TARGET_SUBREGS
562	};	562	};
563	} // end namespace Mips	563	} // end namespace Mips
564		564
565	// Register pressure sets enum.	565	// Register pressure sets enum.
566	namespace Mips {	566	namespace Mips {
567	enum RegisterPressureSets {	567	enum RegisterPressureSets {
568	DSPCC = 0,	568	DSPCC = 0,
569	GPR32ZERO = 1,	569	GPR32ZERO = 1,
570	GPR64_with_sub_32_in_CPURAReg = 2,	570	GPR64_with_sub_32_in_CPURAReg = 2,
571	HI32 = 3,	571	HI32 = 3,
572	GPRMM16MovePPairFirst = 4,	572	GPRMM16MovePPairFirst = 4,
573	CPU16Regs_and_GPRMM16MoveP = 5,	573	CPU16Regs_and_GPRMM16MoveP = 5,
574	HI32DSP = 6,	574	HI32DSP = 6,
575	LO32DSP = 7,	575	LO32DSP = 7,
576	GPRMM16MovePPairSecond = 8,	576	GPRMM16MovePPairSecond = 8,
577	GPRMM16MoveP = 9,	577	GPRMM16MoveP = 9,
578	ACC64DSP = 10,	578	ACC64DSP = 10,
579	CPU16Regs = 11,	579	CPU16Regs = 11,
580	GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,	580	GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,
581	CPU16Regs_with_GPRMM16MovePPairSecond = 13,	581	CPU16Regs_with_GPRMM16MovePPairSecond = 13,
582	CPU16Regs_with_GPRMM16MoveP = 14,	582	CPU16Regs_with_GPRMM16MoveP = 14,
583	DSPR = 15,	583	DSPR = 15,
584	FGR32 = 16,	584	FGR32 = 16,
585	MSA128WEvens = 17,	585	MSA128WEvens = 17,
586	FGR32_with_MSA128WEvens = 18,	586	FGR32_with_MSA128WEvens = 18,
587	MSA128F16 = 19,	587	MSA128F16 = 19,
588	};	588	};
589	} // end namespace Mips	589	} // end namespace Mips
590		590
591	} // end namespace llvm	591	} // end namespace llvm
592		592
593	#endif // GET_REGINFO_ENUM	593	#endif // GET_REGINFO_ENUM
594		594
595	/===- TableGen'erated file -------------------------------------- C++ --===\	595	/===- TableGen'erated file -------------------------------------- C++ --===\
596	\|* *\|	596	\|* *\|
597	\|* MC Register Information *\|	597	\|* MC Register Information *\|
598	\|* *\|	598	\|* *\|
599	\|* Automatically generated file, do not edit! *\|	599	\|* Automatically generated file, do not edit! *\|
600	\|* *\|	600	\|* *\|
601	\===----------------------------------------------------------------------===/	601	\===----------------------------------------------------------------------===/
602		602
603		603
604	#ifdef GET_REGINFO_MC_DESC	604	#ifdef GET_REGINFO_MC_DESC
605	#undef GET_REGINFO_MC_DESC	605	#undef GET_REGINFO_MC_DESC
606		606
607	namespace llvm {	607	namespace llvm {
608		608
609	extern const int16_t MipsRegDiffLists[] = {	609	extern const int16_t MipsRegDiffLists[] = {
610	/* 0 */ -412, 0,	610	/* 0 */ -412, 0,
611	/* 2 */ -358, 0,	611	/* 2 */ -358, 0,
612	/* 4 */ -314, 0,	612	/* 4 */ -314, 0,
613	/* 6 */ -306, 0,	613	/* 6 */ -306, 0,
614	/* 8 */ -265, 0,	614	/* 8 */ -265, 0,
615	/* 10 */ -243, 0,	615	/* 10 */ -243, 0,
616	/* 12 */ 37, -130, 127, -165, -227, 0,	616	/* 12 */ 37, -130, 127, -165, -227, 0,
617	/* 18 */ -211, 0,	617	/* 18 */ -211, 0,
618	/* 20 */ -165, 0,	618	/* 20 */ -165, 0,
619	/* 22 */ -141, 0,	619	/* 22 */ -141, 0,
620	/* 24 */ -140, 0,	620	/* 24 */ -140, 0,
621	/* 26 */ -139, 0,	621	/* 26 */ -139, 0,
622	/* 28 */ -138, 0,	622	/* 28 */ -138, 0,
623	/* 30 */ -130, 0,	623	/* 30 */ -130, 0,
624	/* 32 */ -96, 0,	624	/* 32 */ -96, 0,
625	/* 34 */ -95, 0,	625	/* 34 */ -95, 0,
626	/* 36 */ 165, -38, 0,	626	/* 36 */ 165, -38, 0,
627	/* 39 */ -20, 258, -38, 0,	627	/* 39 */ -20, 258, -38, 0,
628	/* 43 */ -21, 259, -38, 0,	628	/* 43 */ -21, 259, -38, 0,
629	/* 47 */ -22, 260, -38, 0,	629	/* 47 */ -22, 260, -38, 0,
630	/* 51 */ -23, 261, -38, 0,	630	/* 51 */ -23, 261, -38, 0,
631	/* 55 */ -24, 262, -38, 0,	631	/* 55 */ -24, 262, -38, 0,
632	/* 59 */ -25, 263, -38, 0,	632	/* 59 */ -25, 263, -38, 0,
633	/* 63 */ -26, 264, -38, 0,	633	/* 63 */ -26, 264, -38, 0,
634	/* 67 */ -27, 265, -38, 0,	634	/* 67 */ -27, 265, -38, 0,
635	/* 71 */ -28, 266, -38, 0,	635	/* 71 */ -28, 266, -38, 0,
636	/* 75 */ -29, 267, -38, 0,	636	/* 75 */ -29, 267, -38, 0,
637	/* 79 */ -30, 268, -38, 0,	637	/* 79 */ -30, 268, -38, 0,
638	/* 83 */ -31, 269, -38, 0,	638	/* 83 */ -31, 269, -38, 0,
639	/* 87 */ -32, 270, -38, 0,	639	/* 87 */ -32, 270, -38, 0,
640	/* 91 */ -33, 271, -38, 0,	640	/* 91 */ -33, 271, -38, 0,
641	/* 95 */ -34, 272, -38, 0,	641	/* 95 */ -34, 272, -38, 0,
642	/* 99 */ -35, 273, -38, 0,	642	/* 99 */ -35, 273, -38, 0,
643	/* 103 */ -36, 274, -38, 0,	643	/* 103 */ -36, 274, -38, 0,
644	/* 107 */ -265, 395, -37, 0,	644	/* 107 */ -265, 395, -37, 0,
645	/* 111 */ -227, 392, -34, 0,	645	/* 111 */ -227, 392, -34, 0,
646	/* 115 */ -29, 0,	646	/* 115 */ -29, 0,
647	/* 117 */ 412, -274, 1, 1, 1, 0,	647	/* 117 */ 412, -274, 1, 1, 1, 0,
648	/* 123 */ 1, 1, 1, 1, 0,	648	/* 123 */ 1, 1, 1, 1, 0,
649	/* 128 */ 20, 1, 0,	649	/* 128 */ 20, 1, 0,
650	/* 131 */ 21, 1, 0,	650	/* 131 */ 21, 1, 0,
651	/* 134 */ 22, 1, 0,	651	/* 134 */ 22, 1, 0,
652	/* 137 */ 23, 1, 0,	652	/* 137 */ 23, 1, 0,
653	/* 140 */ 24, 1, 0,	653	/* 140 */ 24, 1, 0,
654	/* 143 */ 25, 1, 0,	654	/* 143 */ 25, 1, 0,
655	/* 146 */ 26, 1, 0,	655	/* 146 */ 26, 1, 0,
656	/* 149 */ 27, 1, 0,	656	/* 149 */ 27, 1, 0,
657	/* 152 */ 28, 1, 0,	657	/* 152 */ 28, 1, 0,
658	/* 155 */ 29, 1, 0,	658	/* 155 */ 29, 1, 0,
659	/* 158 */ 30, 1, 0,	659	/* 158 */ 30, 1, 0,
660	/* 161 */ 31, 1, 0,	660	/* 161 */ 31, 1, 0,
661	/* 164 */ 32, 1, 0,	661	/* 164 */ 32, 1, 0,
662	/* 167 */ 33, 1, 0,	662	/* 167 */ 33, 1, 0,
663	/* 170 */ 34, 1, 0,	663	/* 170 */ 34, 1, 0,
664	/* 173 */ 35, 1, 0,	664	/* 173 */ 35, 1, 0,
665	/* 176 */ 29, 0,	665	/* 176 */ 29, 0,
666	/* 178 */ 72, 0,	666	/* 178 */ 72, 0,
667	/* 180 */ 38, -238, 73, 0,	667	/* 180 */ 38, -238, 73, 0,
668	/* 184 */ 95, 0,	668	/* 184 */ 95, 0,
669	/* 186 */ 96, 0,	669	/* 186 */ 96, 0,
670	/* 188 */ 130, 0,	670	/* 188 */ 130, 0,
671	/* 190 */ 211, 0,	671	/* 190 */ 211, 0,
672	/* 192 */ 243, 0,	672	/* 192 */ 243, 0,
673	/* 194 */ 306, 0,	673	/* 194 */ 306, 0,
674	/* 196 */ 314, 0,	674	/* 196 */ 314, 0,
675	/* 198 */ 358, 0,	675	/* 198 */ 358, 0,
676	};	676	};
677		677
678	extern const LaneBitmask MipsLaneMaskLists[] = {	678	extern const LaneBitmask MipsLaneMaskLists[] = {
679	/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),	679	/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
680	/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),	680	/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
681	/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),	681	/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
682	/* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),	682	/* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
683	};	683	};
684		684
685	extern const uint16_t MipsSubRegIdxLists[] = {	685	extern const uint16_t MipsSubRegIdxLists[] = {
686	/* 0 */ 1, 0,	686	/* 0 */ 1, 0,
687	/* 2 */ 3, 4, 5, 6, 7, 0,	687	/* 2 */ 3, 4, 5, 6, 7, 0,
688	/* 8 */ 2, 9, 8, 0,	688	/* 8 */ 2, 9, 8, 0,
689	/* 12 */ 9, 1, 8, 10, 11, 0,	689	/* 12 */ 9, 1, 8, 10, 11, 0,
690	};	690	};
691		691
692	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {	692	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
693	{ 65535, 65535 },	693	{ 65535, 65535 },
694	{ 0, 32 }, // sub_32	694	{ 0, 32 }, // sub_32
695	{ 0, 64 }, // sub_64	695	{ 0, 64 }, // sub_64
696	{ 16, 4 }, // sub_dsp16_19	696	{ 16, 4 }, // sub_dsp16_19
697	{ 20, 1 }, // sub_dsp20	697	{ 20, 1 }, // sub_dsp20
698	{ 21, 1 }, // sub_dsp21	698	{ 21, 1 }, // sub_dsp21
699	{ 22, 1 }, // sub_dsp22	699	{ 22, 1 }, // sub_dsp22
700	{ 23, 1 }, // sub_dsp23	700	{ 23, 1 }, // sub_dsp23
701	{ 32, 32 }, // sub_hi	701	{ 32, 32 }, // sub_hi
702	{ 0, 32 }, // sub_lo	702	{ 0, 32 }, // sub_lo
703	{ 32, 32 }, // sub_hi_then_sub_32	703	{ 32, 32 }, // sub_hi_then_sub_32
704	{ 0, 64 }, // sub_32_sub_hi_then_sub_32	704	{ 0, 64 }, // sub_32_sub_hi_then_sub_32
705	};	705	};
706		706
707		707
708	#ifdef __GNUC__	708	#ifdef __GNUC__
709	#pragma GCC diagnostic push	709	#pragma GCC diagnostic push
710	#pragma GCC diagnostic ignored "-Woverlength-strings"	710	#pragma GCC diagnostic ignored "-Woverlength-strings"
711	#endif	711	#endif
712	extern const char MipsRegStrings[] = {	712	extern const char MipsRegStrings[] = {
713	/* 0 */ "COP00\0"	713	/* 0 */ "COP00\0"
714	/* 6 */ "COP010\0"	714	/* 6 */ "COP010\0"
715	/* 13 */ "COP210\0"	715	/* 13 */ "COP210\0"
716	/* 20 */ "COP310\0"	716	/* 20 */ "COP310\0"
717	/* 27 */ "MSA10\0"	717	/* 27 */ "MSA10\0"
718	/* 33 */ "D10\0"	718	/* 33 */ "D10\0"
719	/* 37 */ "F10\0"	719	/* 37 */ "F10\0"
720	/* 41 */ "F_HI10\0"	720	/* 41 */ "F_HI10\0"
721	/* 48 */ "FCR10\0"	721	/* 48 */ "FCR10\0"
722	/* 54 */ "HWR10\0"	722	/* 54 */ "HWR10\0"
723	/* 60 */ "W10\0"	723	/* 60 */ "W10\0"
724	/* 64 */ "COP020\0"	724	/* 64 */ "COP020\0"
725	/* 71 */ "COP220\0"	725	/* 71 */ "COP220\0"
726	/* 78 */ "COP320\0"	726	/* 78 */ "COP320\0"
727	/* 85 */ "MSA20\0"	727	/* 85 */ "MSA20\0"
728	/* 91 */ "F20\0"	728	/* 91 */ "F20\0"
729	/* 95 */ "F_HI20\0"	729	/* 95 */ "F_HI20\0"
730	/* 102 */ "COP20\0"	730	/* 102 */ "COP20\0"
731	/* 108 */ "FCR20\0"	731	/* 108 */ "FCR20\0"
732	/* 114 */ "HWR20\0"	732	/* 114 */ "HWR20\0"
733	/* 120 */ "W20\0"	733	/* 120 */ "W20\0"
734	/* 124 */ "DSPOutFlag20\0"	734	/* 124 */ "DSPOutFlag20\0"
735	/* 137 */ "COP030\0"	735	/* 137 */ "COP030\0"
736	/* 144 */ "COP230\0"	736	/* 144 */ "COP230\0"
737	/* 151 */ "COP330\0"	737	/* 151 */ "COP330\0"
738	/* 158 */ "MSA30\0"	738	/* 158 */ "MSA30\0"
739	/* 164 */ "F30\0"	739	/* 164 */ "F30\0"
740	/* 168 */ "F_HI30\0"	740	/* 168 */ "F_HI30\0"
741	/* 175 */ "COP30\0"	741	/* 175 */ "COP30\0"
742	/* 181 */ "FCR30\0"	742	/* 181 */ "FCR30\0"
743	/* 187 */ "HWR30\0"	743	/* 187 */ "HWR30\0"
744	/* 193 */ "W30\0"	744	/* 193 */ "W30\0"
745	/* 197 */ "A0\0"	745	/* 197 */ "A0\0"
746	/* 200 */ "AC0\0"	746	/* 200 */ "AC0\0"
747	/* 204 */ "FCC0\0"	747	/* 204 */ "FCC0\0"
748	/* 209 */ "D0\0"	748	/* 209 */ "D0\0"
749	/* 212 */ "F0\0"	749	/* 212 */ "F0\0"
750	/* 215 */ "F_HI0\0"	750	/* 215 */ "F_HI0\0"
751	/* 221 */ "K0\0"	751	/* 221 */ "K0\0"
752	/* 224 */ "MPL0\0"	752	/* 224 */ "MPL0\0"
753	/* 229 */ "LO0\0"	753	/* 229 */ "LO0\0"
754	/* 233 */ "P0\0"	754	/* 233 */ "P0\0"
755	/* 236 */ "FCR0\0"	755	/* 236 */ "FCR0\0"
756	/* 241 */ "HWR0\0"	756	/* 241 */ "HWR0\0"
757	/* 246 */ "S0\0"	757	/* 246 */ "S0\0"
758	/* 249 */ "T0\0"	758	/* 249 */ "T0\0"
759	/* 252 */ "V0\0"	759	/* 252 */ "V0\0"
760	/* 255 */ "W0\0"	760	/* 255 */ "W0\0"
761	/* 258 */ "COP01\0"	761	/* 258 */ "COP01\0"
762	/* 264 */ "COP011\0"	762	/* 264 */ "COP011\0"
763	/* 271 */ "COP211\0"	763	/* 271 */ "COP211\0"
764	/* 278 */ "COP311\0"	764	/* 278 */ "COP311\0"
765	/* 285 */ "MSA11\0"	765	/* 285 */ "MSA11\0"
766	/* 291 */ "D11\0"	766	/* 291 */ "D11\0"
767	/* 295 */ "F11\0"	767	/* 295 */ "F11\0"
768	/* 299 */ "F_HI11\0"	768	/* 299 */ "F_HI11\0"
769	/* 306 */ "FCR11\0"	769	/* 306 */ "FCR11\0"
770	/* 312 */ "HWR11\0"	770	/* 312 */ "HWR11\0"
771	/* 318 */ "W11\0"	771	/* 318 */ "W11\0"
772	/* 322 */ "COP021\0"	772	/* 322 */ "COP021\0"
773	/* 329 */ "COP221\0"	773	/* 329 */ "COP221\0"
774	/* 336 */ "COP321\0"	774	/* 336 */ "COP321\0"
775	/* 343 */ "MSA21\0"	775	/* 343 */ "MSA21\0"
776	/* 349 */ "F21\0"	776	/* 349 */ "F21\0"
777	/* 353 */ "F_HI21\0"	777	/* 353 */ "F_HI21\0"
778	/* 360 */ "COP21\0"	778	/* 360 */ "COP21\0"
779	/* 366 */ "FCR21\0"	779	/* 366 */ "FCR21\0"
780	/* 372 */ "HWR21\0"	780	/* 372 */ "HWR21\0"
781	/* 378 */ "W21\0"	781	/* 378 */ "W21\0"
782	/* 382 */ "DSPOutFlag21\0"	782	/* 382 */ "DSPOutFlag21\0"
783	/* 395 */ "COP031\0"	783	/* 395 */ "COP031\0"
784	/* 402 */ "COP231\0"	784	/* 402 */ "COP231\0"
785	/* 409 */ "COP331\0"	785	/* 409 */ "COP331\0"
786	/* 416 */ "MSA31\0"	786	/* 416 */ "MSA31\0"
787	/* 422 */ "F31\0"	787	/* 422 */ "F31\0"
788	/* 426 */ "F_HI31\0"	788	/* 426 */ "F_HI31\0"
789	/* 433 */ "COP31\0"	789	/* 433 */ "COP31\0"
790	/* 439 */ "FCR31\0"	790	/* 439 */ "FCR31\0"
791	/* 445 */ "HWR31\0"	791	/* 445 */ "HWR31\0"
792	/* 451 */ "W31\0"	792	/* 451 */ "W31\0"
793	/* 455 */ "A1\0"	793	/* 455 */ "A1\0"
794	/* 458 */ "AC1\0"	794	/* 458 */ "AC1\0"
795	/* 462 */ "FCC1\0"	795	/* 462 */ "FCC1\0"
796	/* 467 */ "D1\0"	796	/* 467 */ "D1\0"
797	/* 470 */ "F1\0"	797	/* 470 */ "F1\0"
798	/* 473 */ "F_HI1\0"	798	/* 473 */ "F_HI1\0"
799	/* 479 */ "K1\0"	799	/* 479 */ "K1\0"
800	/* 482 */ "MPL1\0"	800	/* 482 */ "MPL1\0"
801	/* 487 */ "LO1\0"	801	/* 487 */ "LO1\0"
802	/* 491 */ "P1\0"	802	/* 491 */ "P1\0"
803	/* 494 */ "FCR1\0"	803	/* 494 */ "FCR1\0"
804	/* 499 */ "HWR1\0"	804	/* 499 */ "HWR1\0"
805	/* 504 */ "S1\0"	805	/* 504 */ "S1\0"
806	/* 507 */ "T1\0"	806	/* 507 */ "T1\0"
807	/* 510 */ "V1\0"	807	/* 510 */ "V1\0"
808	/* 513 */ "W1\0"	808	/* 513 */ "W1\0"
809	/* 516 */ "COP02\0"	809	/* 516 */ "COP02\0"
810	/* 522 */ "COP012\0"	810	/* 522 */ "COP012\0"
811	/* 529 */ "COP212\0"	811	/* 529 */ "COP212\0"
812	/* 536 */ "COP312\0"	812	/* 536 */ "COP312\0"
813	/* 543 */ "MSA12\0"	813	/* 543 */ "MSA12\0"
814	/* 549 */ "D12\0"	814	/* 549 */ "D12\0"
815	/* 553 */ "F12\0"	815	/* 553 */ "F12\0"
816	/* 557 */ "F_HI12\0"	816	/* 557 */ "F_HI12\0"
817	/* 564 */ "FCR12\0"	817	/* 564 */ "FCR12\0"
818	/* 570 */ "HWR12\0"	818	/* 570 */ "HWR12\0"
819	/* 576 */ "W12\0"	819	/* 576 */ "W12\0"
820	/* 580 */ "COP022\0"	820	/* 580 */ "COP022\0"
821	/* 587 */ "COP222\0"	821	/* 587 */ "COP222\0"
822	/* 594 */ "COP322\0"	822	/* 594 */ "COP322\0"
823	/* 601 */ "MSA22\0"	823	/* 601 */ "MSA22\0"
824	/* 607 */ "F22\0"	824	/* 607 */ "F22\0"
825	/* 611 */ "F_HI22\0"	825	/* 611 */ "F_HI22\0"
826	/* 618 */ "COP22\0"	826	/* 618 */ "COP22\0"
827	/* 624 */ "FCR22\0"	827	/* 624 */ "FCR22\0"
828	/* 630 */ "HWR22\0"	828	/* 630 */ "HWR22\0"
829	/* 636 */ "W22\0"	829	/* 636 */ "W22\0"
830	/* 640 */ "DSPOutFlag22\0"	830	/* 640 */ "DSPOutFlag22\0"
831	/* 653 */ "COP32\0"	831	/* 653 */ "COP32\0"
832	/* 659 */ "A2\0"	832	/* 659 */ "A2\0"
833	/* 662 */ "AC2\0"	833	/* 662 */ "AC2\0"
834	/* 666 */ "FCC2\0"	834	/* 666 */ "FCC2\0"
835	/* 671 */ "D2\0"	835	/* 671 */ "D2\0"
836	/* 674 */ "F2\0"	836	/* 674 */ "F2\0"
837	/* 677 */ "F_HI2\0"	837	/* 677 */ "F_HI2\0"
838	/* 683 */ "MPL2\0"	838	/* 683 */ "MPL2\0"
839	/* 688 */ "LO2\0"	839	/* 688 */ "LO2\0"
840	/* 692 */ "P2\0"	840	/* 692 */ "P2\0"
841	/* 695 */ "FCR2\0"	841	/* 695 */ "FCR2\0"
842	/* 700 */ "HWR2\0"	842	/* 700 */ "HWR2\0"
843	/* 705 */ "S2\0"	843	/* 705 */ "S2\0"
844	/* 708 */ "T2\0"	844	/* 708 */ "T2\0"
845	/* 711 */ "W2\0"	845	/* 711 */ "W2\0"
846	/* 714 */ "COP03\0"	846	/* 714 */ "COP03\0"
847	/* 720 */ "COP013\0"	847	/* 720 */ "COP013\0"
848	/* 727 */ "COP213\0"	848	/* 727 */ "COP213\0"
849	/* 734 */ "COP313\0"	849	/* 734 */ "COP313\0"
850	/* 741 */ "MSA13\0"	850	/* 741 */ "MSA13\0"
851	/* 747 */ "D13\0"	851	/* 747 */ "D13\0"
852	/* 751 */ "F13\0"	852	/* 751 */ "F13\0"
853	/* 755 */ "F_HI13\0"	853	/* 755 */ "F_HI13\0"
854	/* 762 */ "FCR13\0"	854	/* 762 */ "FCR13\0"
855	/* 768 */ "HWR13\0"	855	/* 768 */ "HWR13\0"
856	/* 774 */ "W13\0"	856	/* 774 */ "W13\0"
857	/* 778 */ "COP023\0"	857	/* 778 */ "COP023\0"
858	/* 785 */ "COP223\0"	858	/* 785 */ "COP223\0"
859	/* 792 */ "COP323\0"	859	/* 792 */ "COP323\0"
860	/* 799 */ "MSA23\0"	860	/* 799 */ "MSA23\0"
861	/* 805 */ "F23\0"	861	/* 805 */ "F23\0"
862	/* 809 */ "F_HI23\0"	862	/* 809 */ "F_HI23\0"
863	/* 816 */ "COP23\0"	863	/* 816 */ "COP23\0"
864	/* 822 */ "FCR23\0"	864	/* 822 */ "FCR23\0"
865	/* 828 */ "HWR23\0"	865	/* 828 */ "HWR23\0"
866	/* 834 */ "W23\0"	866	/* 834 */ "W23\0"
867	/* 838 */ "DSPOutFlag23\0"	867	/* 838 */ "DSPOutFlag23\0"
868	/* 851 */ "COP33\0"	868	/* 851 */ "COP33\0"
869	/* 857 */ "A3\0"	869	/* 857 */ "A3\0"
870	/* 860 */ "AC3\0"	870	/* 860 */ "AC3\0"
871	/* 864 */ "FCC3\0"	871	/* 864 */ "FCC3\0"
872	/* 869 */ "D3\0"	872	/* 869 */ "D3\0"
873	/* 872 */ "F3\0"	873	/* 872 */ "F3\0"
874	/* 875 */ "F_HI3\0"	874	/* 875 */ "F_HI3\0"
875	/* 881 */ "LO3\0"	875	/* 881 */ "LO3\0"
876	/* 885 */ "FCR3\0"	876	/* 885 */ "FCR3\0"
877	/* 890 */ "HWR3\0"	877	/* 890 */ "HWR3\0"
878	/* 895 */ "S3\0"	878	/* 895 */ "S3\0"
879	/* 898 */ "T3\0"	879	/* 898 */ "T3\0"
880	/* 901 */ "W3\0"	880	/* 901 */ "W3\0"
881	/* 904 */ "COP04\0"	881	/* 904 */ "COP04\0"
882	/* 910 */ "COP014\0"	882	/* 910 */ "COP014\0"
883	/* 917 */ "COP214\0"	883	/* 917 */ "COP214\0"
884	/* 924 */ "COP314\0"	884	/* 924 */ "COP314\0"
885	/* 931 */ "MSA14\0"	885	/* 931 */ "MSA14\0"
886	/* 937 */ "D14\0"	886	/* 937 */ "D14\0"
887	/* 941 */ "F14\0"	887	/* 941 */ "F14\0"
888	/* 945 */ "F_HI14\0"	888	/* 945 */ "F_HI14\0"
889	/* 952 */ "FCR14\0"	889	/* 952 */ "FCR14\0"
890	/* 958 */ "HWR14\0"	890	/* 958 */ "HWR14\0"
891	/* 964 */ "W14\0"	891	/* 964 */ "W14\0"
892	/* 968 */ "COP024\0"	892	/* 968 */ "COP024\0"
893	/* 975 */ "COP224\0"	893	/* 975 */ "COP224\0"
894	/* 982 */ "COP324\0"	894	/* 982 */ "COP324\0"
895	/* 989 */ "MSA24\0"	895	/* 989 */ "MSA24\0"
896	/* 995 */ "F24\0"	896	/* 995 */ "F24\0"
897	/* 999 */ "F_HI24\0"	897	/* 999 */ "F_HI24\0"
898	/* 1006 */ "COP24\0"	898	/* 1006 */ "COP24\0"
899	/* 1012 */ "FCR24\0"	899	/* 1012 */ "FCR24\0"
900	/* 1018 */ "HWR24\0"	900	/* 1018 */ "HWR24\0"
901	/* 1024 */ "W24\0"	901	/* 1024 */ "W24\0"
902	/* 1028 */ "COP34\0"	902	/* 1028 */ "COP34\0"
903	/* 1034 */ "D10_64\0"	903	/* 1034 */ "D10_64\0"
904	/* 1041 */ "D20_64\0"	904	/* 1041 */ "D20_64\0"
905	/* 1048 */ "D30_64\0"	905	/* 1048 */ "D30_64\0"
906	/* 1055 */ "A0_64\0"	906	/* 1055 */ "A0_64\0"
907	/* 1061 */ "AC0_64\0"	907	/* 1061 */ "AC0_64\0"
908	/* 1068 */ "D0_64\0"	908	/* 1068 */ "D0_64\0"
909	/* 1074 */ "HI0_64\0"	909	/* 1074 */ "HI0_64\0"
910	/* 1081 */ "K0_64\0"	910	/* 1081 */ "K0_64\0"
911	/* 1087 */ "LO0_64\0"	911	/* 1087 */ "LO0_64\0"
912	/* 1094 */ "S0_64\0"	912	/* 1094 */ "S0_64\0"
913	/* 1100 */ "T0_64\0"	913	/* 1100 */ "T0_64\0"
914	/* 1106 */ "V0_64\0"	914	/* 1106 */ "V0_64\0"
915	/* 1112 */ "D11_64\0"	915	/* 1112 */ "D11_64\0"
916	/* 1119 */ "D21_64\0"	916	/* 1119 */ "D21_64\0"
917	/* 1126 */ "D31_64\0"	917	/* 1126 */ "D31_64\0"
918	/* 1133 */ "A1_64\0"	918	/* 1133 */ "A1_64\0"
919	/* 1139 */ "D1_64\0"	919	/* 1139 */ "D1_64\0"
920	/* 1145 */ "K1_64\0"	920	/* 1145 */ "K1_64\0"
921	/* 1151 */ "S1_64\0"	921	/* 1151 */ "S1_64\0"
922	/* 1157 */ "T1_64\0"	922	/* 1157 */ "T1_64\0"
923	/* 1163 */ "V1_64\0"	923	/* 1163 */ "V1_64\0"
924	/* 1169 */ "D12_64\0"	924	/* 1169 */ "D12_64\0"
925	/* 1176 */ "D22_64\0"	925	/* 1176 */ "D22_64\0"
926	/* 1183 */ "A2_64\0"	926	/* 1183 */ "A2_64\0"
927	/* 1189 */ "D2_64\0"	927	/* 1189 */ "D2_64\0"
928	/* 1195 */ "S2_64\0"	928	/* 1195 */ "S2_64\0"
929	/* 1201 */ "T2_64\0"	929	/* 1201 */ "T2_64\0"
930	/* 1207 */ "D13_64\0"	930	/* 1207 */ "D13_64\0"
931	/* 1214 */ "D23_64\0"	931	/* 1214 */ "D23_64\0"
932	/* 1221 */ "A3_64\0"	932	/* 1221 */ "A3_64\0"
933	/* 1227 */ "D3_64\0"	933	/* 1227 */ "D3_64\0"
934	/* 1233 */ "S3_64\0"	934	/* 1233 */ "S3_64\0"
935	/* 1239 */ "T3_64\0"	935	/* 1239 */ "T3_64\0"
936	/* 1245 */ "D14_64\0"	936	/* 1245 */ "D14_64\0"
937	/* 1252 */ "D24_64\0"	937	/* 1252 */ "D24_64\0"
938	/* 1259 */ "D4_64\0"	938	/* 1259 */ "D4_64\0"
939	/* 1265 */ "S4_64\0"	939	/* 1265 */ "S4_64\0"
940	/* 1271 */ "T4_64\0"	940	/* 1271 */ "T4_64\0"
941	/* 1277 */ "D15_64\0"	941	/* 1277 */ "D15_64\0"
942	/* 1284 */ "D25_64\0"	942	/* 1284 */ "D25_64\0"
943	/* 1291 */ "D5_64\0"	943	/* 1291 */ "D5_64\0"
944	/* 1297 */ "S5_64\0"	944	/* 1297 */ "S5_64\0"
945	/* 1303 */ "T5_64\0"	945	/* 1303 */ "T5_64\0"
946	/* 1309 */ "D16_64\0"	946	/* 1309 */ "D16_64\0"
947	/* 1316 */ "D26_64\0"	947	/* 1316 */ "D26_64\0"
948	/* 1323 */ "D6_64\0"	948	/* 1323 */ "D6_64\0"
949	/* 1329 */ "S6_64\0"	949	/* 1329 */ "S6_64\0"
950	/* 1335 */ "T6_64\0"	950	/* 1335 */ "T6_64\0"
951	/* 1341 */ "D17_64\0"	951	/* 1341 */ "D17_64\0"
952	/* 1348 */ "D27_64\0"	952	/* 1348 */ "D27_64\0"
953	/* 1355 */ "D7_64\0"	953	/* 1355 */ "D7_64\0"
954	/* 1361 */ "S7_64\0"	954	/* 1361 */ "S7_64\0"
955	/* 1367 */ "T7_64\0"	955	/* 1367 */ "T7_64\0"
956	/* 1373 */ "D18_64\0"	956	/* 1373 */ "D18_64\0"
957	/* 1380 */ "D28_64\0"	957	/* 1380 */ "D28_64\0"
958	/* 1387 */ "D8_64\0"	958	/* 1387 */ "D8_64\0"
959	/* 1393 */ "T8_64\0"	959	/* 1393 */ "T8_64\0"
960	/* 1399 */ "D19_64\0"	960	/* 1399 */ "D19_64\0"
961	/* 1406 */ "D29_64\0"	961	/* 1406 */ "D29_64\0"
962	/* 1413 */ "D9_64\0"	962	/* 1413 */ "D9_64\0"
963	/* 1419 */ "T9_64\0"	963	/* 1419 */ "T9_64\0"
964	/* 1425 */ "RA_64\0"	964	/* 1425 */ "RA_64\0"
965	/* 1431 */ "ZERO_64\0"	965	/* 1431 */ "ZERO_64\0"
966	/* 1439 */ "FP_64\0"	966	/* 1439 */ "FP_64\0"
967	/* 1445 */ "GP_64\0"	967	/* 1445 */ "GP_64\0"
968	/* 1451 */ "SP_64\0"	968	/* 1451 */ "SP_64\0"
969	/* 1457 */ "AT_64\0"	969	/* 1457 */ "AT_64\0"
970	/* 1463 */ "FCC4\0"	970	/* 1463 */ "FCC4\0"
971	/* 1468 */ "D4\0"	971	/* 1468 */ "D4\0"
972	/* 1471 */ "F4\0"	972	/* 1471 */ "F4\0"
973	/* 1474 */ "F_HI4\0"	973	/* 1474 */ "F_HI4\0"
974	/* 1480 */ "FCR4\0"	974	/* 1480 */ "FCR4\0"
975	/* 1485 */ "HWR4\0"	975	/* 1485 */ "HWR4\0"
976	/* 1490 */ "S4\0"	976	/* 1490 */ "S4\0"
977	/* 1493 */ "T4\0"	977	/* 1493 */ "T4\0"
978	/* 1496 */ "W4\0"	978	/* 1496 */ "W4\0"
979	/* 1499 */ "COP05\0"	979	/* 1499 */ "COP05\0"
980	/* 1505 */ "COP015\0"	980	/* 1505 */ "COP015\0"
981	/* 1512 */ "COP215\0"	981	/* 1512 */ "COP215\0"
982	/* 1519 */ "COP315\0"	982	/* 1519 */ "COP315\0"
983	/* 1526 */ "MSA15\0"	983	/* 1526 */ "MSA15\0"
984	/* 1532 */ "D15\0"	984	/* 1532 */ "D15\0"
985	/* 1536 */ "F15\0"	985	/* 1536 */ "F15\0"
986	/* 1540 */ "F_HI15\0"	986	/* 1540 */ "F_HI15\0"
987	/* 1547 */ "FCR15\0"	987	/* 1547 */ "FCR15\0"
988	/* 1553 */ "HWR15\0"	988	/* 1553 */ "HWR15\0"
989	/* 1559 */ "W15\0"	989	/* 1559 */ "W15\0"
990	/* 1563 */ "COP025\0"	990	/* 1563 */ "COP025\0"
991	/* 1570 */ "COP225\0"	991	/* 1570 */ "COP225\0"
992	/* 1577 */ "COP325\0"	992	/* 1577 */ "COP325\0"
993	/* 1584 */ "MSA25\0"	993	/* 1584 */ "MSA25\0"
994	/* 1590 */ "F25\0"	994	/* 1590 */ "F25\0"
995	/* 1594 */ "F_HI25\0"	995	/* 1594 */ "F_HI25\0"
996	/* 1601 */ "COP25\0"	996	/* 1601 */ "COP25\0"
997	/* 1607 */ "FCR25\0"	997	/* 1607 */ "FCR25\0"
998	/* 1613 */ "HWR25\0"	998	/* 1613 */ "HWR25\0"
999	/* 1619 */ "W25\0"	999	/* 1619 */ "W25\0"
1000	/* 1623 */ "COP35\0"	1000	/* 1623 */ "COP35\0"
1001	/* 1629 */ "FCC5\0"	1001	/* 1629 */ "FCC5\0"
1002	/* 1634 */ "D5\0"	1002	/* 1634 */ "D5\0"
1003	/* 1637 */ "F5\0"	1003	/* 1637 */ "F5\0"
1004	/* 1640 */ "F_HI5\0"	1004	/* 1640 */ "F_HI5\0"
1005	/* 1646 */ "FCR5\0"	1005	/* 1646 */ "FCR5\0"
1006	/* 1651 */ "HWR5\0"	1006	/* 1651 */ "HWR5\0"
1007	/* 1656 */ "S5\0"	1007	/* 1656 */ "S5\0"
1008	/* 1659 */ "T5\0"	1008	/* 1659 */ "T5\0"
1009	/* 1662 */ "W5\0"	1009	/* 1662 */ "W5\0"
1010	/* 1665 */ "COP06\0"	1010	/* 1665 */ "COP06\0"
1011	/* 1671 */ "COP016\0"	1011	/* 1671 */ "COP016\0"
1012	/* 1678 */ "COP216\0"	1012	/* 1678 */ "COP216\0"
1013	/* 1685 */ "COP316\0"	1013	/* 1685 */ "COP316\0"
1014	/* 1692 */ "MSA16\0"	1014	/* 1692 */ "MSA16\0"
1015	/* 1698 */ "F16\0"	1015	/* 1698 */ "F16\0"
1016	/* 1702 */ "F_HI16\0"	1016	/* 1702 */ "F_HI16\0"
1017	/* 1709 */ "FCR16\0"	1017	/* 1709 */ "FCR16\0"
1018	/* 1715 */ "HWR16\0"	1018	/* 1715 */ "HWR16\0"
1019	/* 1721 */ "W16\0"	1019	/* 1721 */ "W16\0"
1020	/* 1725 */ "COP026\0"	1020	/* 1725 */ "COP026\0"
1021	/* 1732 */ "COP226\0"	1021	/* 1732 */ "COP226\0"
1022	/* 1739 */ "COP326\0"	1022	/* 1739 */ "COP326\0"
1023	/* 1746 */ "MSA26\0"	1023	/* 1746 */ "MSA26\0"
1024	/* 1752 */ "F26\0"	1024	/* 1752 */ "F26\0"
1025	/* 1756 */ "F_HI26\0"	1025	/* 1756 */ "F_HI26\0"
1026	/* 1763 */ "COP26\0"	1026	/* 1763 */ "COP26\0"
1027	/* 1769 */ "FCR26\0"	1027	/* 1769 */ "FCR26\0"
1028	/* 1775 */ "HWR26\0"	1028	/* 1775 */ "HWR26\0"
1029	/* 1781 */ "W26\0"	1029	/* 1781 */ "W26\0"
1030	/* 1785 */ "COP36\0"	1030	/* 1785 */ "COP36\0"
1031	/* 1791 */ "FCC6\0"	1031	/* 1791 */ "FCC6\0"
1032	/* 1796 */ "D6\0"	1032	/* 1796 */ "D6\0"
1033	/* 1799 */ "F6\0"	1033	/* 1799 */ "F6\0"
1034	/* 1802 */ "F_HI6\0"	1034	/* 1802 */ "F_HI6\0"
1035	/* 1808 */ "FCR6\0"	1035	/* 1808 */ "FCR6\0"
1036	/* 1813 */ "HWR6\0"	1036	/* 1813 */ "HWR6\0"
1037	/* 1818 */ "S6\0"	1037	/* 1818 */ "S6\0"
1038	/* 1821 */ "T6\0"	1038	/* 1821 */ "T6\0"
1039	/* 1824 */ "W6\0"	1039	/* 1824 */ "W6\0"
1040	/* 1827 */ "COP07\0"	1040	/* 1827 */ "COP07\0"
1041	/* 1833 */ "COP017\0"	1041	/* 1833 */ "COP017\0"
1042	/* 1840 */ "COP217\0"	1042	/* 1840 */ "COP217\0"
1043	/* 1847 */ "COP317\0"	1043	/* 1847 */ "COP317\0"
1044	/* 1854 */ "MSA17\0"	1044	/* 1854 */ "MSA17\0"
1045	/* 1860 */ "F17\0"	1045	/* 1860 */ "F17\0"
1046	/* 1864 */ "F_HI17\0"	1046	/* 1864 */ "F_HI17\0"
1047	/* 1871 */ "FCR17\0"	1047	/* 1871 */ "FCR17\0"
1048	/* 1877 */ "HWR17\0"	1048	/* 1877 */ "HWR17\0"
1049	/* 1883 */ "W17\0"	1049	/* 1883 */ "W17\0"
1050	/* 1887 */ "COP027\0"	1050	/* 1887 */ "COP027\0"
1051	/* 1894 */ "COP227\0"	1051	/* 1894 */ "COP227\0"
1052	/* 1901 */ "COP327\0"	1052	/* 1901 */ "COP327\0"
1053	/* 1908 */ "MSA27\0"	1053	/* 1908 */ "MSA27\0"
1054	/* 1914 */ "F27\0"	1054	/* 1914 */ "F27\0"
1055	/* 1918 */ "F_HI27\0"	1055	/* 1918 */ "F_HI27\0"
1056	/* 1925 */ "COP27\0"	1056	/* 1925 */ "COP27\0"
1057	/* 1931 */ "FCR27\0"	1057	/* 1931 */ "FCR27\0"
1058	/* 1937 */ "HWR27\0"	1058	/* 1937 */ "HWR27\0"
1059	/* 1943 */ "W27\0"	1059	/* 1943 */ "W27\0"
1060	/* 1947 */ "COP37\0"	1060	/* 1947 */ "COP37\0"
1061	/* 1953 */ "FCC7\0"	1061	/* 1953 */ "FCC7\0"
1062	/* 1958 */ "D7\0"	1062	/* 1958 */ "D7\0"
1063	/* 1961 */ "F7\0"	1063	/* 1961 */ "F7\0"
1064	/* 1964 */ "F_HI7\0"	1064	/* 1964 */ "F_HI7\0"
1065	/* 1970 */ "FCR7\0"	1065	/* 1970 */ "FCR7\0"
1066	/* 1975 */ "HWR7\0"	1066	/* 1975 */ "HWR7\0"
1067	/* 1980 */ "S7\0"	1067	/* 1980 */ "S7\0"
1068	/* 1983 */ "T7\0"	1068	/* 1983 */ "T7\0"
1069	/* 1986 */ "W7\0"	1069	/* 1986 */ "W7\0"
1070	/* 1989 */ "COP08\0"	1070	/* 1989 */ "COP08\0"
1071	/* 1995 */ "COP018\0"	1071	/* 1995 */ "COP018\0"
1072	/* 2002 */ "COP218\0"	1072	/* 2002 */ "COP218\0"
1073	/* 2009 */ "COP318\0"	1073	/* 2009 */ "COP318\0"
1074	/* 2016 */ "MSA18\0"	1074	/* 2016 */ "MSA18\0"
1075	/* 2022 */ "F18\0"	1075	/* 2022 */ "F18\0"
1076	/* 2026 */ "F_HI18\0"	1076	/* 2026 */ "F_HI18\0"
1077	/* 2033 */ "FCR18\0"	1077	/* 2033 */ "FCR18\0"
1078	/* 2039 */ "HWR18\0"	1078	/* 2039 */ "HWR18\0"
1079	/* 2045 */ "W18\0"	1079	/* 2045 */ "W18\0"
1080	/* 2049 */ "COP028\0"	1080	/* 2049 */ "COP028\0"
1081	/* 2056 */ "COP228\0"	1081	/* 2056 */ "COP228\0"
1082	/* 2063 */ "COP328\0"	1082	/* 2063 */ "COP328\0"
1083	/* 2070 */ "MSA28\0"	1083	/* 2070 */ "MSA28\0"
1084	/* 2076 */ "F28\0"	1084	/* 2076 */ "F28\0"
1085	/* 2080 */ "F_HI28\0"	1085	/* 2080 */ "F_HI28\0"
1086	/* 2087 */ "COP28\0"	1086	/* 2087 */ "COP28\0"
1087	/* 2093 */ "FCR28\0"	1087	/* 2093 */ "FCR28\0"
1088	/* 2099 */ "HWR28\0"	1088	/* 2099 */ "HWR28\0"
1089	/* 2105 */ "W28\0"	1089	/* 2105 */ "W28\0"
1090	/* 2109 */ "COP38\0"	1090	/* 2109 */ "COP38\0"
1091	/* 2115 */ "MSA8\0"	1091	/* 2115 */ "MSA8\0"
1092	/* 2120 */ "D8\0"	1092	/* 2120 */ "D8\0"
1093	/* 2123 */ "F8\0"	1093	/* 2123 */ "F8\0"
1094	/* 2126 */ "F_HI8\0"	1094	/* 2126 */ "F_HI8\0"
1095	/* 2132 */ "FCR8\0"	1095	/* 2132 */ "FCR8\0"
1096	/* 2137 */ "HWR8\0"	1096	/* 2137 */ "HWR8\0"
1097	/* 2142 */ "T8\0"	1097	/* 2142 */ "T8\0"
1098	/* 2145 */ "W8\0"	1098	/* 2145 */ "W8\0"
1099	/* 2148 */ "COP09\0"	1099	/* 2148 */ "COP09\0"
1100	/* 2154 */ "COP019\0"	1100	/* 2154 */ "COP019\0"
1101	/* 2161 */ "COP219\0"	1101	/* 2161 */ "COP219\0"
1102	/* 2168 */ "COP319\0"	1102	/* 2168 */ "COP319\0"
1103	/* 2175 */ "MSA19\0"	1103	/* 2175 */ "MSA19\0"
1104	/* 2181 */ "F19\0"	1104	/* 2181 */ "F19\0"
1105	/* 2185 */ "F_HI19\0"	1105	/* 2185 */ "F_HI19\0"
1106	/* 2192 */ "FCR19\0"	1106	/* 2192 */ "FCR19\0"
1107	/* 2198 */ "HWR19\0"	1107	/* 2198 */ "HWR19\0"
1108	/* 2204 */ "W19\0"	1108	/* 2204 */ "W19\0"
1109	/* 2208 */ "DSPOutFlag16_19\0"	1109	/* 2208 */ "DSPOutFlag16_19\0"
1110	/* 2224 */ "COP029\0"	1110	/* 2224 */ "COP029\0"
1111	/* 2231 */ "COP229\0"	1111	/* 2231 */ "COP229\0"
1112	/* 2238 */ "COP329\0"	1112	/* 2238 */ "COP329\0"
1113	/* 2245 */ "MSA29\0"	1113	/* 2245 */ "MSA29\0"
1114	/* 2251 */ "F29\0"	1114	/* 2251 */ "F29\0"
1115	/* 2255 */ "F_HI29\0"	1115	/* 2255 */ "F_HI29\0"
1116	/* 2262 */ "COP29\0"	1116	/* 2262 */ "COP29\0"
1117	/* 2268 */ "FCR29\0"	1117	/* 2268 */ "FCR29\0"
1118	/* 2274 */ "HWR29\0"	1118	/* 2274 */ "HWR29\0"
1119	/* 2280 */ "W29\0"	1119	/* 2280 */ "W29\0"
1120	/* 2284 */ "COP39\0"	1120	/* 2284 */ "COP39\0"
1121	/* 2290 */ "MSA9\0"	1121	/* 2290 */ "MSA9\0"
1122	/* 2295 */ "D9\0"	1122	/* 2295 */ "D9\0"
1123	/* 2298 */ "F9\0"	1123	/* 2298 */ "F9\0"
1124	/* 2301 */ "F_HI9\0"	1124	/* 2301 */ "F_HI9\0"
1125	/* 2307 */ "FCR9\0"	1125	/* 2307 */ "FCR9\0"
1126	/* 2312 */ "HWR9\0"	1126	/* 2312 */ "HWR9\0"
1127	/* 2317 */ "T9\0"	1127	/* 2317 */ "T9\0"
1128	/* 2320 */ "W9\0"	1128	/* 2320 */ "W9\0"
1129	/* 2323 */ "RA\0"	1129	/* 2323 */ "RA\0"
1130	/* 2326 */ "PC\0"	1130	/* 2326 */ "PC\0"
1131	/* 2329 */ "DSPEFI\0"	1131	/* 2329 */ "DSPEFI\0"
1132	/* 2336 */ "ZERO\0"	1132	/* 2336 */ "ZERO\0"
1133	/* 2341 */ "FP\0"	1133	/* 2341 */ "FP\0"
1134	/* 2344 */ "GP\0"	1134	/* 2344 */ "GP\0"
1135	/* 2347 */ "SP\0"	1135	/* 2347 */ "SP\0"
1136	/* 2350 */ "MSAIR\0"	1136	/* 2350 */ "MSAIR\0"
1137	/* 2356 */ "MSACSR\0"	1137	/* 2356 */ "MSACSR\0"
1138	/* 2363 */ "AT\0"	1138	/* 2363 */ "AT\0"
1139	/* 2366 */ "DSPCCond\0"	1139	/* 2366 */ "DSPCCond\0"
1140	/* 2375 */ "MSASave\0"	1140	/* 2375 */ "MSASave\0"
1141	/* 2383 */ "DSPOutFlag\0"	1141	/* 2383 */ "DSPOutFlag\0"
1142	/* 2394 */ "MSAMap\0"	1142	/* 2394 */ "MSAMap\0"
1143	/* 2401 */ "MSAUnmap\0"	1143	/* 2401 */ "MSAUnmap\0"
1144	/* 2410 */ "DSPPos\0"	1144	/* 2410 */ "DSPPos\0"
1145	/* 2417 */ "MSAAccess\0"	1145	/* 2417 */ "MSAAccess\0"
1146	/* 2427 */ "DSPSCount\0"	1146	/* 2427 */ "DSPSCount\0"
1147	/* 2437 */ "MSARequest\0"	1147	/* 2437 */ "MSARequest\0"
1148	/* 2448 */ "MSAModify\0"	1148	/* 2448 */ "MSAModify\0"
1149	/* 2458 */ "DSPCarry\0"	1149	/* 2458 */ "DSPCarry\0"
1150	};	1150	};
1151	#ifdef __GNUC__	1151	#ifdef __GNUC__
1152	#pragma GCC diagnostic pop	1152	#pragma GCC diagnostic pop
1153	#endif	1153	#endif
1154		1154
1155	extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors	1155	extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
1156	{ 5, 0, 0, 0, 0, 0 },	1156	{ 5, 0, 0, 0, 0, 0 },
1157	{ 2363, 1, 176, 1, 4096, 0 },	1157	{ 2363, 1, 176, 1, 4096, 0 },
1158	{ 2366, 1, 1, 1, 4097, 0 },	1158	{ 2366, 1, 1, 1, 4097, 0 },
1159	{ 2458, 1, 1, 1, 4098, 0 },	1159	{ 2458, 1, 1, 1, 4098, 0 },
1160	{ 2329, 1, 1, 1, 4099, 0 },	1160	{ 2329, 1, 1, 1, 4099, 0 },
1161	{ 2383, 117, 1, 2, 503812, 4 },	1161	{ 2383, 117, 1, 2, 503812, 4 },
1162	{ 2410, 1, 1, 1, 4105, 0 },	1162	{ 2410, 1, 1, 1, 4105, 0 },
1163	{ 2427, 1, 1, 1, 4106, 0 },	1163	{ 2427, 1, 1, 1, 4106, 0 },
1164	{ 2341, 1, 190, 1, 4107, 0 },	1164	{ 2341, 1, 190, 1, 4107, 0 },
1165	{ 2344, 1, 192, 1, 4108, 0 },	1165	{ 2344, 1, 192, 1, 4108, 0 },
1166	{ 2417, 1, 1, 1, 4109, 0 },	1166	{ 2417, 1, 1, 1, 4109, 0 },
1167	{ 2356, 1, 1, 1, 4110, 0 },	1167	{ 2356, 1, 1, 1, 4110, 0 },
1168	{ 2350, 1, 1, 1, 4111, 0 },	1168	{ 2350, 1, 1, 1, 4111, 0 },
1169	{ 2394, 1, 1, 1, 4112, 0 },	1169	{ 2394, 1, 1, 1, 4112, 0 },
1170	{ 2448, 1, 1, 1, 4113, 0 },	1170	{ 2448, 1, 1, 1, 4113, 0 },
1171	{ 2437, 1, 1, 1, 4114, 0 },	1171	{ 2437, 1, 1, 1, 4114, 0 },
1172	{ 2375, 1, 1, 1, 4115, 0 },	1172	{ 2375, 1, 1, 1, 4115, 0 },
1173	{ 2401, 1, 1, 1, 4116, 0 },	1173	{ 2401, 1, 1, 1, 4116, 0 },
1174	{ 2326, 1, 1, 1, 4117, 0 },	1174	{ 2326, 1, 1, 1, 4117, 0 },
1175	{ 2323, 1, 194, 1, 4118, 0 },	1175	{ 2323, 1, 194, 1, 4118, 0 },
1176	{ 2347, 1, 196, 1, 4119, 0 },	1176	{ 2347, 1, 196, 1, 4119, 0 },
1177	{ 2336, 1, 198, 1, 4120, 0 },	1177	{ 2336, 1, 198, 1, 4120, 0 },
1178	{ 197, 1, 198, 1, 4121, 0 },	1178	{ 197, 1, 198, 1, 4121, 0 },
1179	{ 455, 1, 198, 1, 4122, 0 },	1179	{ 455, 1, 198, 1, 4122, 0 },
1180	{ 659, 1, 198, 1, 4123, 0 },	1180	{ 659, 1, 198, 1, 4123, 0 },
1181	{ 857, 1, 198, 1, 4124, 0 },	1181	{ 857, 1, 198, 1, 4124, 0 },
1182	{ 200, 68, 198, 9, 495645, 10 },	1182	{ 200, 68, 198, 9, 495645, 10 },
1183	{ 458, 68, 1, 9, 495647, 10 },	1183	{ 458, 68, 1, 9, 495647, 10 },
1184	{ 662, 68, 1, 9, 495649, 10 },	1184	{ 662, 68, 1, 9, 495649, 10 },
1185	{ 860, 68, 1, 9, 495651, 10 },	1185	{ 860, 68, 1, 9, 495651, 10 },
1186	{ 1457, 115, 1, 0, 4096, 2 },	1186	{ 1457, 115, 1, 0, 4096, 2 },
1187	{ 0, 1, 1, 1, 4133, 0 },	1187	{ 0, 1, 1, 1, 4133, 0 },
1188	{ 258, 1, 1, 1, 4134, 0 },	1188	{ 258, 1, 1, 1, 4134, 0 },
1189	{ 516, 1, 1, 1, 4135, 0 },	1189	{ 516, 1, 1, 1, 4135, 0 },
1190	{ 714, 1, 1, 1, 4136, 0 },	1190	{ 714, 1, 1, 1, 4136, 0 },
1191	{ 904, 1, 1, 1, 4137, 0 },	1191	{ 904, 1, 1, 1, 4137, 0 },
1192	{ 1499, 1, 1, 1, 4138, 0 },	1192	{ 1499, 1, 1, 1, 4138, 0 },
1193	{ 1665, 1, 1, 1, 4139, 0 },	1193	{ 1665, 1, 1, 1, 4139, 0 },
1194	{ 1827, 1, 1, 1, 4140, 0 },	1194	{ 1827, 1, 1, 1, 4140, 0 },
1195	{ 1989, 1, 1, 1, 4141, 0 },	1195	{ 1989, 1, 1, 1, 4141, 0 },
1196	{ 2148, 1, 1, 1, 4142, 0 },	1196	{ 2148, 1, 1, 1, 4142, 0 },
1197	{ 102, 1, 1, 1, 4143, 0 },	1197	{ 102, 1, 1, 1, 4143, 0 },
1198	{ 360, 1, 1, 1, 4144, 0 },	1198	{ 360, 1, 1, 1, 4144, 0 },
1199	{ 618, 1, 1, 1, 4145, 0 },	1199	{ 618, 1, 1, 1, 4145, 0 },
1200	{ 816, 1, 1, 1, 4146, 0 },	1200	{ 816, 1, 1, 1, 4146, 0 },
1201	{ 1006, 1, 1, 1, 4147, 0 },	1201	{ 1006, 1, 1, 1, 4147, 0 },
1202	{ 1601, 1, 1, 1, 4148, 0 },	1202	{ 1601, 1, 1, 1, 4148, 0 },
1203	{ 1763, 1, 1, 1, 4149, 0 },	1203	{ 1763, 1, 1, 1, 4149, 0 },
1204	{ 1925, 1, 1, 1, 4150, 0 },	1204	{ 1925, 1, 1, 1, 4150, 0 },
1205	{ 2087, 1, 1, 1, 4151, 0 },	1205	{ 2087, 1, 1, 1, 4151, 0 },
1206	{ 2262, 1, 1, 1, 4152, 0 },	1206	{ 2262, 1, 1, 1, 4152, 0 },
1207	{ 175, 1, 1, 1, 4153, 0 },	1207	{ 175, 1, 1, 1, 4153, 0 },
1208	{ 433, 1, 1, 1, 4154, 0 },	1208	{ 433, 1, 1, 1, 4154, 0 },
1209	{ 653, 1, 1, 1, 4155, 0 },	1209	{ 653, 1, 1, 1, 4155, 0 },
1210	{ 851, 1, 1, 1, 4156, 0 },	1210	{ 851, 1, 1, 1, 4156, 0 },
1211	{ 1028, 1, 1, 1, 4157, 0 },	1211	{ 1028, 1, 1, 1, 4157, 0 },
1212	{ 1623, 1, 1, 1, 4158, 0 },	1212	{ 1623, 1, 1, 1, 4158, 0 },
1213	{ 1785, 1, 1, 1, 4159, 0 },	1213	{ 1785, 1, 1, 1, 4159, 0 },
1214	{ 1947, 1, 1, 1, 4160, 0 },	1214	{ 1947, 1, 1, 1, 4160, 0 },
1215	{ 2109, 1, 1, 1, 4161, 0 },	1215	{ 2109, 1, 1, 1, 4161, 0 },
1216	{ 2284, 1, 1, 1, 4162, 0 },	1216	{ 2284, 1, 1, 1, 4162, 0 },
1217	{ 6, 1, 1, 1, 4163, 0 },	1217	{ 6, 1, 1, 1, 4163, 0 },
1218	{ 264, 1, 1, 1, 4164, 0 },	1218	{ 264, 1, 1, 1, 4164, 0 },
1219	{ 522, 1, 1, 1, 4165, 0 },	1219	{ 522, 1, 1, 1, 4165, 0 },
1220	{ 720, 1, 1, 1, 4166, 0 },	1220	{ 720, 1, 1, 1, 4166, 0 },
1221	{ 910, 1, 1, 1, 4167, 0 },	1221	{ 910, 1, 1, 1, 4167, 0 },
1222	{ 1505, 1, 1, 1, 4168, 0 },	1222	{ 1505, 1, 1, 1, 4168, 0 },
1223	{ 1671, 1, 1, 1, 4169, 0 },	1223	{ 1671, 1, 1, 1, 4169, 0 },
1224	{ 1833, 1, 1, 1, 4170, 0 },	1224	{ 1833, 1, 1, 1, 4170, 0 },
1225	{ 1995, 1, 1, 1, 4171, 0 },	1225	{ 1995, 1, 1, 1, 4171, 0 },
1226	{ 2154, 1, 1, 1, 4172, 0 },	1226	{ 2154, 1, 1, 1, 4172, 0 },
1227	{ 64, 1, 1, 1, 4173, 0 },	1227	{ 64, 1, 1, 1, 4173, 0 },
1228	{ 322, 1, 1, 1, 4174, 0 },	1228	{ 322, 1, 1, 1, 4174, 0 },
1229	{ 580, 1, 1, 1, 4175, 0 },	1229	{ 580, 1, 1, 1, 4175, 0 },
1230	{ 778, 1, 1, 1, 4176, 0 },	1230	{ 778, 1, 1, 1, 4176, 0 },
1231	{ 968, 1, 1, 1, 4177, 0 },	1231	{ 968, 1, 1, 1, 4177, 0 },
1232	{ 1563, 1, 1, 1, 4178, 0 },	1232	{ 1563, 1, 1, 1, 4178, 0 },
1233	{ 1725, 1, 1, 1, 4179, 0 },	1233	{ 1725, 1, 1, 1, 4179, 0 },
1234	{ 1887, 1, 1, 1, 4180, 0 },	1234	{ 1887, 1, 1, 1, 4180, 0 },
1235	{ 2049, 1, 1, 1, 4181, 0 },	1235	{ 2049, 1, 1, 1, 4181, 0 },
1236	{ 2224, 1, 1, 1, 4182, 0 },	1236	{ 2224, 1, 1, 1, 4182, 0 },
1237	{ 137, 1, 1, 1, 4183, 0 },	1237	{ 137, 1, 1, 1, 4183, 0 },
1238	{ 395, 1, 1, 1, 4184, 0 },	1238	{ 395, 1, 1, 1, 4184, 0 },
1239	{ 13, 1, 1, 1, 4185, 0 },	1239	{ 13, 1, 1, 1, 4185, 0 },
1240	{ 271, 1, 1, 1, 4186, 0 },	1240	{ 271, 1, 1, 1, 4186, 0 },
1241	{ 529, 1, 1, 1, 4187, 0 },	1241	{ 529, 1, 1, 1, 4187, 0 },
1242	{ 727, 1, 1, 1, 4188, 0 },	1242	{ 727, 1, 1, 1, 4188, 0 },
1243	{ 917, 1, 1, 1, 4189, 0 },	1243	{ 917, 1, 1, 1, 4189, 0 },
1244	{ 1512, 1, 1, 1, 4190, 0 },	1244	{ 1512, 1, 1, 1, 4190, 0 },
1245	{ 1678, 1, 1, 1, 4191, 0 },	1245	{ 1678, 1, 1, 1, 4191, 0 },
1246	{ 1840, 1, 1, 1, 4192, 0 },	1246	{ 1840, 1, 1, 1, 4192, 0 },
1247	{ 2002, 1, 1, 1, 4193, 0 },	1247	{ 2002, 1, 1, 1, 4193, 0 },
1248	{ 2161, 1, 1, 1, 4194, 0 },	1248	{ 2161, 1, 1, 1, 4194, 0 },
1249	{ 71, 1, 1, 1, 4195, 0 },	1249	{ 71, 1, 1, 1, 4195, 0 },
1250	{ 329, 1, 1, 1, 4196, 0 },	1250	{ 329, 1, 1, 1, 4196, 0 },
1251	{ 587, 1, 1, 1, 4197, 0 },	1251	{ 587, 1, 1, 1, 4197, 0 },
1252	{ 785, 1, 1, 1, 4198, 0 },	1252	{ 785, 1, 1, 1, 4198, 0 },
1253	{ 975, 1, 1, 1, 4199, 0 },	1253	{ 975, 1, 1, 1, 4199, 0 },
1254	{ 1570, 1, 1, 1, 4200, 0 },	1254	{ 1570, 1, 1, 1, 4200, 0 },
1255	{ 1732, 1, 1, 1, 4201, 0 },	1255	{ 1732, 1, 1, 1, 4201, 0 },
1256	{ 1894, 1, 1, 1, 4202, 0 },	1256	{ 1894, 1, 1, 1, 4202, 0 },
1257	{ 2056, 1, 1, 1, 4203, 0 },	1257	{ 2056, 1, 1, 1, 4203, 0 },
1258	{ 2231, 1, 1, 1, 4204, 0 },	1258	{ 2231, 1, 1, 1, 4204, 0 },
1259	{ 144, 1, 1, 1, 4205, 0 },	1259	{ 144, 1, 1, 1, 4205, 0 },
1260	{ 402, 1, 1, 1, 4206, 0 },	1260	{ 402, 1, 1, 1, 4206, 0 },
1261	{ 20, 1, 1, 1, 4207, 0 },	1261	{ 20, 1, 1, 1, 4207, 0 },
1262	{ 278, 1, 1, 1, 4208, 0 },	1262	{ 278, 1, 1, 1, 4208, 0 },
1263	{ 536, 1, 1, 1, 4209, 0 },	1263	{ 536, 1, 1, 1, 4209, 0 },
1264	{ 734, 1, 1, 1, 4210, 0 },	1264	{ 734, 1, 1, 1, 4210, 0 },
1265	{ 924, 1, 1, 1, 4211, 0 },	1265	{ 924, 1, 1, 1, 4211, 0 },
1266	{ 1519, 1, 1, 1, 4212, 0 },	1266	{ 1519, 1, 1, 1, 4212, 0 },
1267	{ 1685, 1, 1, 1, 4213, 0 },	1267	{ 1685, 1, 1, 1, 4213, 0 },
1268	{ 1847, 1, 1, 1, 4214, 0 },	1268	{ 1847, 1, 1, 1, 4214, 0 },
1269	{ 2009, 1, 1, 1, 4215, 0 },	1269	{ 2009, 1, 1, 1, 4215, 0 },
1270	{ 2168, 1, 1, 1, 4216, 0 },	1270	{ 2168, 1, 1, 1, 4216, 0 },
1271	{ 78, 1, 1, 1, 4217, 0 },	1271	{ 78, 1, 1, 1, 4217, 0 },
1272	{ 336, 1, 1, 1, 4218, 0 },	1272	{ 336, 1, 1, 1, 4218, 0 },
1273	{ 594, 1, 1, 1, 4219, 0 },	1273	{ 594, 1, 1, 1, 4219, 0 },
1274	{ 792, 1, 1, 1, 4220, 0 },	1274	{ 792, 1, 1, 1, 4220, 0 },
1275	{ 982, 1, 1, 1, 4221, 0 },	1275	{ 982, 1, 1, 1, 4221, 0 },
1276	{ 1577, 1, 1, 1, 4222, 0 },	1276	{ 1577, 1, 1, 1, 4222, 0 },
1277	{ 1739, 1, 1, 1, 4223, 0 },	1277	{ 1739, 1, 1, 1, 4223, 0 },
1278	{ 1901, 1, 1, 1, 4224, 0 },	1278	{ 1901, 1, 1, 1, 4224, 0 },
1279	{ 2063, 1, 1, 1, 4225, 0 },	1279	{ 2063, 1, 1, 1, 4225, 0 },
1280	{ 2238, 1, 1, 1, 4226, 0 },	1280	{ 2238, 1, 1, 1, 4226, 0 },
1281	{ 151, 1, 1, 1, 4227, 0 },	1281	{ 151, 1, 1, 1, 4227, 0 },
1282	{ 409, 1, 1, 1, 4228, 0 },	1282	{ 409, 1, 1, 1, 4228, 0 },
1283	{ 209, 128, 1, 9, 495749, 10 },	1283	{ 209, 128, 1, 9, 495749, 10 },
1284	{ 467, 131, 1, 9, 495751, 10 },	1284	{ 467, 131, 1, 9, 495751, 10 },
1285	{ 671, 134, 1, 9, 495753, 10 },	1285	{ 671, 134, 1, 9, 495753, 10 },
1286	{ 869, 137, 1, 9, 495755, 10 },	1286	{ 869, 137, 1, 9, 495755, 10 },
1287	{ 1468, 140, 1, 9, 495757, 10 },	1287	{ 1468, 140, 1, 9, 495757, 10 },
1288	{ 1634, 143, 1, 9, 495759, 10 },	1288	{ 1634, 143, 1, 9, 495759, 10 },
1289	{ 1796, 146, 1, 9, 495761, 10 },	1289	{ 1796, 146, 1, 9, 495761, 10 },
1290	{ 1958, 149, 1, 9, 495763, 10 },	1290	{ 1958, 149, 1, 9, 495763, 10 },
1291	{ 2120, 152, 1, 9, 495765, 10 },	1291	{ 2120, 152, 1, 9, 495765, 10 },
1292	{ 2295, 155, 1, 9, 495767, 10 },	1292	{ 2295, 155, 1, 9, 495767, 10 },
1293	{ 33, 158, 1, 9, 495769, 10 },	1293	{ 33, 158, 1, 9, 495769, 10 },
1294	{ 291, 161, 1, 9, 495771, 10 },	1294	{ 291, 161, 1, 9, 495771, 10 },
1295	{ 549, 164, 1, 9, 495773, 10 },	1295	{ 549, 164, 1, 9, 495773, 10 },
1296	{ 747, 167, 1, 9, 495775, 10 },	1296	{ 747, 167, 1, 9, 495775, 10 },
1297	{ 937, 170, 1, 9, 495777, 10 },	1297	{ 937, 170, 1, 9, 495777, 10 },
1298	{ 1532, 173, 1, 9, 495779, 10 },	1298	{ 1532, 173, 1, 9, 495779, 10 },
1299	{ 124, 1, 28, 1, 4101, 0 },	1299	{ 124, 1, 28, 1, 4101, 0 },
1300	{ 382, 1, 26, 1, 4102, 0 },	1300	{ 382, 1, 26, 1, 4102, 0 },
1301	{ 640, 1, 24, 1, 4103, 0 },	1301	{ 640, 1, 24, 1, 4103, 0 },
1302	{ 838, 1, 22, 1, 4104, 0 },	1302	{ 838, 1, 22, 1, 4104, 0 },
1303	{ 212, 1, 39, 1, 4229, 0 },	1303	{ 212, 1, 39, 1, 4229, 0 },
1304	{ 470, 1, 43, 1, 4230, 0 },	1304	{ 470, 1, 43, 1, 4230, 0 },
1305	{ 674, 1, 43, 1, 4231, 0 },	1305	{ 674, 1, 43, 1, 4231, 0 },
1306	{ 872, 1, 47, 1, 4232, 0 },	1306	{ 872, 1, 47, 1, 4232, 0 },
1307	{ 1471, 1, 47, 1, 4233, 0 },	1307	{ 1471, 1, 47, 1, 4233, 0 },
1308	{ 1637, 1, 51, 1, 4234, 0 },	1308	{ 1637, 1, 51, 1, 4234, 0 },
1309	{ 1799, 1, 51, 1, 4235, 0 },	1309	{ 1799, 1, 51, 1, 4235, 0 },
1310	{ 1961, 1, 55, 1, 4236, 0 },	1310	{ 1961, 1, 55, 1, 4236, 0 },
1311	{ 2123, 1, 55, 1, 4237, 0 },	1311	{ 2123, 1, 55, 1, 4237, 0 },
1312	{ 2298, 1, 59, 1, 4238, 0 },	1312	{ 2298, 1, 59, 1, 4238, 0 },
1313	{ 37, 1, 59, 1, 4239, 0 },	1313	{ 37, 1, 59, 1, 4239, 0 },
1314	{ 295, 1, 63, 1, 4240, 0 },	1314	{ 295, 1, 63, 1, 4240, 0 },
1315	{ 553, 1, 63, 1, 4241, 0 },	1315	{ 553, 1, 63, 1, 4241, 0 },
1316	{ 751, 1, 67, 1, 4242, 0 },	1316	{ 751, 1, 67, 1, 4242, 0 },
1317	{ 941, 1, 67, 1, 4243, 0 },	1317	{ 941, 1, 67, 1, 4243, 0 },
1318	{ 1536, 1, 71, 1, 4244, 0 },	1318	{ 1536, 1, 71, 1, 4244, 0 },
1319	{ 1698, 1, 71, 1, 4245, 0 },	1319	{ 1698, 1, 71, 1, 4245, 0 },
1320	{ 1860, 1, 75, 1, 4246, 0 },	1320	{ 1860, 1, 75, 1, 4246, 0 },
1321	{ 2022, 1, 75, 1, 4247, 0 },	1321	{ 2022, 1, 75, 1, 4247, 0 },
1322	{ 2181, 1, 79, 1, 4248, 0 },	1322	{ 2181, 1, 79, 1, 4248, 0 },
1323	{ 91, 1, 79, 1, 4249, 0 },	1323	{ 91, 1, 79, 1, 4249, 0 },
1324	{ 349, 1, 83, 1, 4250, 0 },	1324	{ 349, 1, 83, 1, 4250, 0 },
1325	{ 607, 1, 83, 1, 4251, 0 },	1325	{ 607, 1, 83, 1, 4251, 0 },
1326	{ 805, 1, 87, 1, 4252, 0 },	1326	{ 805, 1, 87, 1, 4252, 0 },
1327	{ 995, 1, 87, 1, 4253, 0 },	1327	{ 995, 1, 87, 1, 4253, 0 },
1328	{ 1590, 1, 91, 1, 4254, 0 },	1328	{ 1590, 1, 91, 1, 4254, 0 },
1329	{ 1752, 1, 91, 1, 4255, 0 },	1329	{ 1752, 1, 91, 1, 4255, 0 },
1330	{ 1914, 1, 95, 1, 4256, 0 },	1330	{ 1914, 1, 95, 1, 4256, 0 },
1331	{ 2076, 1, 95, 1, 4257, 0 },	1331	{ 2076, 1, 95, 1, 4257, 0 },
1332	{ 2251, 1, 99, 1, 4258, 0 },	1332	{ 2251, 1, 99, 1, 4258, 0 },
1333	{ 164, 1, 99, 1, 4259, 0 },	1333	{ 164, 1, 99, 1, 4259, 0 },
1334	{ 422, 1, 103, 1, 4260, 0 },	1334	{ 422, 1, 103, 1, 4260, 0 },
1335	{ 204, 1, 1, 1, 4261, 0 },	1335	{ 204, 1, 1, 1, 4261, 0 },
1336	{ 462, 1, 1, 1, 4262, 0 },	1336	{ 462, 1, 1, 1, 4262, 0 },
1337	{ 666, 1, 1, 1, 4263, 0 },	1337	{ 666, 1, 1, 1, 4263, 0 },
1338	{ 864, 1, 1, 1, 4264, 0 },	1338	{ 864, 1, 1, 1, 4264, 0 },
1339	{ 1463, 1, 1, 1, 4265, 0 },	1339	{ 1463, 1, 1, 1, 4265, 0 },
1340	{ 1629, 1, 1, 1, 4266, 0 },	1340	{ 1629, 1, 1, 1, 4266, 0 },
1341	{ 1791, 1, 1, 1, 4267, 0 },	1341	{ 1791, 1, 1, 1, 4267, 0 },
1342	{ 1953, 1, 1, 1, 4268, 0 },	1342	{ 1953, 1, 1, 1, 4268, 0 },
1343	{ 236, 1, 1, 1, 4269, 0 },	1343	{ 236, 1, 1, 1, 4269, 0 },
1344	{ 494, 1, 1, 1, 4270, 0 },	1344	{ 494, 1, 1, 1, 4270, 0 },
1345	{ 695, 1, 1, 1, 4271, 0 },	1345	{ 695, 1, 1, 1, 4271, 0 },
1346	{ 885, 1, 1, 1, 4272, 0 },	1346	{ 885, 1, 1, 1, 4272, 0 },
1347	{ 1480, 1, 1, 1, 4273, 0 },	1347	{ 1480, 1, 1, 1, 4273, 0 },
1348	{ 1646, 1, 1, 1, 4274, 0 },	1348	{ 1646, 1, 1, 1, 4274, 0 },
1349	{ 1808, 1, 1, 1, 4275, 0 },	1349	{ 1808, 1, 1, 1, 4275, 0 },
1350	{ 1970, 1, 1, 1, 4276, 0 },	1350	{ 1970, 1, 1, 1, 4276, 0 },
1351	{ 2132, 1, 1, 1, 4277, 0 },	1351	{ 2132, 1, 1, 1, 4277, 0 },
1352	{ 2307, 1, 1, 1, 4278, 0 },	1352	{ 2307, 1, 1, 1, 4278, 0 },
1353	{ 48, 1, 1, 1, 4279, 0 },	1353	{ 48, 1, 1, 1, 4279, 0 },
1354	{ 306, 1, 1, 1, 4280, 0 },	1354	{ 306, 1, 1, 1, 4280, 0 },
1355	{ 564, 1, 1, 1, 4281, 0 },	1355	{ 564, 1, 1, 1, 4281, 0 },
1356	{ 762, 1, 1, 1, 4282, 0 },	1356	{ 762, 1, 1, 1, 4282, 0 },
1357	{ 952, 1, 1, 1, 4283, 0 },	1357	{ 952, 1, 1, 1, 4283, 0 },
1358	{ 1547, 1, 1, 1, 4284, 0 },	1358	{ 1547, 1, 1, 1, 4284, 0 },
1359	{ 1709, 1, 1, 1, 4285, 0 },	1359	{ 1709, 1, 1, 1, 4285, 0 },
1360	{ 1871, 1, 1, 1, 4286, 0 },	1360	{ 1871, 1, 1, 1, 4286, 0 },
1361	{ 2033, 1, 1, 1, 4287, 0 },	1361	{ 2033, 1, 1, 1, 4287, 0 },
1362	{ 2192, 1, 1, 1, 4288, 0 },	1362	{ 2192, 1, 1, 1, 4288, 0 },
1363	{ 108, 1, 1, 1, 4289, 0 },	1363	{ 108, 1, 1, 1, 4289, 0 },
1364	{ 366, 1, 1, 1, 4290, 0 },	1364	{ 366, 1, 1, 1, 4290, 0 },
1365	{ 624, 1, 1, 1, 4291, 0 },	1365	{ 624, 1, 1, 1, 4291, 0 },
1366	{ 822, 1, 1, 1, 4292, 0 },	1366	{ 822, 1, 1, 1, 4292, 0 },
1367	{ 1012, 1, 1, 1, 4293, 0 },	1367	{ 1012, 1, 1, 1, 4293, 0 },
1368	{ 1607, 1, 1, 1, 4294, 0 },	1368	{ 1607, 1, 1, 1, 4294, 0 },
1369	{ 1769, 1, 1, 1, 4295, 0 },	1369	{ 1769, 1, 1, 1, 4295, 0 },
1370	{ 1931, 1, 1, 1, 4296, 0 },	1370	{ 1931, 1, 1, 1, 4296, 0 },
1371	{ 2093, 1, 1, 1, 4297, 0 },	1371	{ 2093, 1, 1, 1, 4297, 0 },
1372	{ 2268, 1, 1, 1, 4298, 0 },	1372	{ 2268, 1, 1, 1, 4298, 0 },
1373	{ 181, 1, 1, 1, 4299, 0 },	1373	{ 181, 1, 1, 1, 4299, 0 },
1374	{ 439, 1, 1, 1, 4300, 0 },	1374	{ 439, 1, 1, 1, 4300, 0 },
1375	{ 1439, 18, 1, 0, 4107, 2 },	1375	{ 1439, 18, 1, 0, 4107, 2 },
1376	{ 215, 1, 36, 1, 4301, 0 },	1376	{ 215, 1, 36, 1, 4301, 0 },
1377	{ 473, 1, 36, 1, 4302, 0 },	1377	{ 473, 1, 36, 1, 4302, 0 },
1378	{ 677, 1, 36, 1, 4303, 0 },	1378	{ 677, 1, 36, 1, 4303, 0 },
1379	{ 875, 1, 36, 1, 4304, 0 },	1379	{ 875, 1, 36, 1, 4304, 0 },
1380	{ 1474, 1, 36, 1, 4305, 0 },	1380	{ 1474, 1, 36, 1, 4305, 0 },
1381	{ 1640, 1, 36, 1, 4306, 0 },	1381	{ 1640, 1, 36, 1, 4306, 0 },
1382	{ 1802, 1, 36, 1, 4307, 0 },	1382	{ 1802, 1, 36, 1, 4307, 0 },
1383	{ 1964, 1, 36, 1, 4308, 0 },	1383	{ 1964, 1, 36, 1, 4308, 0 },
1384	{ 2126, 1, 36, 1, 4309, 0 },	1384	{ 2126, 1, 36, 1, 4309, 0 },
1385	{ 2301, 1, 36, 1, 4310, 0 },	1385	{ 2301, 1, 36, 1, 4310, 0 },
1386	{ 41, 1, 36, 1, 4311, 0 },	1386	{ 41, 1, 36, 1, 4311, 0 },
1387	{ 299, 1, 36, 1, 4312, 0 },	1387	{ 299, 1, 36, 1, 4312, 0 },
1388	{ 557, 1, 36, 1, 4313, 0 },	1388	{ 557, 1, 36, 1, 4313, 0 },
1389	{ 755, 1, 36, 1, 4314, 0 },	1389	{ 755, 1, 36, 1, 4314, 0 },
1390	{ 945, 1, 36, 1, 4315, 0 },	1390	{ 945, 1, 36, 1, 4315, 0 },
1391	{ 1540, 1, 36, 1, 4316, 0 },	1391	{ 1540, 1, 36, 1, 4316, 0 },
1392	{ 1702, 1, 36, 1, 4317, 0 },	1392	{ 1702, 1, 36, 1, 4317, 0 },
1393	{ 1864, 1, 36, 1, 4318, 0 },	1393	{ 1864, 1, 36, 1, 4318, 0 },
1394	{ 2026, 1, 36, 1, 4319, 0 },	1394	{ 2026, 1, 36, 1, 4319, 0 },
1395	{ 2185, 1, 36, 1, 4320, 0 },	1395	{ 2185, 1, 36, 1, 4320, 0 },
1396	{ 95, 1, 36, 1, 4321, 0 },	1396	{ 95, 1, 36, 1, 4321, 0 },
1397	{ 353, 1, 36, 1, 4322, 0 },	1397	{ 353, 1, 36, 1, 4322, 0 },
1398	{ 611, 1, 36, 1, 4323, 0 },	1398	{ 611, 1, 36, 1, 4323, 0 },
1399	{ 809, 1, 36, 1, 4324, 0 },	1399	{ 809, 1, 36, 1, 4324, 0 },
1400	{ 999, 1, 36, 1, 4325, 0 },	1400	{ 999, 1, 36, 1, 4325, 0 },
1401	{ 1594, 1, 36, 1, 4326, 0 },	1401	{ 1594, 1, 36, 1, 4326, 0 },
1402	{ 1756, 1, 36, 1, 4327, 0 },	1402	{ 1756, 1, 36, 1, 4327, 0 },
1403	{ 1918, 1, 36, 1, 4328, 0 },	1403	{ 1918, 1, 36, 1, 4328, 0 },
1404	{ 2080, 1, 36, 1, 4329, 0 },	1404	{ 2080, 1, 36, 1, 4329, 0 },
1405	{ 2255, 1, 36, 1, 4330, 0 },	1405	{ 2255, 1, 36, 1, 4330, 0 },
1406	{ 168, 1, 36, 1, 4331, 0 },	1406	{ 168, 1, 36, 1, 4331, 0 },
1407	{ 426, 1, 36, 1, 4332, 0 },	1407	{ 426, 1, 36, 1, 4332, 0 },
1408	{ 1445, 10, 1, 0, 4108, 2 },	1408	{ 1445, 10, 1, 0, 4108, 2 },
1409	{ 217, 1, 111, 1, 4126, 0 },	1409	{ 217, 1, 111, 1, 4126, 0 },
1410	{ 475, 1, 16, 1, 4128, 0 },	1410	{ 475, 1, 16, 1, 4128, 0 },
1411	{ 679, 1, 16, 1, 4130, 0 },	1411	{ 679, 1, 16, 1, 4130, 0 },
1412	{ 877, 1, 16, 1, 4132, 0 },	1412	{ 877, 1, 16, 1, 4132, 0 },
1413	{ 241, 1, 1, 1, 4333, 0 },	1413	{ 241, 1, 1, 1, 4333, 0 },
1414	{ 499, 1, 1, 1, 4334, 0 },	1414	{ 499, 1, 1, 1, 4334, 0 },
1415	{ 700, 1, 1, 1, 4335, 0 },	1415	{ 700, 1, 1, 1, 4335, 0 },
1416	{ 890, 1, 1, 1, 4336, 0 },	1416	{ 890, 1, 1, 1, 4336, 0 },
1417	{ 1485, 1, 1, 1, 4337, 0 },	1417	{ 1485, 1, 1, 1, 4337, 0 },
1418	{ 1651, 1, 1, 1, 4338, 0 },	1418	{ 1651, 1, 1, 1, 4338, 0 },
1419	{ 1813, 1, 1, 1, 4339, 0 },	1419	{ 1813, 1, 1, 1, 4339, 0 },
1420	{ 1975, 1, 1, 1, 4340, 0 },	1420	{ 1975, 1, 1, 1, 4340, 0 },
1421	{ 2137, 1, 1, 1, 4341, 0 },	1421	{ 2137, 1, 1, 1, 4341, 0 },
1422	{ 2312, 1, 1, 1, 4342, 0 },	1422	{ 2312, 1, 1, 1, 4342, 0 },
1423	{ 54, 1, 1, 1, 4343, 0 },	1423	{ 54, 1, 1, 1, 4343, 0 },
1424	{ 312, 1, 1, 1, 4344, 0 },	1424	{ 312, 1, 1, 1, 4344, 0 },
1425	{ 570, 1, 1, 1, 4345, 0 },	1425	{ 570, 1, 1, 1, 4345, 0 },
1426	{ 768, 1, 1, 1, 4346, 0 },	1426	{ 768, 1, 1, 1, 4346, 0 },
1427	{ 958, 1, 1, 1, 4347, 0 },	1427	{ 958, 1, 1, 1, 4347, 0 },
1428	{ 1553, 1, 1, 1, 4348, 0 },	1428	{ 1553, 1, 1, 1, 4348, 0 },
1429	{ 1715, 1, 1, 1, 4349, 0 },	1429	{ 1715, 1, 1, 1, 4349, 0 },
1430	{ 1877, 1, 1, 1, 4350, 0 },	1430	{ 1877, 1, 1, 1, 4350, 0 },
1431	{ 2039, 1, 1, 1, 4351, 0 },	1431	{ 2039, 1, 1, 1, 4351, 0 },
1432	{ 2198, 1, 1, 1, 4352, 0 },	1432	{ 2198, 1, 1, 1, 4352, 0 },
1433	{ 114, 1, 1, 1, 4353, 0 },	1433	{ 114, 1, 1, 1, 4353, 0 },
1434	{ 372, 1, 1, 1, 4354, 0 },	1434	{ 372, 1, 1, 1, 4354, 0 },
1435	{ 630, 1, 1, 1, 4355, 0 },	1435	{ 630, 1, 1, 1, 4355, 0 },
1436	{ 828, 1, 1, 1, 4356, 0 },	1436	{ 828, 1, 1, 1, 4356, 0 },
1437	{ 1018, 1, 1, 1, 4357, 0 },	1437	{ 1018, 1, 1, 1, 4357, 0 },
1438	{ 1613, 1, 1, 1, 4358, 0 },	1438	{ 1613, 1, 1, 1, 4358, 0 },
1439	{ 1775, 1, 1, 1, 4359, 0 },	1439	{ 1775, 1, 1, 1, 4359, 0 },
1440	{ 1937, 1, 1, 1, 4360, 0 },	1440	{ 1937, 1, 1, 1, 4360, 0 },
1441	{ 2099, 1, 1, 1, 4361, 0 },	1441	{ 2099, 1, 1, 1, 4361, 0 },
1442	{ 2274, 1, 1, 1, 4362, 0 },	1442	{ 2274, 1, 1, 1, 4362, 0 },
1443	{ 187, 1, 1, 1, 4363, 0 },	1443	{ 187, 1, 1, 1, 4363, 0 },
1444	{ 445, 1, 1, 1, 4364, 0 },	1444	{ 445, 1, 1, 1, 4364, 0 },
1445	{ 221, 1, 188, 1, 4365, 0 },	1445	{ 221, 1, 188, 1, 4365, 0 },
1446	{ 479, 1, 188, 1, 4366, 0 },	1446	{ 479, 1, 188, 1, 4366, 0 },
1447	{ 229, 1, 107, 1, 4125, 0 },	1447	{ 229, 1, 107, 1, 4125, 0 },
1448	{ 487, 1, 8, 1, 4127, 0 },	1448	{ 487, 1, 8, 1, 4127, 0 },
1449	{ 688, 1, 8, 1, 4129, 0 },	1449	{ 688, 1, 8, 1, 4129, 0 },
1450	{ 881, 1, 8, 1, 4131, 0 },	1450	{ 881, 1, 8, 1, 4131, 0 },
1451	{ 224, 1, 1, 1, 4367, 0 },	1451	{ 224, 1, 1, 1, 4367, 0 },
1452	{ 482, 1, 1, 1, 4368, 0 },	1452	{ 482, 1, 1, 1, 4368, 0 },
1453	{ 683, 1, 1, 1, 4369, 0 },	1453	{ 683, 1, 1, 1, 4369, 0 },
1454	{ 2115, 1, 1, 1, 4370, 0 },	1454	{ 2115, 1, 1, 1, 4370, 0 },
1455	{ 2290, 1, 1, 1, 4371, 0 },	1455	{ 2290, 1, 1, 1, 4371, 0 },
1456	{ 27, 1, 1, 1, 4372, 0 },	1456	{ 27, 1, 1, 1, 4372, 0 },
1457	{ 285, 1, 1, 1, 4373, 0 },	1457	{ 285, 1, 1, 1, 4373, 0 },
1458	{ 543, 1, 1, 1, 4374, 0 },	1458	{ 543, 1, 1, 1, 4374, 0 },
1459	{ 741, 1, 1, 1, 4375, 0 },	1459	{ 741, 1, 1, 1, 4375, 0 },
1460	{ 931, 1, 1, 1, 4376, 0 },	1460	{ 931, 1, 1, 1, 4376, 0 },
1461	{ 1526, 1, 1, 1, 4377, 0 },	1461	{ 1526, 1, 1, 1, 4377, 0 },
1462	{ 1692, 1, 1, 1, 4378, 0 },	1462	{ 1692, 1, 1, 1, 4378, 0 },
1463	{ 1854, 1, 1, 1, 4379, 0 },	1463	{ 1854, 1, 1, 1, 4379, 0 },
1464	{ 2016, 1, 1, 1, 4380, 0 },	1464	{ 2016, 1, 1, 1, 4380, 0 },
1465	{ 2175, 1, 1, 1, 4381, 0 },	1465	{ 2175, 1, 1, 1, 4381, 0 },
1466	{ 85, 1, 1, 1, 4382, 0 },	1466	{ 85, 1, 1, 1, 4382, 0 },
1467	{ 343, 1, 1, 1, 4383, 0 },	1467	{ 343, 1, 1, 1, 4383, 0 },
1468	{ 601, 1, 1, 1, 4384, 0 },	1468	{ 601, 1, 1, 1, 4384, 0 },
1469	{ 799, 1, 1, 1, 4385, 0 },	1469	{ 799, 1, 1, 1, 4385, 0 },
1470	{ 989, 1, 1, 1, 4386, 0 },	1470	{ 989, 1, 1, 1, 4386, 0 },
1471	{ 1584, 1, 1, 1, 4387, 0 },	1471	{ 1584, 1, 1, 1, 4387, 0 },
1472	{ 1746, 1, 1, 1, 4388, 0 },	1472	{ 1746, 1, 1, 1, 4388, 0 },
1473	{ 1908, 1, 1, 1, 4389, 0 },	1473	{ 1908, 1, 1, 1, 4389, 0 },
1474	{ 2070, 1, 1, 1, 4390, 0 },	1474	{ 2070, 1, 1, 1, 4390, 0 },
1475	{ 2245, 1, 1, 1, 4391, 0 },	1475	{ 2245, 1, 1, 1, 4391, 0 },
1476	{ 158, 1, 1, 1, 4392, 0 },	1476	{ 158, 1, 1, 1, 4392, 0 },
1477	{ 416, 1, 1, 1, 4393, 0 },	1477	{ 416, 1, 1, 1, 4393, 0 },
1478	{ 233, 1, 1, 1, 4394, 0 },	1478	{ 233, 1, 1, 1, 4394, 0 },
1479	{ 491, 1, 1, 1, 4395, 0 },	1479	{ 491, 1, 1, 1, 4395, 0 },
1480	{ 692, 1, 1, 1, 4396, 0 },	1480	{ 692, 1, 1, 1, 4396, 0 },
1481	{ 1425, 6, 1, 0, 4118, 2 },	1481	{ 1425, 6, 1, 0, 4118, 2 },
1482	{ 246, 1, 186, 1, 4397, 0 },	1482	{ 246, 1, 186, 1, 4397, 0 },
1483	{ 504, 1, 186, 1, 4398, 0 },	1483	{ 504, 1, 186, 1, 4398, 0 },
1484	{ 705, 1, 186, 1, 4399, 0 },	1484	{ 705, 1, 186, 1, 4399, 0 },
1485	{ 895, 1, 186, 1, 4400, 0 },	1485	{ 895, 1, 186, 1, 4400, 0 },
1486	{ 1490, 1, 186, 1, 4401, 0 },	1486	{ 1490, 1, 186, 1, 4401, 0 },
1487	{ 1656, 1, 186, 1, 4402, 0 },	1487	{ 1656, 1, 186, 1, 4402, 0 },
1488	{ 1818, 1, 186, 1, 4403, 0 },	1488	{ 1818, 1, 186, 1, 4403, 0 },
1489	{ 1980, 1, 186, 1, 4404, 0 },	1489	{ 1980, 1, 186, 1, 4404, 0 },
1490	{ 1451, 4, 1, 0, 4119, 2 },	1490	{ 1451, 4, 1, 0, 4119, 2 },
1491	{ 249, 1, 184, 1, 4405, 0 },	1491	{ 249, 1, 184, 1, 4405, 0 },
1492	{ 507, 1, 184, 1, 4406, 0 },	1492	{ 507, 1, 184, 1, 4406, 0 },
1493	{ 708, 1, 184, 1, 4407, 0 },	1493	{ 708, 1, 184, 1, 4407, 0 },
1494	{ 898, 1, 184, 1, 4408, 0 },	1494	{ 898, 1, 184, 1, 4408, 0 },
1495	{ 1493, 1, 184, 1, 4409, 0 },	1495	{ 1493, 1, 184, 1, 4409, 0 },
1496	{ 1659, 1, 184, 1, 4410, 0 },	1496	{ 1659, 1, 184, 1, 4410, 0 },
1497	{ 1821, 1, 184, 1, 4411, 0 },	1497	{ 1821, 1, 184, 1, 4411, 0 },
1498	{ 1983, 1, 184, 1, 4412, 0 },	1498	{ 1983, 1, 184, 1, 4412, 0 },
1499	{ 2142, 1, 184, 1, 4413, 0 },	1499	{ 2142, 1, 184, 1, 4413, 0 },
1500	{ 2317, 1, 184, 1, 4414, 0 },	1500	{ 2317, 1, 184, 1, 4414, 0 },
1501	{ 252, 1, 184, 1, 4415, 0 },	1501	{ 252, 1, 184, 1, 4415, 0 },
1502	{ 510, 1, 184, 1, 4416, 0 },	1502	{ 510, 1, 184, 1, 4416, 0 },
1503	{ 255, 180, 1, 8, 729221, 10 },	1503	{ 255, 180, 1, 8, 729221, 10 },
1504	{ 513, 180, 1, 8, 729222, 10 },	1504	{ 513, 180, 1, 8, 729222, 10 },
1505	{ 711, 180, 1, 8, 729223, 10 },	1505	{ 711, 180, 1, 8, 729223, 10 },
1506	{ 901, 180, 1, 8, 729224, 10 },	1506	{ 901, 180, 1, 8, 729224, 10 },
1507	{ 1496, 180, 1, 8, 729225, 10 },	1507	{ 1496, 180, 1, 8, 729225, 10 },
1508	{ 1662, 180, 1, 8, 729226, 10 },	1508	{ 1662, 180, 1, 8, 729226, 10 },
1509	{ 1824, 180, 1, 8, 729227, 10 },	1509	{ 1824, 180, 1, 8, 729227, 10 },
1510	{ 1986, 180, 1, 8, 729228, 10 },	1510	{ 1986, 180, 1, 8, 729228, 10 },
1511	{ 2145, 180, 1, 8, 729229, 10 },	1511	{ 2145, 180, 1, 8, 729229, 10 },
1512	{ 2320, 180, 1, 8, 729230, 10 },	1512	{ 2320, 180, 1, 8, 729230, 10 },
1513	{ 60, 180, 1, 8, 729231, 10 },	1513	{ 60, 180, 1, 8, 729231, 10 },
1514	{ 318, 180, 1, 8, 729232, 10 },	1514	{ 318, 180, 1, 8, 729232, 10 },
1515	{ 576, 180, 1, 8, 729233, 10 },	1515	{ 576, 180, 1, 8, 729233, 10 },
1516	{ 774, 180, 1, 8, 729234, 10 },	1516	{ 774, 180, 1, 8, 729234, 10 },
1517	{ 964, 180, 1, 8, 729235, 10 },	1517	{ 964, 180, 1, 8, 729235, 10 },
1518	{ 1559, 180, 1, 8, 729236, 10 },	1518	{ 1559, 180, 1, 8, 729236, 10 },
1519	{ 1721, 180, 1, 8, 729237, 10 },	1519	{ 1721, 180, 1, 8, 729237, 10 },
1520	{ 1883, 180, 1, 8, 729238, 10 },	1520	{ 1883, 180, 1, 8, 729238, 10 },
1521	{ 2045, 180, 1, 8, 729239, 10 },	1521	{ 2045, 180, 1, 8, 729239, 10 },
1522	{ 2204, 180, 1, 8, 729240, 10 },	1522	{ 2204, 180, 1, 8, 729240, 10 },
1523	{ 120, 180, 1, 8, 729241, 10 },	1523	{ 120, 180, 1, 8, 729241, 10 },
1524	{ 378, 180, 1, 8, 729242, 10 },	1524	{ 378, 180, 1, 8, 729242, 10 },
1525	{ 636, 180, 1, 8, 729243, 10 },	1525	{ 636, 180, 1, 8, 729243, 10 },
1526	{ 834, 180, 1, 8, 729244, 10 },	1526	{ 834, 180, 1, 8, 729244, 10 },
1527	{ 1024, 180, 1, 8, 729245, 10 },	1527	{ 1024, 180, 1, 8, 729245, 10 },
1528	{ 1619, 180, 1, 8, 729246, 10 },	1528	{ 1619, 180, 1, 8, 729246, 10 },
1529	{ 1781, 180, 1, 8, 729247, 10 },	1529	{ 1781, 180, 1, 8, 729247, 10 },
1530	{ 1943, 180, 1, 8, 729248, 10 },	1530	{ 1943, 180, 1, 8, 729248, 10 },
1531	{ 2105, 180, 1, 8, 729249, 10 },	1531	{ 2105, 180, 1, 8, 729249, 10 },
1532	{ 2280, 180, 1, 8, 729250, 10 },	1532	{ 2280, 180, 1, 8, 729250, 10 },
1533	{ 193, 180, 1, 8, 729251, 10 },	1533	{ 193, 180, 1, 8, 729251, 10 },
1534	{ 451, 180, 1, 8, 729252, 10 },	1534	{ 451, 180, 1, 8, 729252, 10 },
1535	{ 1431, 2, 1, 0, 4120, 2 },	1535	{ 1431, 2, 1, 0, 4120, 2 },
1536	{ 1055, 2, 1, 0, 4121, 2 },	1536	{ 1055, 2, 1, 0, 4121, 2 },
1537	{ 1133, 2, 1, 0, 4122, 2 },	1537	{ 1133, 2, 1, 0, 4122, 2 },
1538	{ 1183, 2, 1, 0, 4123, 2 },	1538	{ 1183, 2, 1, 0, 4123, 2 },
1539	{ 1221, 2, 1, 0, 4124, 2 },	1539	{ 1221, 2, 1, 0, 4124, 2 },
1540	{ 1061, 12, 1, 12, 495645, 10 },	1540	{ 1061, 12, 1, 12, 495645, 10 },
1541	{ 1068, 181, 37, 9, 729221, 10 },	1541	{ 1068, 181, 37, 9, 729221, 10 },
1542	{ 1139, 181, 37, 9, 729222, 10 },	1542	{ 1139, 181, 37, 9, 729222, 10 },
1543	{ 1189, 181, 37, 9, 729223, 10 },	1543	{ 1189, 181, 37, 9, 729223, 10 },
1544	{ 1227, 181, 37, 9, 729224, 10 },	1544	{ 1227, 181, 37, 9, 729224, 10 },
1545	{ 1259, 181, 37, 9, 729225, 10 },	1545	{ 1259, 181, 37, 9, 729225, 10 },
1546	{ 1291, 181, 37, 9, 729226, 10 },	1546	{ 1291, 181, 37, 9, 729226, 10 },
1547	{ 1323, 181, 37, 9, 729227, 10 },	1547	{ 1323, 181, 37, 9, 729227, 10 },
1548	{ 1355, 181, 37, 9, 729228, 10 },	1548	{ 1355, 181, 37, 9, 729228, 10 },
1549	{ 1387, 181, 37, 9, 729229, 10 },	1549	{ 1387, 181, 37, 9, 729229, 10 },
1550	{ 1413, 181, 37, 9, 729230, 10 },	1550	{ 1413, 181, 37, 9, 729230, 10 },
1551	{ 1034, 181, 37, 9, 729231, 10 },	1551	{ 1034, 181, 37, 9, 729231, 10 },
1552	{ 1112, 181, 37, 9, 729232, 10 },	1552	{ 1112, 181, 37, 9, 729232, 10 },
1553	{ 1169, 181, 37, 9, 729233, 10 },	1553	{ 1169, 181, 37, 9, 729233, 10 },
1554	{ 1207, 181, 37, 9, 729234, 10 },	1554	{ 1207, 181, 37, 9, 729234, 10 },
1555	{ 1245, 181, 37, 9, 729235, 10 },	1555	{ 1245, 181, 37, 9, 729235, 10 },
1556	{ 1277, 181, 37, 9, 729236, 10 },	1556	{ 1277, 181, 37, 9, 729236, 10 },
1557	{ 1309, 181, 37, 9, 729237, 10 },	1557	{ 1309, 181, 37, 9, 729237, 10 },
1558	{ 1341, 181, 37, 9, 729238, 10 },	1558	{ 1341, 181, 37, 9, 729238, 10 },
1559	{ 1373, 181, 37, 9, 729239, 10 },	1559	{ 1373, 181, 37, 9, 729239, 10 },
1560	{ 1399, 181, 37, 9, 729240, 10 },	1560	{ 1399, 181, 37, 9, 729240, 10 },
1561	{ 1041, 181, 37, 9, 729241, 10 },	1561	{ 1041, 181, 37, 9, 729241, 10 },
1562	{ 1119, 181, 37, 9, 729242, 10 },	1562	{ 1119, 181, 37, 9, 729242, 10 },
1563	{ 1176, 181, 37, 9, 729243, 10 },	1563	{ 1176, 181, 37, 9, 729243, 10 },
1564	{ 1214, 181, 37, 9, 729244, 10 },	1564	{ 1214, 181, 37, 9, 729244, 10 },
1565	{ 1252, 181, 37, 9, 729245, 10 },	1565	{ 1252, 181, 37, 9, 729245, 10 },
1566	{ 1284, 181, 37, 9, 729246, 10 },	1566	{ 1284, 181, 37, 9, 729246, 10 },
1567	{ 1316, 181, 37, 9, 729247, 10 },	1567	{ 1316, 181, 37, 9, 729247, 10 },
1568	{ 1348, 181, 37, 9, 729248, 10 },	1568	{ 1348, 181, 37, 9, 729248, 10 },
1569	{ 1380, 181, 37, 9, 729249, 10 },	1569	{ 1380, 181, 37, 9, 729249, 10 },
1570	{ 1406, 181, 37, 9, 729250, 10 },	1570	{ 1406, 181, 37, 9, 729250, 10 },
1571	{ 1048, 181, 37, 9, 729251, 10 },	1571	{ 1048, 181, 37, 9, 729251, 10 },
1572	{ 1126, 181, 37, 9, 729252, 10 },	1572	{ 1126, 181, 37, 9, 729252, 10 },
1573	{ 2208, 1, 0, 1, 4100, 0 },	1573	{ 2208, 1, 0, 1, 4100, 0 },
1574	{ 1074, 20, 113, 0, 4126, 2 },	1574	{ 1074, 20, 113, 0, 4126, 2 },
1575	{ 1081, 30, 1, 0, 4365, 2 },	1575	{ 1081, 30, 1, 0, 4365, 2 },
1576	{ 1145, 30, 1, 0, 4366, 2 },	1576	{ 1145, 30, 1, 0, 4366, 2 },
1577	{ 1087, 30, 109, 0, 4125, 2 },	1577	{ 1087, 30, 109, 0, 4125, 2 },
1578	{ 1094, 32, 1, 0, 4397, 2 },	1578	{ 1094, 32, 1, 0, 4397, 2 },
1579	{ 1151, 32, 1, 0, 4398, 2 },	1579	{ 1151, 32, 1, 0, 4398, 2 },
1580	{ 1195, 32, 1, 0, 4399, 2 },	1580	{ 1195, 32, 1, 0, 4399, 2 },
1581	{ 1233, 32, 1, 0, 4400, 2 },	1581	{ 1233, 32, 1, 0, 4400, 2 },
1582	{ 1265, 32, 1, 0, 4401, 2 },	1582	{ 1265, 32, 1, 0, 4401, 2 },
1583	{ 1297, 32, 1, 0, 4402, 2 },	1583	{ 1297, 32, 1, 0, 4402, 2 },
1584	{ 1329, 32, 1, 0, 4403, 2 },	1584	{ 1329, 32, 1, 0, 4403, 2 },
1585	{ 1361, 32, 1, 0, 4404, 2 },	1585	{ 1361, 32, 1, 0, 4404, 2 },
1586	{ 1100, 34, 1, 0, 4405, 2 },	1586	{ 1100, 34, 1, 0, 4405, 2 },
1587	{ 1157, 34, 1, 0, 4406, 2 },	1587	{ 1157, 34, 1, 0, 4406, 2 },
1588	{ 1201, 34, 1, 0, 4407, 2 },	1588	{ 1201, 34, 1, 0, 4407, 2 },
1589	{ 1239, 34, 1, 0, 4408, 2 },	1589	{ 1239, 34, 1, 0, 4408, 2 },
1590	{ 1271, 34, 1, 0, 4409, 2 },	1590	{ 1271, 34, 1, 0, 4409, 2 },
1591	{ 1303, 34, 1, 0, 4410, 2 },	1591	{ 1303, 34, 1, 0, 4410, 2 },
1592	{ 1335, 34, 1, 0, 4411, 2 },	1592	{ 1335, 34, 1, 0, 4411, 2 },
1593	{ 1367, 34, 1, 0, 4412, 2 },	1593	{ 1367, 34, 1, 0, 4412, 2 },
1594	{ 1393, 34, 1, 0, 4413, 2 },	1594	{ 1393, 34, 1, 0, 4413, 2 },
1595	{ 1419, 34, 1, 0, 4414, 2 },	1595	{ 1419, 34, 1, 0, 4414, 2 },
1596	{ 1106, 34, 1, 0, 4415, 2 },	1596	{ 1106, 34, 1, 0, 4415, 2 },
1597	{ 1163, 34, 1, 0, 4416, 2 },	1597	{ 1163, 34, 1, 0, 4416, 2 },
1598	};	1598	};
1599		1599
1600	extern const MCPhysReg MipsRegUnitRoots[][2] = {	1600	extern const MCPhysReg MipsRegUnitRoots[][2] = {
1601	{ Mips::AT },	1601	{ Mips::AT },
1602	{ Mips::DSPCCond },	1602	{ Mips::DSPCCond },
1603	{ Mips::DSPCarry },	1603	{ Mips::DSPCarry },
1604	{ Mips::DSPEFI },	1604	{ Mips::DSPEFI },
1605	{ Mips::DSPOutFlag16_19 },	1605	{ Mips::DSPOutFlag16_19 },
1606	{ Mips::DSPOutFlag20 },	1606	{ Mips::DSPOutFlag20 },
1607	{ Mips::DSPOutFlag21 },	1607	{ Mips::DSPOutFlag21 },
1608	{ Mips::DSPOutFlag22 },	1608	{ Mips::DSPOutFlag22 },
1609	{ Mips::DSPOutFlag23 },	1609	{ Mips::DSPOutFlag23 },
1610	{ Mips::DSPPos },	1610	{ Mips::DSPPos },
1611	{ Mips::DSPSCount },	1611	{ Mips::DSPSCount },
1612	{ Mips::FP },	1612	{ Mips::FP },
1613	{ Mips::GP },	1613	{ Mips::GP },
1614	{ Mips::MSAAccess },	1614	{ Mips::MSAAccess },
1615	{ Mips::MSACSR },	1615	{ Mips::MSACSR },
1616	{ Mips::MSAIR },	1616	{ Mips::MSAIR },
1617	{ Mips::MSAMap },	1617	{ Mips::MSAMap },
1618	{ Mips::MSAModify },	1618	{ Mips::MSAModify },
1619	{ Mips::MSARequest },	1619	{ Mips::MSARequest },
1620	{ Mips::MSASave },	1620	{ Mips::MSASave },
1621	{ Mips::MSAUnmap },	1621	{ Mips::MSAUnmap },
1622	{ Mips::PC },	1622	{ Mips::PC },
1623	{ Mips::RA },	1623	{ Mips::RA },
1624	{ Mips::SP },	1624	{ Mips::SP },
1625	{ Mips::ZERO },	1625	{ Mips::ZERO },
1626	{ Mips::A0 },	1626	{ Mips::A0 },
1627	{ Mips::A1 },	1627	{ Mips::A1 },
1628	{ Mips::A2 },	1628	{ Mips::A2 },
1629	{ Mips::A3 },	1629	{ Mips::A3 },
1630	{ Mips::LO0 },	1630	{ Mips::LO0 },
1631	{ Mips::HI0 },	1631	{ Mips::HI0 },
1632	{ Mips::LO1 },	1632	{ Mips::LO1 },
1633	{ Mips::HI1 },	1633	{ Mips::HI1 },
1634	{ Mips::LO2 },	1634	{ Mips::LO2 },
1635	{ Mips::HI2 },	1635	{ Mips::HI2 },
1636	{ Mips::LO3 },	1636	{ Mips::LO3 },
1637	{ Mips::HI3 },	1637	{ Mips::HI3 },
1638	{ Mips::COP00 },	1638	{ Mips::COP00 },
1639	{ Mips::COP01 },	1639	{ Mips::COP01 },
1640	{ Mips::COP02 },	1640	{ Mips::COP02 },
1641	{ Mips::COP03 },	1641	{ Mips::COP03 },
1642	{ Mips::COP04 },	1642	{ Mips::COP04 },
1643	{ Mips::COP05 },	1643	{ Mips::COP05 },
1644	{ Mips::COP06 },	1644	{ Mips::COP06 },
1645	{ Mips::COP07 },	1645	{ Mips::COP07 },
1646	{ Mips::COP08 },	1646	{ Mips::COP08 },
1647	{ Mips::COP09 },	1647	{ Mips::COP09 },
1648	{ Mips::COP20 },	1648	{ Mips::COP20 },
1649	{ Mips::COP21 },	1649	{ Mips::COP21 },
1650	{ Mips::COP22 },	1650	{ Mips::COP22 },
1651	{ Mips::COP23 },	1651	{ Mips::COP23 },
1652	{ Mips::COP24 },	1652	{ Mips::COP24 },
1653	{ Mips::COP25 },	1653	{ Mips::COP25 },
1654	{ Mips::COP26 },	1654	{ Mips::COP26 },
1655	{ Mips::COP27 },	1655	{ Mips::COP27 },
1656	{ Mips::COP28 },	1656	{ Mips::COP28 },
1657	{ Mips::COP29 },	1657	{ Mips::COP29 },
1658	{ Mips::COP30 },	1658	{ Mips::COP30 },
1659	{ Mips::COP31 },	1659	{ Mips::COP31 },
1660	{ Mips::COP32 },	1660	{ Mips::COP32 },
1661	{ Mips::COP33 },	1661	{ Mips::COP33 },
1662	{ Mips::COP34 },	1662	{ Mips::COP34 },
1663	{ Mips::COP35 },	1663	{ Mips::COP35 },
1664	{ Mips::COP36 },	1664	{ Mips::COP36 },
1665	{ Mips::COP37 },	1665	{ Mips::COP37 },
1666	{ Mips::COP38 },	1666	{ Mips::COP38 },
1667	{ Mips::COP39 },	1667	{ Mips::COP39 },
1668	{ Mips::COP010 },	1668	{ Mips::COP010 },
1669	{ Mips::COP011 },	1669	{ Mips::COP011 },
1670	{ Mips::COP012 },	1670	{ Mips::COP012 },
1671	{ Mips::COP013 },	1671	{ Mips::COP013 },
1672	{ Mips::COP014 },	1672	{ Mips::COP014 },
1673	{ Mips::COP015 },	1673	{ Mips::COP015 },
1674	{ Mips::COP016 },	1674	{ Mips::COP016 },
1675	{ Mips::COP017 },	1675	{ Mips::COP017 },
1676	{ Mips::COP018 },	1676	{ Mips::COP018 },
1677	{ Mips::COP019 },	1677	{ Mips::COP019 },
1678	{ Mips::COP020 },	1678	{ Mips::COP020 },
1679	{ Mips::COP021 },	1679	{ Mips::COP021 },
1680	{ Mips::COP022 },	1680	{ Mips::COP022 },
1681	{ Mips::COP023 },	1681	{ Mips::COP023 },
1682	{ Mips::COP024 },	1682	{ Mips::COP024 },
1683	{ Mips::COP025 },	1683	{ Mips::COP025 },
1684	{ Mips::COP026 },	1684	{ Mips::COP026 },
1685	{ Mips::COP027 },	1685	{ Mips::COP027 },
1686	{ Mips::COP028 },	1686	{ Mips::COP028 },
1687	{ Mips::COP029 },	1687	{ Mips::COP029 },
1688	{ Mips::COP030 },	1688	{ Mips::COP030 },
1689	{ Mips::COP031 },	1689	{ Mips::COP031 },
1690	{ Mips::COP210 },	1690	{ Mips::COP210 },
1691	{ Mips::COP211 },	1691	{ Mips::COP211 },
1692	{ Mips::COP212 },	1692	{ Mips::COP212 },
1693	{ Mips::COP213 },	1693	{ Mips::COP213 },
1694	{ Mips::COP214 },	1694	{ Mips::COP214 },
1695	{ Mips::COP215 },	1695	{ Mips::COP215 },
1696	{ Mips::COP216 },	1696	{ Mips::COP216 },
1697	{ Mips::COP217 },	1697	{ Mips::COP217 },
1698	{ Mips::COP218 },	1698	{ Mips::COP218 },
1699	{ Mips::COP219 },	1699	{ Mips::COP219 },
1700	{ Mips::COP220 },	1700	{ Mips::COP220 },
1701	{ Mips::COP221 },	1701	{ Mips::COP221 },
1702	{ Mips::COP222 },	1702	{ Mips::COP222 },
1703	{ Mips::COP223 },	1703	{ Mips::COP223 },
1704	{ Mips::COP224 },	1704	{ Mips::COP224 },
1705	{ Mips::COP225 },	1705	{ Mips::COP225 },
1706	{ Mips::COP226 },	1706	{ Mips::COP226 },
1707	{ Mips::COP227 },	1707	{ Mips::COP227 },
1708	{ Mips::COP228 },	1708	{ Mips::COP228 },
1709	{ Mips::COP229 },	1709	{ Mips::COP229 },
1710	{ Mips::COP230 },	1710	{ Mips::COP230 },
1711	{ Mips::COP231 },	1711	{ Mips::COP231 },
1712	{ Mips::COP310 },	1712	{ Mips::COP310 },
1713	{ Mips::COP311 },	1713	{ Mips::COP311 },
1714	{ Mips::COP312 },	1714	{ Mips::COP312 },
1715	{ Mips::COP313 },	1715	{ Mips::COP313 },
1716	{ Mips::COP314 },	1716	{ Mips::COP314 },
1717	{ Mips::COP315 },	1717	{ Mips::COP315 },
1718	{ Mips::COP316 },	1718	{ Mips::COP316 },
1719	{ Mips::COP317 },	1719	{ Mips::COP317 },
1720	{ Mips::COP318 },	1720	{ Mips::COP318 },
1721	{ Mips::COP319 },	1721	{ Mips::COP319 },
1722	{ Mips::COP320 },	1722	{ Mips::COP320 },
1723	{ Mips::COP321 },	1723	{ Mips::COP321 },
1724	{ Mips::COP322 },	1724	{ Mips::COP322 },
1725	{ Mips::COP323 },	1725	{ Mips::COP323 },
1726	{ Mips::COP324 },	1726	{ Mips::COP324 },
1727	{ Mips::COP325 },	1727	{ Mips::COP325 },
1728	{ Mips::COP326 },	1728	{ Mips::COP326 },
1729	{ Mips::COP327 },	1729	{ Mips::COP327 },
1730	{ Mips::COP328 },	1730	{ Mips::COP328 },
1731	{ Mips::COP329 },	1731	{ Mips::COP329 },
1732	{ Mips::COP330 },	1732	{ Mips::COP330 },
1733	{ Mips::COP331 },	1733	{ Mips::COP331 },
1734	{ Mips::F0 },	1734	{ Mips::F0 },
1735	{ Mips::F1 },	1735	{ Mips::F1 },
1736	{ Mips::F2 },	1736	{ Mips::F2 },
1737	{ Mips::F3 },	1737	{ Mips::F3 },
1738	{ Mips::F4 },	1738	{ Mips::F4 },
1739	{ Mips::F5 },	1739	{ Mips::F5 },
1740	{ Mips::F6 },	1740	{ Mips::F6 },
1741	{ Mips::F7 },	1741	{ Mips::F7 },
1742	{ Mips::F8 },	1742	{ Mips::F8 },
1743	{ Mips::F9 },	1743	{ Mips::F9 },
1744	{ Mips::F10 },	1744	{ Mips::F10 },
1745	{ Mips::F11 },	1745	{ Mips::F11 },
1746	{ Mips::F12 },	1746	{ Mips::F12 },
1747	{ Mips::F13 },	1747	{ Mips::F13 },
1748	{ Mips::F14 },	1748	{ Mips::F14 },
1749	{ Mips::F15 },	1749	{ Mips::F15 },
1750	{ Mips::F16 },	1750	{ Mips::F16 },
1751	{ Mips::F17 },	1751	{ Mips::F17 },
1752	{ Mips::F18 },	1752	{ Mips::F18 },
1753	{ Mips::F19 },	1753	{ Mips::F19 },
1754	{ Mips::F20 },	1754	{ Mips::F20 },
1755	{ Mips::F21 },	1755	{ Mips::F21 },
1756	{ Mips::F22 },	1756	{ Mips::F22 },
1757	{ Mips::F23 },	1757	{ Mips::F23 },
1758	{ Mips::F24 },	1758	{ Mips::F24 },
1759	{ Mips::F25 },	1759	{ Mips::F25 },
1760	{ Mips::F26 },	1760	{ Mips::F26 },
1761	{ Mips::F27 },	1761	{ Mips::F27 },
1762	{ Mips::F28 },	1762	{ Mips::F28 },
1763	{ Mips::F29 },	1763	{ Mips::F29 },
1764	{ Mips::F30 },	1764	{ Mips::F30 },
1765	{ Mips::F31 },	1765	{ Mips::F31 },
1766	{ Mips::FCC0 },	1766	{ Mips::FCC0 },
1767	{ Mips::FCC1 },	1767	{ Mips::FCC1 },
1768	{ Mips::FCC2 },	1768	{ Mips::FCC2 },
1769	{ Mips::FCC3 },	1769	{ Mips::FCC3 },
1770	{ Mips::FCC4 },	1770	{ Mips::FCC4 },
1771	{ Mips::FCC5 },	1771	{ Mips::FCC5 },
1772	{ Mips::FCC6 },	1772	{ Mips::FCC6 },
1773	{ Mips::FCC7 },	1773	{ Mips::FCC7 },
1774	{ Mips::FCR0 },	1774	{ Mips::FCR0 },
1775	{ Mips::FCR1 },	1775	{ Mips::FCR1 },
1776	{ Mips::FCR2 },	1776	{ Mips::FCR2 },
1777	{ Mips::FCR3 },	1777	{ Mips::FCR3 },
1778	{ Mips::FCR4 },	1778	{ Mips::FCR4 },
1779	{ Mips::FCR5 },	1779	{ Mips::FCR5 },
1780	{ Mips::FCR6 },	1780	{ Mips::FCR6 },
1781	{ Mips::FCR7 },	1781	{ Mips::FCR7 },
1782	{ Mips::FCR8 },	1782	{ Mips::FCR8 },
1783	{ Mips::FCR9 },	1783	{ Mips::FCR9 },
1784	{ Mips::FCR10 },	1784	{ Mips::FCR10 },
1785	{ Mips::FCR11 },	1785	{ Mips::FCR11 },
1786	{ Mips::FCR12 },	1786	{ Mips::FCR12 },
1787	{ Mips::FCR13 },	1787	{ Mips::FCR13 },
1788	{ Mips::FCR14 },	1788	{ Mips::FCR14 },
1789	{ Mips::FCR15 },	1789	{ Mips::FCR15 },
1790	{ Mips::FCR16 },	1790	{ Mips::FCR16 },
1791	{ Mips::FCR17 },	1791	{ Mips::FCR17 },
1792	{ Mips::FCR18 },	1792	{ Mips::FCR18 },
1793	{ Mips::FCR19 },	1793	{ Mips::FCR19 },
1794	{ Mips::FCR20 },	1794	{ Mips::FCR20 },
1795	{ Mips::FCR21 },	1795	{ Mips::FCR21 },
1796	{ Mips::FCR22 },	1796	{ Mips::FCR22 },
1797	{ Mips::FCR23 },	1797	{ Mips::FCR23 },
1798	{ Mips::FCR24 },	1798	{ Mips::FCR24 },
1799	{ Mips::FCR25 },	1799	{ Mips::FCR25 },
1800	{ Mips::FCR26 },	1800	{ Mips::FCR26 },
1801	{ Mips::FCR27 },	1801	{ Mips::FCR27 },
1802	{ Mips::FCR28 },	1802	{ Mips::FCR28 },
1803	{ Mips::FCR29 },	1803	{ Mips::FCR29 },
1804	{ Mips::FCR30 },	1804	{ Mips::FCR30 },
1805	{ Mips::FCR31 },	1805	{ Mips::FCR31 },
1806	{ Mips::F_HI0 },	1806	{ Mips::F_HI0 },
1807	{ Mips::F_HI1 },	1807	{ Mips::F_HI1 },
1808	{ Mips::F_HI2 },	1808	{ Mips::F_HI2 },
1809	{ Mips::F_HI3 },	1809	{ Mips::F_HI3 },
1810	{ Mips::F_HI4 },	1810	{ Mips::F_HI4 },
1811	{ Mips::F_HI5 },	1811	{ Mips::F_HI5 },
1812	{ Mips::F_HI6 },	1812	{ Mips::F_HI6 },
1813	{ Mips::F_HI7 },	1813	{ Mips::F_HI7 },
1814	{ Mips::F_HI8 },	1814	{ Mips::F_HI8 },
1815	{ Mips::F_HI9 },	1815	{ Mips::F_HI9 },
1816	{ Mips::F_HI10 },	1816	{ Mips::F_HI10 },
1817	{ Mips::F_HI11 },	1817	{ Mips::F_HI11 },
1818	{ Mips::F_HI12 },	1818	{ Mips::F_HI12 },
1819	{ Mips::F_HI13 },	1819	{ Mips::F_HI13 },
1820	{ Mips::F_HI14 },	1820	{ Mips::F_HI14 },
1821	{ Mips::F_HI15 },	1821	{ Mips::F_HI15 },
1822	{ Mips::F_HI16 },	1822	{ Mips::F_HI16 },
1823	{ Mips::F_HI17 },	1823	{ Mips::F_HI17 },
1824	{ Mips::F_HI18 },	1824	{ Mips::F_HI18 },
1825	{ Mips::F_HI19 },	1825	{ Mips::F_HI19 },
1826	{ Mips::F_HI20 },	1826	{ Mips::F_HI20 },
1827	{ Mips::F_HI21 },	1827	{ Mips::F_HI21 },
1828	{ Mips::F_HI22 },	1828	{ Mips::F_HI22 },
1829	{ Mips::F_HI23 },	1829	{ Mips::F_HI23 },
1830	{ Mips::F_HI24 },	1830	{ Mips::F_HI24 },
1831	{ Mips::F_HI25 },	1831	{ Mips::F_HI25 },
1832	{ Mips::F_HI26 },	1832	{ Mips::F_HI26 },
1833	{ Mips::F_HI27 },	1833	{ Mips::F_HI27 },
1834	{ Mips::F_HI28 },	1834	{ Mips::F_HI28 },
1835	{ Mips::F_HI29 },	1835	{ Mips::F_HI29 },
1836	{ Mips::F_HI30 },	1836	{ Mips::F_HI30 },
1837	{ Mips::F_HI31 },	1837	{ Mips::F_HI31 },
1838	{ Mips::HWR0 },	1838	{ Mips::HWR0 },
1839	{ Mips::HWR1 },	1839	{ Mips::HWR1 },
1840	{ Mips::HWR2 },	1840	{ Mips::HWR2 },
1841	{ Mips::HWR3 },	1841	{ Mips::HWR3 },
1842	{ Mips::HWR4 },	1842	{ Mips::HWR4 },
1843	{ Mips::HWR5 },	1843	{ Mips::HWR5 },
1844	{ Mips::HWR6 },	1844	{ Mips::HWR6 },
1845	{ Mips::HWR7 },	1845	{ Mips::HWR7 },
1846	{ Mips::HWR8 },	1846	{ Mips::HWR8 },
1847	{ Mips::HWR9 },	1847	{ Mips::HWR9 },
1848	{ Mips::HWR10 },	1848	{ Mips::HWR10 },
1849	{ Mips::HWR11 },	1849	{ Mips::HWR11 },
1850	{ Mips::HWR12 },	1850	{ Mips::HWR12 },
1851	{ Mips::HWR13 },	1851	{ Mips::HWR13 },
1852	{ Mips::HWR14 },	1852	{ Mips::HWR14 },
1853	{ Mips::HWR15 },	1853	{ Mips::HWR15 },
1854	{ Mips::HWR16 },	1854	{ Mips::HWR16 },
1855	{ Mips::HWR17 },	1855	{ Mips::HWR17 },
1856	{ Mips::HWR18 },	1856	{ Mips::HWR18 },
1857	{ Mips::HWR19 },	1857	{ Mips::HWR19 },
1858	{ Mips::HWR20 },	1858	{ Mips::HWR20 },
1859	{ Mips::HWR21 },	1859	{ Mips::HWR21 },
1860	{ Mips::HWR22 },	1860	{ Mips::HWR22 },
1861	{ Mips::HWR23 },	1861	{ Mips::HWR23 },
1862	{ Mips::HWR24 },	1862	{ Mips::HWR24 },
1863	{ Mips::HWR25 },	1863	{ Mips::HWR25 },
1864	{ Mips::HWR26 },	1864	{ Mips::HWR26 },
1865	{ Mips::HWR27 },	1865	{ Mips::HWR27 },
1866	{ Mips::HWR28 },	1866	{ Mips::HWR28 },
1867	{ Mips::HWR29 },	1867	{ Mips::HWR29 },
1868	{ Mips::HWR30 },	1868	{ Mips::HWR30 },
1869	{ Mips::HWR31 },	1869	{ Mips::HWR31 },
1870	{ Mips::K0 },	1870	{ Mips::K0 },
1871	{ Mips::K1 },	1871	{ Mips::K1 },
1872	{ Mips::MPL0 },	1872	{ Mips::MPL0 },
1873	{ Mips::MPL1 },	1873	{ Mips::MPL1 },
1874	{ Mips::MPL2 },	1874	{ Mips::MPL2 },
1875	{ Mips::MSA8 },	1875	{ Mips::MSA8 },
1876	{ Mips::MSA9 },	1876	{ Mips::MSA9 },
1877	{ Mips::MSA10 },	1877	{ Mips::MSA10 },
1878	{ Mips::MSA11 },	1878	{ Mips::MSA11 },
1879	{ Mips::MSA12 },	1879	{ Mips::MSA12 },
1880	{ Mips::MSA13 },	1880	{ Mips::MSA13 },
1881	{ Mips::MSA14 },	1881	{ Mips::MSA14 },
1882	{ Mips::MSA15 },	1882	{ Mips::MSA15 },
1883	{ Mips::MSA16 },	1883	{ Mips::MSA16 },
1884	{ Mips::MSA17 },	1884	{ Mips::MSA17 },
1885	{ Mips::MSA18 },	1885	{ Mips::MSA18 },
1886	{ Mips::MSA19 },	1886	{ Mips::MSA19 },
1887	{ Mips::MSA20 },	1887	{ Mips::MSA20 },
1888	{ Mips::MSA21 },	1888	{ Mips::MSA21 },
1889	{ Mips::MSA22 },	1889	{ Mips::MSA22 },
1890	{ Mips::MSA23 },	1890	{ Mips::MSA23 },
1891	{ Mips::MSA24 },	1891	{ Mips::MSA24 },
1892	{ Mips::MSA25 },	1892	{ Mips::MSA25 },
1893	{ Mips::MSA26 },	1893	{ Mips::MSA26 },
1894	{ Mips::MSA27 },	1894	{ Mips::MSA27 },
1895	{ Mips::MSA28 },	1895	{ Mips::MSA28 },
1896	{ Mips::MSA29 },	1896	{ Mips::MSA29 },
1897	{ Mips::MSA30 },	1897	{ Mips::MSA30 },
1898	{ Mips::MSA31 },	1898	{ Mips::MSA31 },
1899	{ Mips::P0 },	1899	{ Mips::P0 },
1900	{ Mips::P1 },	1900	{ Mips::P1 },
1901	{ Mips::P2 },	1901	{ Mips::P2 },
1902	{ Mips::S0 },	1902	{ Mips::S0 },
1903	{ Mips::S1 },	1903	{ Mips::S1 },
1904	{ Mips::S2 },	1904	{ Mips::S2 },
1905	{ Mips::S3 },	1905	{ Mips::S3 },
1906	{ Mips::S4 },	1906	{ Mips::S4 },
1907	{ Mips::S5 },	1907	{ Mips::S5 },
1908	{ Mips::S6 },	1908	{ Mips::S6 },
1909	{ Mips::S7 },	1909	{ Mips::S7 },
1910	{ Mips::T0 },	1910	{ Mips::T0 },
1911	{ Mips::T1 },	1911	{ Mips::T1 },
1912	{ Mips::T2 },	1912	{ Mips::T2 },
1913	{ Mips::T3 },	1913	{ Mips::T3 },
1914	{ Mips::T4 },	1914	{ Mips::T4 },
1915	{ Mips::T5 },	1915	{ Mips::T5 },
1916	{ Mips::T6 },	1916	{ Mips::T6 },
1917	{ Mips::T7 },	1917	{ Mips::T7 },
1918	{ Mips::T8 },	1918	{ Mips::T8 },
1919	{ Mips::T9 },	1919	{ Mips::T9 },
1920	{ Mips::V0 },	1920	{ Mips::V0 },
1921	{ Mips::V1 },	1921	{ Mips::V1 },
1922	};	1922	};
1923		1923
1924	namespace { // Register classes...	1924	namespace { // Register classes...
1925	// MSA128F16 Register Class...	1925	// MSA128F16 Register Class...
1926	const MCPhysReg MSA128F16[] = {	1926	const MCPhysReg MSA128F16[] = {
1927	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	1927	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
1928	};	1928	};
1929		1929
1930	// MSA128F16 Bit set.	1930	// MSA128F16 Bit set.
1931	const uint8_t MSA128F16Bits[] = {	1931	const uint8_t MSA128F16Bits[] = {
1932	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	1932	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1933	};	1933	};
1934		1934
1935	// CCR Register Class...	1935	// CCR Register Class...
1936	const MCPhysReg CCR[] = {	1936	const MCPhysReg CCR[] = {
1937	Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,	1937	Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
1938	};	1938	};
1939		1939
1940	// CCR Bit set.	1940	// CCR Bit set.
1941	const uint8_t CCRBits[] = {	1941	const uint8_t CCRBits[] = {
1942	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	1942	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1943	};	1943	};
1944		1944
1945	// COP0 Register Class...	1945	// COP0 Register Class...
1946	const MCPhysReg COP0[] = {	1946	const MCPhysReg COP0[] = {
1947	Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,	1947	Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
1948	};	1948	};
1949		1949
1950	// COP0 Bit set.	1950	// COP0 Bit set.
1951	const uint8_t COP0Bits[] = {	1951	const uint8_t COP0Bits[] = {
1952	0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,	1952	0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
1953	};	1953	};
1954		1954
1955	// COP2 Register Class...	1955	// COP2 Register Class...
1956	const MCPhysReg COP2[] = {	1956	const MCPhysReg COP2[] = {
1957	Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,	1957	Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
1958	};	1958	};
1959		1959
1960	// COP2 Bit set.	1960	// COP2 Bit set.
1961	const uint8_t COP2Bits[] = {	1961	const uint8_t COP2Bits[] = {
1962	0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,	1962	0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
1963	};	1963	};
1964		1964
1965	// COP3 Register Class...	1965	// COP3 Register Class...
1966	const MCPhysReg COP3[] = {	1966	const MCPhysReg COP3[] = {
1967	Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,	1967	Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
1968	};	1968	};
1969		1969
1970	// COP3 Bit set.	1970	// COP3 Bit set.
1971	const uint8_t COP3Bits[] = {	1971	const uint8_t COP3Bits[] = {
1972	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,	1972	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1973	};	1973	};
1974		1974
1975	// DSPR Register Class...	1975	// DSPR Register Class...
1976	const MCPhysReg DSPR[] = {	1976	const MCPhysReg DSPR[] = {
1977	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	1977	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
1978	};	1978	};
1979		1979
1980	// DSPR Bit set.	1980	// DSPR Bit set.
1981	const uint8_t DSPRBits[] = {	1981	const uint8_t DSPRBits[] = {
1982	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	1982	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
1983	};	1983	};
1984		1984
1985	// FGR32 Register Class...	1985	// FGR32 Register Class...
1986	const MCPhysReg FGR32[] = {	1986	const MCPhysReg FGR32[] = {
1987	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	1987	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1988	};	1988	};
1989		1989
1990	// FGR32 Bit set.	1990	// FGR32 Bit set.
1991	const uint8_t FGR32Bits[] = {	1991	const uint8_t FGR32Bits[] = {
1992	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	1992	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1993	};	1993	};
1994		1994
1995	// FGRCC Register Class...	1995	// FGRCC Register Class...
1996	const MCPhysReg FGRCC[] = {	1996	const MCPhysReg FGRCC[] = {
1997	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	1997	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
1998	};	1998	};
1999		1999
2000	// FGRCC Bit set.	2000	// FGRCC Bit set.
2001	const uint8_t FGRCCBits[] = {	2001	const uint8_t FGRCCBits[] = {
2002	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	2002	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2003	};	2003	};
2004		2004
2005	// GPR32 Register Class...	2005	// GPR32 Register Class...
2006	const MCPhysReg GPR32[] = {	2006	const MCPhysReg GPR32[] = {
2007	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	2007	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2008	};	2008	};
2009		2009
2010	// GPR32 Bit set.	2010	// GPR32 Bit set.
2011	const uint8_t GPR32Bits[] = {	2011	const uint8_t GPR32Bits[] = {
2012	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	2012	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2013	};	2013	};
2014		2014
2015	// HWRegs Register Class...	2015	// HWRegs Register Class...
2016	const MCPhysReg HWRegs[] = {	2016	const MCPhysReg HWRegs[] = {
2017	Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,	2017	Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
2018	};	2018	};
2019		2019
2020	// HWRegs Bit set.	2020	// HWRegs Bit set.
2021	const uint8_t HWRegsBits[] = {	2021	const uint8_t HWRegsBits[] = {
2022	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	2022	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2023	};	2023	};
2024		2024
2025	// MSACtrl Register Class...	2025	// MSACtrl Register Class...
2026	const MCPhysReg MSACtrl[] = {	2026	const MCPhysReg MSACtrl[] = {
2027	Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,	2027	Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,
2028	};	2028	};
2029		2029
2030	// MSACtrl Bit set.	2030	// MSACtrl Bit set.
2031	const uint8_t MSACtrlBits[] = {	2031	const uint8_t MSACtrlBits[] = {
2032	0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,	2032	0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,
2033	};	2033	};
2034		2034
2035	// GPR32NONZERO Register Class...	2035	// GPR32NONZERO Register Class...
2036	const MCPhysReg GPR32NONZERO[] = {	2036	const MCPhysReg GPR32NONZERO[] = {
2037	Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	2037	Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
2038	};	2038	};
2039		2039
2040	// GPR32NONZERO Bit set.	2040	// GPR32NONZERO Bit set.
2041	const uint8_t GPR32NONZEROBits[] = {	2041	const uint8_t GPR32NONZEROBits[] = {
2042	0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	2042	0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,
2043	};	2043	};
2044		2044
2045	// CPU16RegsPlusSP Register Class...	2045	// CPU16RegsPlusSP Register Class...
2046	const MCPhysReg CPU16RegsPlusSP[] = {	2046	const MCPhysReg CPU16RegsPlusSP[] = {
2047	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,	2047	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
2048	};	2048	};
2049		2049
2050	// CPU16RegsPlusSP Bit set.	2050	// CPU16RegsPlusSP Bit set.
2051	const uint8_t CPU16RegsPlusSPBits[] = {	2051	const uint8_t CPU16RegsPlusSPBits[] = {
2052	0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	2052	0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2053	};	2053	};
2054		2054
2055	// CPU16Regs Register Class...	2055	// CPU16Regs Register Class...
2056	const MCPhysReg CPU16Regs[] = {	2056	const MCPhysReg CPU16Regs[] = {
2057	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,	2057	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
2058	};	2058	};
2059		2059
2060	// CPU16Regs Bit set.	2060	// CPU16Regs Bit set.
2061	const uint8_t CPU16RegsBits[] = {	2061	const uint8_t CPU16RegsBits[] = {
2062	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	2062	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2063	};	2063	};
2064		2064
2065	// FCC Register Class...	2065	// FCC Register Class...
2066	const MCPhysReg FCC[] = {	2066	const MCPhysReg FCC[] = {
2067	Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,	2067	Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
2068	};	2068	};
2069		2069
2070	// FCC Bit set.	2070	// FCC Bit set.
2071	const uint8_t FCCBits[] = {	2071	const uint8_t FCCBits[] = {
2072	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,	2072	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
2073	};	2073	};
2074		2074
2075	// GPRMM16 Register Class...	2075	// GPRMM16 Register Class...
2076	const MCPhysReg GPRMM16[] = {	2076	const MCPhysReg GPRMM16[] = {
2077	Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	2077	Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2078	};	2078	};
2079		2079
2080	// GPRMM16 Bit set.	2080	// GPRMM16 Bit set.
2081	const uint8_t GPRMM16Bits[] = {	2081	const uint8_t GPRMM16Bits[] = {
2082	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	2082	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2083	};	2083	};
2084		2084
2085	// GPRMM16MoveP Register Class...	2085	// GPRMM16MoveP Register Class...
2086	const MCPhysReg GPRMM16MoveP[] = {	2086	const MCPhysReg GPRMM16MoveP[] = {
2087	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	2087	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2088	};	2088	};
2089		2089
2090	// GPRMM16MoveP Bit set.	2090	// GPRMM16MoveP Bit set.
2091	const uint8_t GPRMM16MovePBits[] = {	2091	const uint8_t GPRMM16MovePBits[] = {
2092	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	2092	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2093	};	2093	};
2094		2094
2095	// GPRMM16Zero Register Class...	2095	// GPRMM16Zero Register Class...
2096	const MCPhysReg GPRMM16Zero[] = {	2096	const MCPhysReg GPRMM16Zero[] = {
2097	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	2097	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2098	};	2098	};
2099		2099
2100	// GPRMM16Zero Bit set.	2100	// GPRMM16Zero Bit set.
2101	const uint8_t GPRMM16ZeroBits[] = {	2101	const uint8_t GPRMM16ZeroBits[] = {
2102	0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	2102	0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2103	};	2103	};
2104		2104
2105	// CPU16Regs_and_GPRMM16Zero Register Class...	2105	// CPU16Regs_and_GPRMM16Zero Register Class...
2106	const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {	2106	const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
2107	Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	2107	Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
2108	};	2108	};
2109		2109
2110	// CPU16Regs_and_GPRMM16Zero Bit set.	2110	// CPU16Regs_and_GPRMM16Zero Bit set.
2111	const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {	2111	const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
2112	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	2112	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2113	};	2113	};
2114		2114
2115	// GPR32NONZERO_and_GPRMM16MoveP Register Class...	2115	// GPR32NONZERO_and_GPRMM16MoveP Register Class...
2116	const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {	2116	const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
2117	Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	2117	Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
2118	};	2118	};
2119		2119
2120	// GPR32NONZERO_and_GPRMM16MoveP Bit set.	2120	// GPR32NONZERO_and_GPRMM16MoveP Bit set.
2121	const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {	2121	const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
2122	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	2122	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
2123	};	2123	};
2124		2124
2125	// GPRMM16MovePPairSecond Register Class...	2125	// GPRMM16MovePPairSecond Register Class...
2126	const MCPhysReg GPRMM16MovePPairSecond[] = {	2126	const MCPhysReg GPRMM16MovePPairSecond[] = {
2127	Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,	2127	Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,
2128	};	2128	};
2129		2129
2130	// GPRMM16MovePPairSecond Bit set.	2130	// GPRMM16MovePPairSecond Bit set.
2131	const uint8_t GPRMM16MovePPairSecondBits[] = {	2131	const uint8_t GPRMM16MovePPairSecondBits[] = {
2132	0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	2132	0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2133	};	2133	};
2134		2134
2135	// CPU16Regs_and_GPRMM16MoveP Register Class...	2135	// CPU16Regs_and_GPRMM16MoveP Register Class...
2136	const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {	2136	const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
2137	Mips::S1, Mips::V0, Mips::V1, Mips::S0,	2137	Mips::S1, Mips::V0, Mips::V1, Mips::S0,
2138	};	2138	};
2139		2139
2140	// CPU16Regs_and_GPRMM16MoveP Bit set.	2140	// CPU16Regs_and_GPRMM16MoveP Bit set.
2141	const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {	2141	const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
2142	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	2142	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
2143	};	2143	};
2144		2144
2145	// GPRMM16MoveP_and_GPRMM16Zero Register Class...	2145	// GPRMM16MoveP_and_GPRMM16Zero Register Class...
2146	const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {	2146	const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
2147	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,	2147	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
2148	};	2148	};
2149		2149
2150	// GPRMM16MoveP_and_GPRMM16Zero Bit set.	2150	// GPRMM16MoveP_and_GPRMM16Zero Bit set.
2151	const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	2151	const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2152	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	2152	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2153	};	2153	};
2154		2154
2155	// HI32DSP Register Class...	2155	// HI32DSP Register Class...
2156	const MCPhysReg HI32DSP[] = {	2156	const MCPhysReg HI32DSP[] = {
2157	Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,	2157	Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
2158	};	2158	};
2159		2159
2160	// HI32DSP Bit set.	2160	// HI32DSP Bit set.
2161	const uint8_t HI32DSPBits[] = {	2161	const uint8_t HI32DSPBits[] = {
2162	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,	2162	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
2163	};	2163	};
2164		2164
2165	// LO32DSP Register Class...	2165	// LO32DSP Register Class...
2166	const MCPhysReg LO32DSP[] = {	2166	const MCPhysReg LO32DSP[] = {
2167	Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,	2167	Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
2168	};	2168	};
2169		2169
2170	// LO32DSP Bit set.	2170	// LO32DSP Bit set.
2171	const uint8_t LO32DSPBits[] = {	2171	const uint8_t LO32DSPBits[] = {
2172	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,	2172	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
2173	};	2173	};
2174		2174
2175	// CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	2175	// CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2176	const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {	2176	const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2177	Mips::A1, Mips::A2, Mips::A3,	2177	Mips::A1, Mips::A2, Mips::A3,
2178	};	2178	};
2179		2179
2180	// CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	2180	// CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2181	const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	2181	const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2182	0x00, 0x00, 0x80, 0x03,	2182	0x00, 0x00, 0x80, 0x03,
2183	};	2183	};
2184		2184
2185	// GPRMM16MovePPairFirst Register Class...	2185	// GPRMM16MovePPairFirst Register Class...
2186	const MCPhysReg GPRMM16MovePPairFirst[] = {	2186	const MCPhysReg GPRMM16MovePPairFirst[] = {
2187	Mips::A0, Mips::A1, Mips::A2,	2187	Mips::A0, Mips::A1, Mips::A2,
2188	};	2188	};
2189		2189
2190	// GPRMM16MovePPairFirst Bit set.	2190	// GPRMM16MovePPairFirst Bit set.
2191	const uint8_t GPRMM16MovePPairFirstBits[] = {	2191	const uint8_t GPRMM16MovePPairFirstBits[] = {
2192	0x00, 0x00, 0xc0, 0x01,	2192	0x00, 0x00, 0xc0, 0x01,
2193	};	2193	};
2194		2194
2195	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	2195	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2196	const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	2196	const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2197	Mips::S1, Mips::V0, Mips::V1,	2197	Mips::S1, Mips::V0, Mips::V1,
2198	};	2198	};
2199		2199
2200	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	2200	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2201	const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	2201	const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2202	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	2202	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
2203	};	2203	};
2204		2204
2205	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	2205	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2206	const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	2206	const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2207	Mips::A1, Mips::A2,	2207	Mips::A1, Mips::A2,
2208	};	2208	};
2209		2209
2210	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	2210	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2211	const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	2211	const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2212	0x00, 0x00, 0x80, 0x01,	2212	0x00, 0x00, 0x80, 0x01,
2213	};	2213	};
2214		2214
2215	// CPURAReg Register Class...	2215	// CPURAReg Register Class...
2216	const MCPhysReg CPURAReg[] = {	2216	const MCPhysReg CPURAReg[] = {
2217	Mips::RA,	2217	Mips::RA,
2218	};	2218	};
2219		2219
2220	// CPURAReg Bit set.	2220	// CPURAReg Bit set.
2221	const uint8_t CPURARegBits[] = {	2221	const uint8_t CPURARegBits[] = {
2222	0x00, 0x00, 0x08,	2222	0x00, 0x00, 0x08,
2223	};	2223	};
2224		2224
2225	// CPUSPReg Register Class...	2225	// CPUSPReg Register Class...
2226	const MCPhysReg CPUSPReg[] = {	2226	const MCPhysReg CPUSPReg[] = {
2227	Mips::SP,	2227	Mips::SP,
2228	};	2228	};
2229		2229
2230	// CPUSPReg Bit set.	2230	// CPUSPReg Bit set.
2231	const uint8_t CPUSPRegBits[] = {	2231	const uint8_t CPUSPRegBits[] = {
2232	0x00, 0x00, 0x10,	2232	0x00, 0x00, 0x10,
2233	};	2233	};
2234		2234
2235	// DSPCC Register Class...	2235	// DSPCC Register Class...
2236	const MCPhysReg DSPCC[] = {	2236	const MCPhysReg DSPCC[] = {
2237	Mips::DSPCCond,	2237	Mips::DSPCCond,
2238	};	2238	};
2239		2239
2240	// DSPCC Bit set.	2240	// DSPCC Bit set.
2241	const uint8_t DSPCCBits[] = {	2241	const uint8_t DSPCCBits[] = {
2242	0x04,	2242	0x04,
2243	};	2243	};
2244		2244
2245	// GP32 Register Class...	2245	// GP32 Register Class...
2246	const MCPhysReg GP32[] = {	2246	const MCPhysReg GP32[] = {
2247	Mips::GP,	2247	Mips::GP,
2248	};	2248	};
2249		2249
2250	// GP32 Bit set.	2250	// GP32 Bit set.
2251	const uint8_t GP32Bits[] = {	2251	const uint8_t GP32Bits[] = {
2252	0x00, 0x02,	2252	0x00, 0x02,
2253	};	2253	};
2254		2254
2255	// GPR32ZERO Register Class...	2255	// GPR32ZERO Register Class...
2256	const MCPhysReg GPR32ZERO[] = {	2256	const MCPhysReg GPR32ZERO[] = {
2257	Mips::ZERO,	2257	Mips::ZERO,
2258	};	2258	};
2259		2259
2260	// GPR32ZERO Bit set.	2260	// GPR32ZERO Bit set.
2261	const uint8_t GPR32ZEROBits[] = {	2261	const uint8_t GPR32ZEROBits[] = {
2262	0x00, 0x00, 0x20,	2262	0x00, 0x00, 0x20,
2263	};	2263	};
2264		2264
2265	// HI32 Register Class...	2265	// HI32 Register Class...
2266	const MCPhysReg HI32[] = {	2266	const MCPhysReg HI32[] = {
2267	Mips::HI0,	2267	Mips::HI0,
2268	};	2268	};
2269		2269
2270	// HI32 Bit set.	2270	// HI32 Bit set.
2271	const uint8_t HI32Bits[] = {	2271	const uint8_t HI32Bits[] = {
2272	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	2272	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2273	};	2273	};
2274		2274
2275	// LO32 Register Class...	2275	// LO32 Register Class...
2276	const MCPhysReg LO32[] = {	2276	const MCPhysReg LO32[] = {
2277	Mips::LO0,	2277	Mips::LO0,
2278	};	2278	};
2279		2279
2280	// LO32 Bit set.	2280	// LO32 Bit set.
2281	const uint8_t LO32Bits[] = {	2281	const uint8_t LO32Bits[] = {
2282	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	2282	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2283	};	2283	};
2284		2284
2285	// SP32 Register Class...	2285	// SP32 Register Class...
2286	const MCPhysReg SP32[] = {	2286	const MCPhysReg SP32[] = {
2287	Mips::SP,	2287	Mips::SP,
2288	};	2288	};
2289		2289
2290	// SP32 Bit set.	2290	// SP32 Bit set.
2291	const uint8_t SP32Bits[] = {	2291	const uint8_t SP32Bits[] = {
2292	0x00, 0x00, 0x10,	2292	0x00, 0x00, 0x10,
2293	};	2293	};
2294		2294
2295	// FGR64 Register Class...	2295	// FGR64 Register Class...
2296	const MCPhysReg FGR64[] = {	2296	const MCPhysReg FGR64[] = {
2297	Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,	2297	Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
2298	};	2298	};
2299		2299
2300	// FGR64 Bit set.	2300	// FGR64 Bit set.
2301	const uint8_t FGR64Bits[] = {	2301	const uint8_t FGR64Bits[] = {
2302	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	2302	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
2303	};	2303	};
2304		2304
2305	// GPR64 Register Class...	2305	// GPR64 Register Class...
2306	const MCPhysReg GPR64[] = {	2306	const MCPhysReg GPR64[] = {
2307	Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	2307	Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2308	};	2308	};
2309		2309
2310	// GPR64 Bit set.	2310	// GPR64 Bit set.
2311	const uint8_t GPR64Bits[] = {	2311	const uint8_t GPR64Bits[] = {
2312	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	2312	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2313	};	2313	};
2314		2314
2315	// GPR64_with_sub_32_in_GPR32NONZERO Register Class...	2315	// GPR64_with_sub_32_in_GPR32NONZERO Register Class...
2316	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {	2316	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
2317	Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	2317	Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
2318	};	2318	};
2319		2319
2320	// GPR64_with_sub_32_in_GPR32NONZERO Bit set.	2320	// GPR64_with_sub_32_in_GPR32NONZERO Bit set.
2321	const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {	2321	const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
2322	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	2322	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
2323	};	2323	};
2324		2324
2325	// AFGR64 Register Class...	2325	// AFGR64 Register Class...
2326	const MCPhysReg AFGR64[] = {	2326	const MCPhysReg AFGR64[] = {
2327	Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,	2327	Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
2328	};	2328	};
2329		2329
2330	// AFGR64 Bit set.	2330	// AFGR64 Bit set.
2331	const uint8_t AFGR64Bits[] = {	2331	const uint8_t AFGR64Bits[] = {
2332	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,	2332	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
2333	};	2333	};
2334		2334
2335	// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...	2335	// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
2336	const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {	2336	const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
2337	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,	2337	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
2338	};	2338	};
2339		2339
2340	// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.	2340	// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
2341	const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {	2341	const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
2342	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	2342	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2343	};	2343	};
2344		2344
2345	// GPR64_with_sub_32_in_CPU16Regs Register Class...	2345	// GPR64_with_sub_32_in_CPU16Regs Register Class...
2346	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {	2346	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
2347	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,	2347	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
2348	};	2348	};
2349		2349
2350	// GPR64_with_sub_32_in_CPU16Regs Bit set.	2350	// GPR64_with_sub_32_in_CPU16Regs Bit set.
2351	const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {	2351	const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
2352	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	2352	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2353	};	2353	};
2354		2354
2355	// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...	2355	// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
2356	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {	2356	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
2357	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	2357	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2358	};	2358	};
2359		2359
2360	// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.	2360	// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
2361	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {	2361	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
2362	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	2362	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2363	};	2363	};
2364		2364
2365	// GPR64_with_sub_32_in_GPRMM16Zero Register Class...	2365	// GPR64_with_sub_32_in_GPRMM16Zero Register Class...
2366	const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {	2366	const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
2367	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	2367	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2368	};	2368	};
2369		2369
2370	// GPR64_with_sub_32_in_GPRMM16Zero Bit set.	2370	// GPR64_with_sub_32_in_GPRMM16Zero Bit set.
2371	const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {	2371	const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
2372	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	2372	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2373	};	2373	};
2374		2374
2375	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...	2375	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
2376	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {	2376	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
2377	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	2377	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
2378	};	2378	};
2379		2379
2380	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.	2380	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
2381	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {	2381	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
2382	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	2382	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2383	};	2383	};
2384		2384
2385	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...	2385	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
2386	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {	2386	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
2387	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	2387	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
2388	};	2388	};
2389		2389
2390	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.	2390	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
2391	const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {	2391	const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
2392	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	2392	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
2393	};	2393	};
2394		2394
2395	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...	2395	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
2396	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {	2396	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
2397	Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,	2397	Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,
2398	};	2398	};
2399		2399
2400	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.	2400	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
2401	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {	2401	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
2402	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	2402	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
2403	};	2403	};
2404		2404
2405	// ACC64DSP Register Class...	2405	// ACC64DSP Register Class...
2406	const MCPhysReg ACC64DSP[] = {	2406	const MCPhysReg ACC64DSP[] = {
2407	Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,	2407	Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
2408	};	2408	};
2409		2409
2410	// ACC64DSP Bit set.	2410	// ACC64DSP Bit set.
2411	const uint8_t ACC64DSPBits[] = {	2411	const uint8_t ACC64DSPBits[] = {
2412	0x00, 0x00, 0x00, 0x3c,	2412	0x00, 0x00, 0x00, 0x3c,
2413	};	2413	};
2414		2414
2415	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...	2415	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
2416	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {	2416	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
2417	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,	2417	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
2418	};	2418	};
2419		2419
2420	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.	2420	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
2421	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {	2421	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
2422	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	2422	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
2423	};	2423	};
2424		2424
2425	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...	2425	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
2426	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {	2426	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
2427	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,	2427	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
2428	};	2428	};
2429		2429
2430	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.	2430	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
2431	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	2431	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
2432	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	2432	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2433	};	2433	};
2434		2434
2435	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	2435	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
2436	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {	2436	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
2437	Mips::A1_64, Mips::A2_64, Mips::A3_64,	2437	Mips::A1_64, Mips::A2_64, Mips::A3_64,
2438	};	2438	};
2439		2439
2440	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	2440	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
2441	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	2441	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
2442	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,	2442	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
2443	};	2443	};
2444		2444
2445	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...	2445	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
2446	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {	2446	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
2447	Mips::A0_64, Mips::A1_64, Mips::A2_64,	2447	Mips::A0_64, Mips::A1_64, Mips::A2_64,
2448	};	2448	};
2449		2449
2450	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.	2450	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
2451	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {	2451	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
2452	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,	2452	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
2453	};	2453	};
2454		2454
2455	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	2455	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
2456	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	2456	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
2457	Mips::V0_64, Mips::V1_64, Mips::S1_64,	2457	Mips::V0_64, Mips::V1_64, Mips::S1_64,
2458	};	2458	};
2459		2459
2460	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	2460	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
2461	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	2461	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
2462	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	2462	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
2463	};	2463	};
2464		2464
2465	// OCTEON_MPL Register Class...	2465	// OCTEON_MPL Register Class...
2466	const MCPhysReg OCTEON_MPL[] = {	2466	const MCPhysReg OCTEON_MPL[] = {
2467	Mips::MPL0, Mips::MPL1, Mips::MPL2,	2467	Mips::MPL0, Mips::MPL1, Mips::MPL2,
2468	};	2468	};
2469		2469
2470	// OCTEON_MPL Bit set.	2470	// OCTEON_MPL Bit set.
2471	const uint8_t OCTEON_MPLBits[] = {	2471	const uint8_t OCTEON_MPLBits[] = {
2472	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,	2472	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
2473	};	2473	};
2474		2474
2475	// OCTEON_P Register Class...	2475	// OCTEON_P Register Class...
2476	const MCPhysReg OCTEON_P[] = {	2476	const MCPhysReg OCTEON_P[] = {
2477	Mips::P0, Mips::P1, Mips::P2,	2477	Mips::P0, Mips::P1, Mips::P2,
2478	};	2478	};
2479		2479
2480	// OCTEON_P Bit set.	2480	// OCTEON_P Bit set.
2481	const uint8_t OCTEON_PBits[] = {	2481	const uint8_t OCTEON_PBits[] = {
2482	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,	2482	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
2483	};	2483	};
2484		2484
2485	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	2485	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
2486	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	2486	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
2487	Mips::A1_64, Mips::A2_64,	2487	Mips::A1_64, Mips::A2_64,
2488	};	2488	};
2489		2489
2490	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	2490	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
2491	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	2491	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
2492	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,	2492	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
2493	};	2493	};
2494		2494
2495	// ACC64 Register Class...	2495	// ACC64 Register Class...
2496	const MCPhysReg ACC64[] = {	2496	const MCPhysReg ACC64[] = {
2497	Mips::AC0,	2497	Mips::AC0,
2498	};	2498	};
2499		2499
2500	// ACC64 Bit set.	2500	// ACC64 Bit set.
2501	const uint8_t ACC64Bits[] = {	2501	const uint8_t ACC64Bits[] = {
2502	0x00, 0x00, 0x00, 0x04,	2502	0x00, 0x00, 0x00, 0x04,
2503	};	2503	};
2504		2504
2505	// GP64 Register Class...	2505	// GP64 Register Class...
2506	const MCPhysReg GP64[] = {	2506	const MCPhysReg GP64[] = {
2507	Mips::GP_64,	2507	Mips::GP_64,
2508	};	2508	};
2509		2509
2510	// GP64 Bit set.	2510	// GP64 Bit set.
2511	const uint8_t GP64Bits[] = {	2511	const uint8_t GP64Bits[] = {
2512	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,	2512	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
2513	};	2513	};
2514		2514
2515	// GPR64_with_sub_32_in_CPURAReg Register Class...	2515	// GPR64_with_sub_32_in_CPURAReg Register Class...
2516	const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {	2516	const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
2517	Mips::RA_64,	2517	Mips::RA_64,
2518	};	2518	};
2519		2519
2520	// GPR64_with_sub_32_in_CPURAReg Bit set.	2520	// GPR64_with_sub_32_in_CPURAReg Bit set.
2521	const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {	2521	const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
2522	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	2522	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2523	};	2523	};
2524		2524
2525	// GPR64_with_sub_32_in_GPR32ZERO Register Class...	2525	// GPR64_with_sub_32_in_GPR32ZERO Register Class...
2526	const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {	2526	const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
2527	Mips::ZERO_64,	2527	Mips::ZERO_64,
2528	};	2528	};
2529		2529
2530	// GPR64_with_sub_32_in_GPR32ZERO Bit set.	2530	// GPR64_with_sub_32_in_GPR32ZERO Bit set.
2531	const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {	2531	const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
2532	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	2532	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
2533	};	2533	};
2534		2534
2535	// HI64 Register Class...	2535	// HI64 Register Class...
2536	const MCPhysReg HI64[] = {	2536	const MCPhysReg HI64[] = {
2537	Mips::HI0_64,	2537	Mips::HI0_64,
2538	};	2538	};
2539		2539
2540	// HI64 Bit set.	2540	// HI64 Bit set.
2541	const uint8_t HI64Bits[] = {	2541	const uint8_t HI64Bits[] = {
2542	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,	2542	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
2543	};	2543	};
2544		2544
2545	// LO64 Register Class...	2545	// LO64 Register Class...
2546	const MCPhysReg LO64[] = {	2546	const MCPhysReg LO64[] = {
2547	Mips::LO0_64,	2547	Mips::LO0_64,
2548	};	2548	};
2549		2549
2550	// LO64 Bit set.	2550	// LO64 Bit set.
2551	const uint8_t LO64Bits[] = {	2551	const uint8_t LO64Bits[] = {
2552	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	2552	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
2553	};	2553	};
2554		2554
2555	// SP64 Register Class...	2555	// SP64 Register Class...
2556	const MCPhysReg SP64[] = {	2556	const MCPhysReg SP64[] = {
2557	Mips::SP_64,	2557	Mips::SP_64,
2558	};	2558	};
2559		2559
2560	// SP64 Bit set.	2560	// SP64 Bit set.
2561	const uint8_t SP64Bits[] = {	2561	const uint8_t SP64Bits[] = {
2562	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,	2562	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
2563	};	2563	};
2564		2564
2565	// MSA128B Register Class...	2565	// MSA128B Register Class...
2566	const MCPhysReg MSA128B[] = {	2566	const MCPhysReg MSA128B[] = {
2567	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	2567	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2568	};	2568	};
2569		2569
2570	// MSA128B Bit set.	2570	// MSA128B Bit set.
2571	const uint8_t MSA128BBits[] = {	2571	const uint8_t MSA128BBits[] = {
2572	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	2572	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2573	};	2573	};
2574		2574
2575	// MSA128D Register Class...	2575	// MSA128D Register Class...
2576	const MCPhysReg MSA128D[] = {	2576	const MCPhysReg MSA128D[] = {
2577	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	2577	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2578	};	2578	};
2579		2579
2580	// MSA128D Bit set.	2580	// MSA128D Bit set.
2581	const uint8_t MSA128DBits[] = {	2581	const uint8_t MSA128DBits[] = {
2582	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	2582	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2583	};	2583	};
2584		2584
2585	// MSA128H Register Class...	2585	// MSA128H Register Class...
2586	const MCPhysReg MSA128H[] = {	2586	const MCPhysReg MSA128H[] = {
2587	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	2587	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2588	};	2588	};
2589		2589
2590	// MSA128H Bit set.	2590	// MSA128H Bit set.
2591	const uint8_t MSA128HBits[] = {	2591	const uint8_t MSA128HBits[] = {
2592	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	2592	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2593	};	2593	};
2594		2594
2595	// MSA128W Register Class...	2595	// MSA128W Register Class...
2596	const MCPhysReg MSA128W[] = {	2596	const MCPhysReg MSA128W[] = {
2597	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	2597	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
2598	};	2598	};
2599		2599
2600	// MSA128W Bit set.	2600	// MSA128W Bit set.
2601	const uint8_t MSA128WBits[] = {	2601	const uint8_t MSA128WBits[] = {
2602	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	2602	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
2603	};	2603	};
2604		2604
2605	// MSA128WEvens Register Class...	2605	// MSA128WEvens Register Class...
2606	const MCPhysReg MSA128WEvens[] = {	2606	const MCPhysReg MSA128WEvens[] = {
2607	Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,	2607	Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
2608	};	2608	};
2609		2609
2610	// MSA128WEvens Bit set.	2610	// MSA128WEvens Bit set.
2611	const uint8_t MSA128WEvensBits[] = {	2611	const uint8_t MSA128WEvensBits[] = {
2612	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,	2612	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
2613	};	2613	};
2614		2614
2615	// ACC128 Register Class...	2615	// ACC128 Register Class...
2616	const MCPhysReg ACC128[] = {	2616	const MCPhysReg ACC128[] = {
2617	Mips::AC0_64,	2617	Mips::AC0_64,
2618	};	2618	};
2619		2619
2620	// ACC128 Bit set.	2620	// ACC128 Bit set.
2621	const uint8_t ACC128Bits[] = {	2621	const uint8_t ACC128Bits[] = {
2622	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,	2622	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
2623	};	2623	};
2624		2624
2625	} // end anonymous namespace	2625	} // end anonymous namespace
2626		2626
2627		2627
2628	#ifdef __GNUC__	2628	#ifdef __GNUC__
2629	#pragma GCC diagnostic push	2629	#pragma GCC diagnostic push
2630	#pragma GCC diagnostic ignored "-Woverlength-strings"	2630	#pragma GCC diagnostic ignored "-Woverlength-strings"
2631	#endif	2631	#endif
2632	extern const char MipsRegClassStrings[] = {	2632	extern const char MipsRegClassStrings[] = {
2633	/* 0 */ "COP0\0"	2633	/* 0 */ "COP0\0"
2634	/* 5 */ "HI32\0"	2634	/* 5 */ "HI32\0"
2635	/* 10 */ "LO32\0"	2635	/* 10 */ "LO32\0"
2636	/* 15 */ "GP32\0"	2636	/* 15 */ "GP32\0"
2637	/* 20 */ "SP32\0"	2637	/* 20 */ "SP32\0"
2638	/* 25 */ "FGR32\0"	2638	/* 25 */ "FGR32\0"
2639	/* 31 */ "GPR32\0"	2639	/* 31 */ "GPR32\0"
2640	/* 37 */ "COP2\0"	2640	/* 37 */ "COP2\0"
2641	/* 42 */ "COP3\0"	2641	/* 42 */ "COP3\0"
2642	/* 47 */ "ACC64\0"	2642	/* 47 */ "ACC64\0"
2643	/* 53 */ "HI64\0"	2643	/* 53 */ "HI64\0"
2644	/* 58 */ "LO64\0"	2644	/* 58 */ "LO64\0"
2645	/* 63 */ "GP64\0"	2645	/* 63 */ "GP64\0"
2646	/* 68 */ "SP64\0"	2646	/* 68 */ "SP64\0"
2647	/* 73 */ "AFGR64\0"	2647	/* 73 */ "AFGR64\0"
2648	/* 80 */ "GPR64\0"	2648	/* 80 */ "GPR64\0"
2649	/* 86 */ "MSA128F16\0"	2649	/* 86 */ "MSA128F16\0"
2650	/* 96 */ "GPRMM16\0"	2650	/* 96 */ "GPRMM16\0"
2651	/* 104 */ "ACC128\0"	2651	/* 104 */ "ACC128\0"
2652	/* 111 */ "MSA128B\0"	2652	/* 111 */ "MSA128B\0"
2653	/* 119 */ "FCC\0"	2653	/* 119 */ "FCC\0"
2654	/* 123 */ "DSPCC\0"	2654	/* 123 */ "DSPCC\0"
2655	/* 129 */ "FGRCC\0"	2655	/* 129 */ "FGRCC\0"
2656	/* 135 */ "MSA128D\0"	2656	/* 135 */ "MSA128D\0"
2657	/* 143 */ "MSA128H\0"	2657	/* 143 */ "MSA128H\0"
2658	/* 151 */ "OCTEON_MPL\0"	2658	/* 151 */ "OCTEON_MPL\0"
2659	/* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"	2659	/* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"
2660	/* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"	2660	/* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"
2661	/* 227 */ "HI32DSP\0"	2661	/* 227 */ "HI32DSP\0"
2662	/* 235 */ "LO32DSP\0"	2662	/* 235 */ "LO32DSP\0"
2663	/* 243 */ "ACC64DSP\0"	2663	/* 243 */ "ACC64DSP\0"
2664	/* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"	2664	/* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"
2665	/* 289 */ "OCTEON_P\0"	2665	/* 289 */ "OCTEON_P\0"
2666	/* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"	2666	/* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"
2667	/* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"	2667	/* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"
2668	/* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"	2668	/* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"
2669	/* 431 */ "CCR\0"	2669	/* 431 */ "CCR\0"
2670	/* 435 */ "DSPR\0"	2670	/* 435 */ "DSPR\0"
2671	/* 440 */ "MSA128W\0"	2671	/* 440 */ "MSA128W\0"
2672	/* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"	2672	/* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"
2673	/* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"	2673	/* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"
2674	/* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"	2674	/* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"
2675	/* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"	2675	/* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"
2676	/* 650 */ "CPUSPReg\0"	2676	/* 650 */ "CPUSPReg\0"
2677	/* 659 */ "MSACtrl\0"	2677	/* 659 */ "MSACtrl\0"
2678	/* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"	2678	/* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"
2679	/* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"	2679	/* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"
2680	/* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"	2680	/* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"
2681	/* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"	2681	/* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"
2682	/* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"	2682	/* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"
2683	/* 892 */ "HWRegs\0"	2683	/* 892 */ "HWRegs\0"
2684	/* 899 */ "MSA128WEvens\0"	2684	/* 899 */ "MSA128WEvens\0"
2685	/* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"	2685	/* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"
2686	};	2686	};
2687	#ifdef __GNUC__	2687	#ifdef __GNUC__
2688	#pragma GCC diagnostic pop	2688	#pragma GCC diagnostic pop
2689	#endif	2689	#endif
2690		2690
2691	extern const MCRegisterClass MipsMCRegisterClasses[] = {	2691	extern const MCRegisterClass MipsMCRegisterClasses[] = {
2692	{ MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },	2692	{ MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },
2693	{ CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },	2693	{ CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },
2694	{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },	2694	{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },
2695	{ COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },	2695	{ COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },
2696	{ COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },	2696	{ COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },
2697	{ DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },	2697	{ DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },
2698	{ FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },	2698	{ FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },
2699	{ FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },	2699	{ FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },
2700	{ GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },	2700	{ GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },
2701	{ HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },	2701	{ HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },
2702	{ MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },	2702	{ MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },
2703	{ GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },	2703	{ GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },
2704	{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },	2704	{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },
2705	{ CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },	2705	{ CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },
2706	{ FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },	2706	{ FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },
2707	{ GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },	2707	{ GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },
2708	{ GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },	2708	{ GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },
2709	{ GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },	2709	{ GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },
2710	{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	2710	{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
2711	{ GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },	2711	{ GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },
2712	{ GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },	2712	{ GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2713	{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },	2713	{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },
2714	{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },	2714	{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },
2715	{ HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },	2715	{ HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },
2716	{ LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },	2716	{ LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },
2717	{ CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	2717	{ CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2718	{ GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },	2718	{ GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },
2719	{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	2719	{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
2720	{ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	2720	{ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
2721	{ CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },	2721	{ CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },
2722	{ CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },	2722	{ CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },
2723	{ DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },	2723	{ DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },
2724	{ GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },	2724	{ GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },
2725	{ GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },	2725	{ GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },
2726	{ HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },	2726	{ HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },
2727	{ LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },	2727	{ LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },
2728	{ SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },	2728	{ SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },
2729	{ FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },	2729	{ FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },
2730	{ GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },	2730	{ GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },
2731	{ GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },	2731	{ GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },
2732	{ AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },	2732	{ AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },
2733	{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },	2733	{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },
2734	{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },	2734	{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },
2735	{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },	2735	{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },
2736	{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },	2736	{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },
2737	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	2737	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
2738	{ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },	2738	{ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },
2739	{ GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	2739	{ GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2740	{ ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },	2740	{ ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },
2741	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },	2741	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },
2742	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },	2742	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },
2743	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	2743	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2744	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },	2744	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },
2745	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	2745	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
2746	{ OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },	2746	{ OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },
2747	{ OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },	2747	{ OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },
2748	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	2748	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
2749	{ ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },	2749	{ ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },
2750	{ GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },	2750	{ GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },
2751	{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },	2751	{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },
2752	{ GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },	2752	{ GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },
2753	{ HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },	2753	{ HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },
2754	{ LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },	2754	{ LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },
2755	{ SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },	2755	{ SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },
2756	{ MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },	2756	{ MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },
2757	{ MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },	2757	{ MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },
2758	{ MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },	2758	{ MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },
2759	{ MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },	2759	{ MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },
2760	{ MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },	2760	{ MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },
2761	{ ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },	2761	{ ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },
2762	};	2762	};
2763		2763
2764	// Mips Dwarf<->LLVM register mappings.	2764	// Mips Dwarf<->LLVM register mappings.
2765	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {	2765	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
2766	{ 0U, Mips::ZERO_64 },	2766	{ 0U, Mips::ZERO_64 },
2767	{ 1U, Mips::AT_64 },	2767	{ 1U, Mips::AT_64 },
2768	{ 2U, Mips::V0_64 },	2768	{ 2U, Mips::V0_64 },
2769	{ 3U, Mips::V1_64 },	2769	{ 3U, Mips::V1_64 },
2770	{ 4U, Mips::A0_64 },	2770	{ 4U, Mips::A0_64 },
2771	{ 5U, Mips::A1_64 },	2771	{ 5U, Mips::A1_64 },
2772	{ 6U, Mips::A2_64 },	2772	{ 6U, Mips::A2_64 },
2773	{ 7U, Mips::A3_64 },	2773	{ 7U, Mips::A3_64 },
2774	{ 8U, Mips::T0_64 },	2774	{ 8U, Mips::T0_64 },
2775	{ 9U, Mips::T1_64 },	2775	{ 9U, Mips::T1_64 },
2776	{ 10U, Mips::T2_64 },	2776	{ 10U, Mips::T2_64 },
2777	{ 11U, Mips::T3_64 },	2777	{ 11U, Mips::T3_64 },
2778	{ 12U, Mips::T4_64 },	2778	{ 12U, Mips::T4_64 },
2779	{ 13U, Mips::T5_64 },	2779	{ 13U, Mips::T5_64 },
2780	{ 14U, Mips::T6_64 },	2780	{ 14U, Mips::T6_64 },
2781	{ 15U, Mips::T7_64 },	2781	{ 15U, Mips::T7_64 },
2782	{ 16U, Mips::S0_64 },	2782	{ 16U, Mips::S0_64 },
2783	{ 17U, Mips::S1_64 },	2783	{ 17U, Mips::S1_64 },
2784	{ 18U, Mips::S2_64 },	2784	{ 18U, Mips::S2_64 },
2785	{ 19U, Mips::S3_64 },	2785	{ 19U, Mips::S3_64 },
2786	{ 20U, Mips::S4_64 },	2786	{ 20U, Mips::S4_64 },
2787	{ 21U, Mips::S5_64 },	2787	{ 21U, Mips::S5_64 },
2788	{ 22U, Mips::S6_64 },	2788	{ 22U, Mips::S6_64 },
2789	{ 23U, Mips::S7_64 },	2789	{ 23U, Mips::S7_64 },
2790	{ 24U, Mips::T8_64 },	2790	{ 24U, Mips::T8_64 },
2791	{ 25U, Mips::T9_64 },	2791	{ 25U, Mips::T9_64 },
2792	{ 26U, Mips::K0_64 },	2792	{ 26U, Mips::K0_64 },
2793	{ 27U, Mips::K1_64 },	2793	{ 27U, Mips::K1_64 },
2794	{ 28U, Mips::GP_64 },	2794	{ 28U, Mips::GP_64 },
2795	{ 29U, Mips::SP_64 },	2795	{ 29U, Mips::SP_64 },
2796	{ 30U, Mips::FP_64 },	2796	{ 30U, Mips::FP_64 },
2797	{ 31U, Mips::RA_64 },	2797	{ 31U, Mips::RA_64 },
2798	{ 32U, Mips::D0_64 },	2798	{ 32U, Mips::D0_64 },
2799	{ 33U, Mips::D1_64 },	2799	{ 33U, Mips::D1_64 },
2800	{ 34U, Mips::D2_64 },	2800	{ 34U, Mips::D2_64 },
2801	{ 35U, Mips::D3_64 },	2801	{ 35U, Mips::D3_64 },
2802	{ 36U, Mips::D4_64 },	2802	{ 36U, Mips::D4_64 },
2803	{ 37U, Mips::D5_64 },	2803	{ 37U, Mips::D5_64 },
2804	{ 38U, Mips::D6_64 },	2804	{ 38U, Mips::D6_64 },
2805	{ 39U, Mips::D7_64 },	2805	{ 39U, Mips::D7_64 },
2806	{ 40U, Mips::D8_64 },	2806	{ 40U, Mips::D8_64 },
2807	{ 41U, Mips::D9_64 },	2807	{ 41U, Mips::D9_64 },
2808	{ 42U, Mips::D10_64 },	2808	{ 42U, Mips::D10_64 },
2809	{ 43U, Mips::D11_64 },	2809	{ 43U, Mips::D11_64 },
2810	{ 44U, Mips::D12_64 },	2810	{ 44U, Mips::D12_64 },
2811	{ 45U, Mips::D13_64 },	2811	{ 45U, Mips::D13_64 },
2812	{ 46U, Mips::D14_64 },	2812	{ 46U, Mips::D14_64 },
2813	{ 47U, Mips::D15_64 },	2813	{ 47U, Mips::D15_64 },
2814	{ 48U, Mips::D16_64 },	2814	{ 48U, Mips::D16_64 },
2815	{ 49U, Mips::D17_64 },	2815	{ 49U, Mips::D17_64 },
2816	{ 50U, Mips::D18_64 },	2816	{ 50U, Mips::D18_64 },
2817	{ 51U, Mips::D19_64 },	2817	{ 51U, Mips::D19_64 },
2818	{ 52U, Mips::D20_64 },	2818	{ 52U, Mips::D20_64 },
2819	{ 53U, Mips::D21_64 },	2819	{ 53U, Mips::D21_64 },
2820	{ 54U, Mips::D22_64 },	2820	{ 54U, Mips::D22_64 },
2821	{ 55U, Mips::D23_64 },	2821	{ 55U, Mips::D23_64 },
2822	{ 56U, Mips::D24_64 },	2822	{ 56U, Mips::D24_64 },
2823	{ 57U, Mips::D25_64 },	2823	{ 57U, Mips::D25_64 },
2824	{ 58U, Mips::D26_64 },	2824	{ 58U, Mips::D26_64 },
2825	{ 59U, Mips::D27_64 },	2825	{ 59U, Mips::D27_64 },
2826	{ 60U, Mips::D28_64 },	2826	{ 60U, Mips::D28_64 },
2827	{ 61U, Mips::D29_64 },	2827	{ 61U, Mips::D29_64 },
2828	{ 62U, Mips::D30_64 },	2828	{ 62U, Mips::D30_64 },
2829	{ 63U, Mips::D31_64 },	2829	{ 63U, Mips::D31_64 },
2830	{ 64U, Mips::HI0 },	2830	{ 64U, Mips::HI0 },
2831	{ 65U, Mips::LO0 },	2831	{ 65U, Mips::LO0 },
2832	{ 176U, Mips::HI1 },	2832	{ 176U, Mips::HI1 },
2833	{ 177U, Mips::LO1 },	2833	{ 177U, Mips::LO1 },
2834	{ 178U, Mips::HI2 },	2834	{ 178U, Mips::HI2 },
2835	{ 179U, Mips::LO2 },	2835	{ 179U, Mips::LO2 },
2836	{ 180U, Mips::HI3 },	2836	{ 180U, Mips::HI3 },
2837	{ 181U, Mips::LO3 },	2837	{ 181U, Mips::LO3 },
2838	};	2838	};
2839	extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);	2839	extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);
2840		2840
2841	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {	2841	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
2842	{ 0U, Mips::ZERO_64 },	2842	{ 0U, Mips::ZERO_64 },
2843	{ 1U, Mips::AT_64 },	2843	{ 1U, Mips::AT_64 },
2844	{ 2U, Mips::V0_64 },	2844	{ 2U, Mips::V0_64 },
2845	{ 3U, Mips::V1_64 },	2845	{ 3U, Mips::V1_64 },
2846	{ 4U, Mips::A0_64 },	2846	{ 4U, Mips::A0_64 },
2847	{ 5U, Mips::A1_64 },	2847	{ 5U, Mips::A1_64 },
2848	{ 6U, Mips::A2_64 },	2848	{ 6U, Mips::A2_64 },
2849	{ 7U, Mips::A3_64 },	2849	{ 7U, Mips::A3_64 },
2850	{ 8U, Mips::T0_64 },	2850	{ 8U, Mips::T0_64 },
2851	{ 9U, Mips::T1_64 },	2851	{ 9U, Mips::T1_64 },
2852	{ 10U, Mips::T2_64 },	2852	{ 10U, Mips::T2_64 },
2853	{ 11U, Mips::T3_64 },	2853	{ 11U, Mips::T3_64 },
2854	{ 12U, Mips::T4_64 },	2854	{ 12U, Mips::T4_64 },
2855	{ 13U, Mips::T5_64 },	2855	{ 13U, Mips::T5_64 },
2856	{ 14U, Mips::T6_64 },	2856	{ 14U, Mips::T6_64 },
2857	{ 15U, Mips::T7_64 },	2857	{ 15U, Mips::T7_64 },
2858	{ 16U, Mips::S0_64 },	2858	{ 16U, Mips::S0_64 },
2859	{ 17U, Mips::S1_64 },	2859	{ 17U, Mips::S1_64 },
2860	{ 18U, Mips::S2_64 },	2860	{ 18U, Mips::S2_64 },
2861	{ 19U, Mips::S3_64 },	2861	{ 19U, Mips::S3_64 },
2862	{ 20U, Mips::S4_64 },	2862	{ 20U, Mips::S4_64 },
2863	{ 21U, Mips::S5_64 },	2863	{ 21U, Mips::S5_64 },
2864	{ 22U, Mips::S6_64 },	2864	{ 22U, Mips::S6_64 },
2865	{ 23U, Mips::S7_64 },	2865	{ 23U, Mips::S7_64 },
2866	{ 24U, Mips::T8_64 },	2866	{ 24U, Mips::T8_64 },
2867	{ 25U, Mips::T9_64 },	2867	{ 25U, Mips::T9_64 },
2868	{ 26U, Mips::K0_64 },	2868	{ 26U, Mips::K0_64 },
2869	{ 27U, Mips::K1_64 },	2869	{ 27U, Mips::K1_64 },
2870	{ 28U, Mips::GP_64 },	2870	{ 28U, Mips::GP_64 },
2871	{ 29U, Mips::SP_64 },	2871	{ 29U, Mips::SP_64 },
2872	{ 30U, Mips::FP_64 },	2872	{ 30U, Mips::FP_64 },
2873	{ 31U, Mips::RA_64 },	2873	{ 31U, Mips::RA_64 },
2874	{ 32U, Mips::D0_64 },	2874	{ 32U, Mips::D0_64 },
2875	{ 33U, Mips::D1_64 },	2875	{ 33U, Mips::D1_64 },
2876	{ 34U, Mips::D2_64 },	2876	{ 34U, Mips::D2_64 },
2877	{ 35U, Mips::D3_64 },	2877	{ 35U, Mips::D3_64 },
2878	{ 36U, Mips::D4_64 },	2878	{ 36U, Mips::D4_64 },
2879	{ 37U, Mips::D5_64 },	2879	{ 37U, Mips::D5_64 },
2880	{ 38U, Mips::D6_64 },	2880	{ 38U, Mips::D6_64 },
2881	{ 39U, Mips::D7_64 },	2881	{ 39U, Mips::D7_64 },
2882	{ 40U, Mips::D8_64 },	2882	{ 40U, Mips::D8_64 },
2883	{ 41U, Mips::D9_64 },	2883	{ 41U, Mips::D9_64 },
2884	{ 42U, Mips::D10_64 },	2884	{ 42U, Mips::D10_64 },
2885	{ 43U, Mips::D11_64 },	2885	{ 43U, Mips::D11_64 },
2886	{ 44U, Mips::D12_64 },	2886	{ 44U, Mips::D12_64 },
2887	{ 45U, Mips::D13_64 },	2887	{ 45U, Mips::D13_64 },
2888	{ 46U, Mips::D14_64 },	2888	{ 46U, Mips::D14_64 },
2889	{ 47U, Mips::D15_64 },	2889	{ 47U, Mips::D15_64 },
2890	{ 48U, Mips::D16_64 },	2890	{ 48U, Mips::D16_64 },
2891	{ 49U, Mips::D17_64 },	2891	{ 49U, Mips::D17_64 },
2892	{ 50U, Mips::D18_64 },	2892	{ 50U, Mips::D18_64 },
2893	{ 51U, Mips::D19_64 },	2893	{ 51U, Mips::D19_64 },
2894	{ 52U, Mips::D20_64 },	2894	{ 52U, Mips::D20_64 },
2895	{ 53U, Mips::D21_64 },	2895	{ 53U, Mips::D21_64 },
2896	{ 54U, Mips::D22_64 },	2896	{ 54U, Mips::D22_64 },
2897	{ 55U, Mips::D23_64 },	2897	{ 55U, Mips::D23_64 },
2898	{ 56U, Mips::D24_64 },	2898	{ 56U, Mips::D24_64 },
2899	{ 57U, Mips::D25_64 },	2899	{ 57U, Mips::D25_64 },
2900	{ 58U, Mips::D26_64 },	2900	{ 58U, Mips::D26_64 },
2901	{ 59U, Mips::D27_64 },	2901	{ 59U, Mips::D27_64 },
2902	{ 60U, Mips::D28_64 },	2902	{ 60U, Mips::D28_64 },
2903	{ 61U, Mips::D29_64 },	2903	{ 61U, Mips::D29_64 },
2904	{ 62U, Mips::D30_64 },	2904	{ 62U, Mips::D30_64 },
2905	{ 63U, Mips::D31_64 },	2905	{ 63U, Mips::D31_64 },
2906	{ 64U, Mips::HI0 },	2906	{ 64U, Mips::HI0 },
2907	{ 65U, Mips::LO0 },	2907	{ 65U, Mips::LO0 },
2908	{ 176U, Mips::HI1 },	2908	{ 176U, Mips::HI1 },
2909	{ 177U, Mips::LO1 },	2909	{ 177U, Mips::LO1 },
2910	{ 178U, Mips::HI2 },	2910	{ 178U, Mips::HI2 },
2911	{ 179U, Mips::LO2 },	2911	{ 179U, Mips::LO2 },
2912	{ 180U, Mips::HI3 },	2912	{ 180U, Mips::HI3 },
2913	{ 181U, Mips::LO3 },	2913	{ 181U, Mips::LO3 },
2914	};	2914	};
2915	extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);	2915	extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);
2916		2916
2917	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {	2917	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
2918	{ Mips::AT, 1U },	2918	{ Mips::AT, 1U },
2919	{ Mips::FP, 30U },	2919	{ Mips::FP, 30U },
2920	{ Mips::GP, 28U },	2920	{ Mips::GP, 28U },
2921	{ Mips::RA, 31U },	2921	{ Mips::RA, 31U },
2922	{ Mips::SP, 29U },	2922	{ Mips::SP, 29U },
2923	{ Mips::ZERO, 0U },	2923	{ Mips::ZERO, 0U },
2924	{ Mips::A0, 4U },	2924	{ Mips::A0, 4U },
2925	{ Mips::A1, 5U },	2925	{ Mips::A1, 5U },
2926	{ Mips::A2, 6U },	2926	{ Mips::A2, 6U },
2927	{ Mips::A3, 7U },	2927	{ Mips::A3, 7U },
2928	{ Mips::AT_64, 1U },	2928	{ Mips::AT_64, 1U },
2929	{ Mips::F0, 32U },	2929	{ Mips::F0, 32U },
2930	{ Mips::F1, 33U },	2930	{ Mips::F1, 33U },
2931	{ Mips::F2, 34U },	2931	{ Mips::F2, 34U },
2932	{ Mips::F3, 35U },	2932	{ Mips::F3, 35U },
2933	{ Mips::F4, 36U },	2933	{ Mips::F4, 36U },
2934	{ Mips::F5, 37U },	2934	{ Mips::F5, 37U },
2935	{ Mips::F6, 38U },	2935	{ Mips::F6, 38U },
2936	{ Mips::F7, 39U },	2936	{ Mips::F7, 39U },
2937	{ Mips::F8, 40U },	2937	{ Mips::F8, 40U },
2938	{ Mips::F9, 41U },	2938	{ Mips::F9, 41U },
2939	{ Mips::F10, 42U },	2939	{ Mips::F10, 42U },
2940	{ Mips::F11, 43U },	2940	{ Mips::F11, 43U },
2941	{ Mips::F12, 44U },	2941	{ Mips::F12, 44U },
2942	{ Mips::F13, 45U },	2942	{ Mips::F13, 45U },
2943	{ Mips::F14, 46U },	2943	{ Mips::F14, 46U },
2944	{ Mips::F15, 47U },	2944	{ Mips::F15, 47U },
2945	{ Mips::F16, 48U },	2945	{ Mips::F16, 48U },
2946	{ Mips::F17, 49U },	2946	{ Mips::F17, 49U },
2947	{ Mips::F18, 50U },	2947	{ Mips::F18, 50U },
2948	{ Mips::F19, 51U },	2948	{ Mips::F19, 51U },
2949	{ Mips::F20, 52U },	2949	{ Mips::F20, 52U },
2950	{ Mips::F21, 53U },	2950	{ Mips::F21, 53U },
2951	{ Mips::F22, 54U },	2951	{ Mips::F22, 54U },
2952	{ Mips::F23, 55U },	2952	{ Mips::F23, 55U },
2953	{ Mips::F24, 56U },	2953	{ Mips::F24, 56U },
2954	{ Mips::F25, 57U },	2954	{ Mips::F25, 57U },
2955	{ Mips::F26, 58U },	2955	{ Mips::F26, 58U },
2956	{ Mips::F27, 59U },	2956	{ Mips::F27, 59U },
2957	{ Mips::F28, 60U },	2957	{ Mips::F28, 60U },
2958	{ Mips::F29, 61U },	2958	{ Mips::F29, 61U },
2959	{ Mips::F30, 62U },	2959	{ Mips::F30, 62U },
2960	{ Mips::F31, 63U },	2960	{ Mips::F31, 63U },
2961	{ Mips::FP_64, 30U },	2961	{ Mips::FP_64, 30U },
2962	{ Mips::F_HI0, 32U },	2962	{ Mips::F_HI0, 32U },
2963	{ Mips::F_HI1, 33U },	2963	{ Mips::F_HI1, 33U },
2964	{ Mips::F_HI2, 34U },	2964	{ Mips::F_HI2, 34U },
2965	{ Mips::F_HI3, 35U },	2965	{ Mips::F_HI3, 35U },
2966	{ Mips::F_HI4, 36U },	2966	{ Mips::F_HI4, 36U },
2967	{ Mips::F_HI5, 37U },	2967	{ Mips::F_HI5, 37U },
2968	{ Mips::F_HI6, 38U },	2968	{ Mips::F_HI6, 38U },
2969	{ Mips::F_HI7, 39U },	2969	{ Mips::F_HI7, 39U },
2970	{ Mips::F_HI8, 40U },	2970	{ Mips::F_HI8, 40U },
2971	{ Mips::F_HI9, 41U },	2971	{ Mips::F_HI9, 41U },
2972	{ Mips::F_HI10, 42U },	2972	{ Mips::F_HI10, 42U },
2973	{ Mips::F_HI11, 43U },	2973	{ Mips::F_HI11, 43U },
2974	{ Mips::F_HI12, 44U },	2974	{ Mips::F_HI12, 44U },
2975	{ Mips::F_HI13, 45U },	2975	{ Mips::F_HI13, 45U },
2976	{ Mips::F_HI14, 46U },	2976	{ Mips::F_HI14, 46U },
2977	{ Mips::F_HI15, 47U },	2977	{ Mips::F_HI15, 47U },
2978	{ Mips::F_HI16, 48U },	2978	{ Mips::F_HI16, 48U },
2979	{ Mips::F_HI17, 49U },	2979	{ Mips::F_HI17, 49U },
2980	{ Mips::F_HI18, 50U },	2980	{ Mips::F_HI18, 50U },
2981	{ Mips::F_HI19, 51U },	2981	{ Mips::F_HI19, 51U },
2982	{ Mips::F_HI20, 52U },	2982	{ Mips::F_HI20, 52U },
2983	{ Mips::F_HI21, 53U },	2983	{ Mips::F_HI21, 53U },
2984	{ Mips::F_HI22, 54U },	2984	{ Mips::F_HI22, 54U },
2985	{ Mips::F_HI23, 55U },	2985	{ Mips::F_HI23, 55U },
2986	{ Mips::F_HI24, 56U },	2986	{ Mips::F_HI24, 56U },
2987	{ Mips::F_HI25, 57U },	2987	{ Mips::F_HI25, 57U },
2988	{ Mips::F_HI26, 58U },	2988	{ Mips::F_HI26, 58U },
2989	{ Mips::F_HI27, 59U },	2989	{ Mips::F_HI27, 59U },
2990	{ Mips::F_HI28, 60U },	2990	{ Mips::F_HI28, 60U },
2991	{ Mips::F_HI29, 61U },	2991	{ Mips::F_HI29, 61U },
2992	{ Mips::F_HI30, 62U },	2992	{ Mips::F_HI30, 62U },
2993	{ Mips::F_HI31, 63U },	2993	{ Mips::F_HI31, 63U },
2994	{ Mips::GP_64, 28U },	2994	{ Mips::GP_64, 28U },
2995	{ Mips::HI0, 64U },	2995	{ Mips::HI0, 64U },
2996	{ Mips::HI1, 176U },	2996	{ Mips::HI1, 176U },
2997	{ Mips::HI2, 178U },	2997	{ Mips::HI2, 178U },
2998	{ Mips::HI3, 180U },	2998	{ Mips::HI3, 180U },
2999	{ Mips::K0, 26U },	2999	{ Mips::K0, 26U },
3000	{ Mips::K1, 27U },	3000	{ Mips::K1, 27U },
3001	{ Mips::LO0, 65U },	3001	{ Mips::LO0, 65U },
3002	{ Mips::LO1, 177U },	3002	{ Mips::LO1, 177U },
3003	{ Mips::LO2, 179U },	3003	{ Mips::LO2, 179U },
3004	{ Mips::LO3, 181U },	3004	{ Mips::LO3, 181U },
3005	{ Mips::RA_64, 31U },	3005	{ Mips::RA_64, 31U },
3006	{ Mips::S0, 16U },	3006	{ Mips::S0, 16U },
3007	{ Mips::S1, 17U },	3007	{ Mips::S1, 17U },
3008	{ Mips::S2, 18U },	3008	{ Mips::S2, 18U },
3009	{ Mips::S3, 19U },	3009	{ Mips::S3, 19U },
3010	{ Mips::S4, 20U },	3010	{ Mips::S4, 20U },
3011	{ Mips::S5, 21U },	3011	{ Mips::S5, 21U },
3012	{ Mips::S6, 22U },	3012	{ Mips::S6, 22U },
3013	{ Mips::S7, 23U },	3013	{ Mips::S7, 23U },
3014	{ Mips::SP_64, 29U },	3014	{ Mips::SP_64, 29U },
3015	{ Mips::T0, 8U },	3015	{ Mips::T0, 8U },
3016	{ Mips::T1, 9U },	3016	{ Mips::T1, 9U },
3017	{ Mips::T2, 10U },	3017	{ Mips::T2, 10U },
3018	{ Mips::T3, 11U },	3018	{ Mips::T3, 11U },
3019	{ Mips::T4, 12U },	3019	{ Mips::T4, 12U },
3020	{ Mips::T5, 13U },	3020	{ Mips::T5, 13U },
3021	{ Mips::T6, 14U },	3021	{ Mips::T6, 14U },
3022	{ Mips::T7, 15U },	3022	{ Mips::T7, 15U },
3023	{ Mips::T8, 24U },	3023	{ Mips::T8, 24U },
3024	{ Mips::T9, 25U },	3024	{ Mips::T9, 25U },
3025	{ Mips::V0, 2U },	3025	{ Mips::V0, 2U },
3026	{ Mips::V1, 3U },	3026	{ Mips::V1, 3U },
3027	{ Mips::W0, 32U },	3027	{ Mips::W0, 32U },
3028	{ Mips::W1, 33U },	3028	{ Mips::W1, 33U },
3029	{ Mips::W2, 34U },	3029	{ Mips::W2, 34U },
3030	{ Mips::W3, 35U },	3030	{ Mips::W3, 35U },
3031	{ Mips::W4, 36U },	3031	{ Mips::W4, 36U },
3032	{ Mips::W5, 37U },	3032	{ Mips::W5, 37U },
3033	{ Mips::W6, 38U },	3033	{ Mips::W6, 38U },
3034	{ Mips::W7, 39U },	3034	{ Mips::W7, 39U },
3035	{ Mips::W8, 40U },	3035	{ Mips::W8, 40U },
3036	{ Mips::W9, 41U },	3036	{ Mips::W9, 41U },
3037	{ Mips::W10, 42U },	3037	{ Mips::W10, 42U },
3038	{ Mips::W11, 43U },	3038	{ Mips::W11, 43U },
3039	{ Mips::W12, 44U },	3039	{ Mips::W12, 44U },
3040	{ Mips::W13, 45U },	3040	{ Mips::W13, 45U },
3041	{ Mips::W14, 46U },	3041	{ Mips::W14, 46U },
3042	{ Mips::W15, 47U },	3042	{ Mips::W15, 47U },
3043	{ Mips::W16, 48U },	3043	{ Mips::W16, 48U },
3044	{ Mips::W17, 49U },	3044	{ Mips::W17, 49U },
3045	{ Mips::W18, 50U },	3045	{ Mips::W18, 50U },
3046	{ Mips::W19, 51U },	3046	{ Mips::W19, 51U },
3047	{ Mips::W20, 52U },	3047	{ Mips::W20, 52U },
3048	{ Mips::W21, 53U },	3048	{ Mips::W21, 53U },
3049	{ Mips::W22, 54U },	3049	{ Mips::W22, 54U },
3050	{ Mips::W23, 55U },	3050	{ Mips::W23, 55U },
3051	{ Mips::W24, 56U },	3051	{ Mips::W24, 56U },
3052	{ Mips::W25, 57U },	3052	{ Mips::W25, 57U },
3053	{ Mips::W26, 58U },	3053	{ Mips::W26, 58U },
3054	{ Mips::W27, 59U },	3054	{ Mips::W27, 59U },
3055	{ Mips::W28, 60U },	3055	{ Mips::W28, 60U },
3056	{ Mips::W29, 61U },	3056	{ Mips::W29, 61U },
3057	{ Mips::W30, 62U },	3057	{ Mips::W30, 62U },
3058	{ Mips::W31, 63U },	3058	{ Mips::W31, 63U },
3059	{ Mips::ZERO_64, 0U },	3059	{ Mips::ZERO_64, 0U },
3060	{ Mips::A0_64, 4U },	3060	{ Mips::A0_64, 4U },
3061	{ Mips::A1_64, 5U },	3061	{ Mips::A1_64, 5U },
3062	{ Mips::A2_64, 6U },	3062	{ Mips::A2_64, 6U },
3063	{ Mips::A3_64, 7U },	3063	{ Mips::A3_64, 7U },
3064	{ Mips::D0_64, 32U },	3064	{ Mips::D0_64, 32U },
3065	{ Mips::D1_64, 33U },	3065	{ Mips::D1_64, 33U },
3066	{ Mips::D2_64, 34U },	3066	{ Mips::D2_64, 34U },
3067	{ Mips::D3_64, 35U },	3067	{ Mips::D3_64, 35U },
3068	{ Mips::D4_64, 36U },	3068	{ Mips::D4_64, 36U },
3069	{ Mips::D5_64, 37U },	3069	{ Mips::D5_64, 37U },
3070	{ Mips::D6_64, 38U },	3070	{ Mips::D6_64, 38U },
3071	{ Mips::D7_64, 39U },	3071	{ Mips::D7_64, 39U },
3072	{ Mips::D8_64, 40U },	3072	{ Mips::D8_64, 40U },
3073	{ Mips::D9_64, 41U },	3073	{ Mips::D9_64, 41U },
3074	{ Mips::D10_64, 42U },	3074	{ Mips::D10_64, 42U },
3075	{ Mips::D11_64, 43U },	3075	{ Mips::D11_64, 43U },
3076	{ Mips::D12_64, 44U },	3076	{ Mips::D12_64, 44U },
3077	{ Mips::D13_64, 45U },	3077	{ Mips::D13_64, 45U },
3078	{ Mips::D14_64, 46U },	3078	{ Mips::D14_64, 46U },
3079	{ Mips::D15_64, 47U },	3079	{ Mips::D15_64, 47U },
3080	{ Mips::D16_64, 48U },	3080	{ Mips::D16_64, 48U },
3081	{ Mips::D17_64, 49U },	3081	{ Mips::D17_64, 49U },
3082	{ Mips::D18_64, 50U },	3082	{ Mips::D18_64, 50U },
3083	{ Mips::D19_64, 51U },	3083	{ Mips::D19_64, 51U },
3084	{ Mips::D20_64, 52U },	3084	{ Mips::D20_64, 52U },
3085	{ Mips::D21_64, 53U },	3085	{ Mips::D21_64, 53U },
3086	{ Mips::D22_64, 54U },	3086	{ Mips::D22_64, 54U },
3087	{ Mips::D23_64, 55U },	3087	{ Mips::D23_64, 55U },
3088	{ Mips::D24_64, 56U },	3088	{ Mips::D24_64, 56U },
3089	{ Mips::D25_64, 57U },	3089	{ Mips::D25_64, 57U },
3090	{ Mips::D26_64, 58U },	3090	{ Mips::D26_64, 58U },
3091	{ Mips::D27_64, 59U },	3091	{ Mips::D27_64, 59U },
3092	{ Mips::D28_64, 60U },	3092	{ Mips::D28_64, 60U },
3093	{ Mips::D29_64, 61U },	3093	{ Mips::D29_64, 61U },
3094	{ Mips::D30_64, 62U },	3094	{ Mips::D30_64, 62U },
3095	{ Mips::D31_64, 63U },	3095	{ Mips::D31_64, 63U },
3096	{ Mips::K0_64, 26U },	3096	{ Mips::K0_64, 26U },
3097	{ Mips::K1_64, 27U },	3097	{ Mips::K1_64, 27U },
3098	{ Mips::S0_64, 16U },	3098	{ Mips::S0_64, 16U },
3099	{ Mips::S1_64, 17U },	3099	{ Mips::S1_64, 17U },
3100	{ Mips::S2_64, 18U },	3100	{ Mips::S2_64, 18U },
3101	{ Mips::S3_64, 19U },	3101	{ Mips::S3_64, 19U },
3102	{ Mips::S4_64, 20U },	3102	{ Mips::S4_64, 20U },
3103	{ Mips::S5_64, 21U },	3103	{ Mips::S5_64, 21U },
3104	{ Mips::S6_64, 22U },	3104	{ Mips::S6_64, 22U },
3105	{ Mips::S7_64, 23U },	3105	{ Mips::S7_64, 23U },
3106	{ Mips::T0_64, 8U },	3106	{ Mips::T0_64, 8U },
3107	{ Mips::T1_64, 9U },	3107	{ Mips::T1_64, 9U },
3108	{ Mips::T2_64, 10U },	3108	{ Mips::T2_64, 10U },
3109	{ Mips::T3_64, 11U },	3109	{ Mips::T3_64, 11U },
3110	{ Mips::T4_64, 12U },	3110	{ Mips::T4_64, 12U },
3111	{ Mips::T5_64, 13U },	3111	{ Mips::T5_64, 13U },
3112	{ Mips::T6_64, 14U },	3112	{ Mips::T6_64, 14U },
3113	{ Mips::T7_64, 15U },	3113	{ Mips::T7_64, 15U },
3114	{ Mips::T8_64, 24U },	3114	{ Mips::T8_64, 24U },
3115	{ Mips::T9_64, 25U },	3115	{ Mips::T9_64, 25U },
3116	{ Mips::V0_64, 2U },	3116	{ Mips::V0_64, 2U },
3117	{ Mips::V1_64, 3U },	3117	{ Mips::V1_64, 3U },
3118	};	3118	};
3119	extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);	3119	extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);
3120		3120
3121	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {	3121	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
3122	{ Mips::AT, 1U },	3122	{ Mips::AT, 1U },
3123	{ Mips::FP, 30U },	3123	{ Mips::FP, 30U },
3124	{ Mips::GP, 28U },	3124	{ Mips::GP, 28U },
3125	{ Mips::RA, 31U },	3125	{ Mips::RA, 31U },
3126	{ Mips::SP, 29U },	3126	{ Mips::SP, 29U },
3127	{ Mips::ZERO, 0U },	3127	{ Mips::ZERO, 0U },
3128	{ Mips::A0, 4U },	3128	{ Mips::A0, 4U },
3129	{ Mips::A1, 5U },	3129	{ Mips::A1, 5U },
3130	{ Mips::A2, 6U },	3130	{ Mips::A2, 6U },
3131	{ Mips::A3, 7U },	3131	{ Mips::A3, 7U },
3132	{ Mips::AT_64, 1U },	3132	{ Mips::AT_64, 1U },
3133	{ Mips::F0, 32U },	3133	{ Mips::F0, 32U },
3134	{ Mips::F1, 33U },	3134	{ Mips::F1, 33U },
3135	{ Mips::F2, 34U },	3135	{ Mips::F2, 34U },
3136	{ Mips::F3, 35U },	3136	{ Mips::F3, 35U },
3137	{ Mips::F4, 36U },	3137	{ Mips::F4, 36U },
3138	{ Mips::F5, 37U },	3138	{ Mips::F5, 37U },
3139	{ Mips::F6, 38U },	3139	{ Mips::F6, 38U },
3140	{ Mips::F7, 39U },	3140	{ Mips::F7, 39U },
3141	{ Mips::F8, 40U },	3141	{ Mips::F8, 40U },
3142	{ Mips::F9, 41U },	3142	{ Mips::F9, 41U },
3143	{ Mips::F10, 42U },	3143	{ Mips::F10, 42U },
3144	{ Mips::F11, 43U },	3144	{ Mips::F11, 43U },
3145	{ Mips::F12, 44U },	3145	{ Mips::F12, 44U },
3146	{ Mips::F13, 45U },	3146	{ Mips::F13, 45U },
3147	{ Mips::F14, 46U },	3147	{ Mips::F14, 46U },
3148	{ Mips::F15, 47U },	3148	{ Mips::F15, 47U },
3149	{ Mips::F16, 48U },	3149	{ Mips::F16, 48U },
3150	{ Mips::F17, 49U },	3150	{ Mips::F17, 49U },
3151	{ Mips::F18, 50U },	3151	{ Mips::F18, 50U },
3152	{ Mips::F19, 51U },	3152	{ Mips::F19, 51U },
3153	{ Mips::F20, 52U },	3153	{ Mips::F20, 52U },
3154	{ Mips::F21, 53U },	3154	{ Mips::F21, 53U },
3155	{ Mips::F22, 54U },	3155	{ Mips::F22, 54U },
3156	{ Mips::F23, 55U },	3156	{ Mips::F23, 55U },
3157	{ Mips::F24, 56U },	3157	{ Mips::F24, 56U },
3158	{ Mips::F25, 57U },	3158	{ Mips::F25, 57U },
3159	{ Mips::F26, 58U },	3159	{ Mips::F26, 58U },
3160	{ Mips::F27, 59U },	3160	{ Mips::F27, 59U },
3161	{ Mips::F28, 60U },	3161	{ Mips::F28, 60U },
3162	{ Mips::F29, 61U },	3162	{ Mips::F29, 61U },
3163	{ Mips::F30, 62U },	3163	{ Mips::F30, 62U },
3164	{ Mips::F31, 63U },	3164	{ Mips::F31, 63U },
3165	{ Mips::FP_64, 30U },	3165	{ Mips::FP_64, 30U },
3166	{ Mips::F_HI0, 32U },	3166	{ Mips::F_HI0, 32U },
3167	{ Mips::F_HI1, 33U },	3167	{ Mips::F_HI1, 33U },
3168	{ Mips::F_HI2, 34U },	3168	{ Mips::F_HI2, 34U },
3169	{ Mips::F_HI3, 35U },	3169	{ Mips::F_HI3, 35U },
3170	{ Mips::F_HI4, 36U },	3170	{ Mips::F_HI4, 36U },
3171	{ Mips::F_HI5, 37U },	3171	{ Mips::F_HI5, 37U },
3172	{ Mips::F_HI6, 38U },	3172	{ Mips::F_HI6, 38U },
3173	{ Mips::F_HI7, 39U },	3173	{ Mips::F_HI7, 39U },
3174	{ Mips::F_HI8, 40U },	3174	{ Mips::F_HI8, 40U },
3175	{ Mips::F_HI9, 41U },	3175	{ Mips::F_HI9, 41U },
3176	{ Mips::F_HI10, 42U },	3176	{ Mips::F_HI10, 42U },
3177	{ Mips::F_HI11, 43U },	3177	{ Mips::F_HI11, 43U },
3178	{ Mips::F_HI12, 44U },	3178	{ Mips::F_HI12, 44U },
3179	{ Mips::F_HI13, 45U },	3179	{ Mips::F_HI13, 45U },
3180	{ Mips::F_HI14, 46U },	3180	{ Mips::F_HI14, 46U },
3181	{ Mips::F_HI15, 47U },	3181	{ Mips::F_HI15, 47U },
3182	{ Mips::F_HI16, 48U },	3182	{ Mips::F_HI16, 48U },
3183	{ Mips::F_HI17, 49U },	3183	{ Mips::F_HI17, 49U },
3184	{ Mips::F_HI18, 50U },	3184	{ Mips::F_HI18, 50U },
3185	{ Mips::F_HI19, 51U },	3185	{ Mips::F_HI19, 51U },
3186	{ Mips::F_HI20, 52U },	3186	{ Mips::F_HI20, 52U },
3187	{ Mips::F_HI21, 53U },	3187	{ Mips::F_HI21, 53U },
3188	{ Mips::F_HI22, 54U },	3188	{ Mips::F_HI22, 54U },
3189	{ Mips::F_HI23, 55U },	3189	{ Mips::F_HI23, 55U },
3190	{ Mips::F_HI24, 56U },	3190	{ Mips::F_HI24, 56U },
3191	{ Mips::F_HI25, 57U },	3191	{ Mips::F_HI25, 57U },
3192	{ Mips::F_HI26, 58U },	3192	{ Mips::F_HI26, 58U },
3193	{ Mips::F_HI27, 59U },	3193	{ Mips::F_HI27, 59U },
3194	{ Mips::F_HI28, 60U },	3194	{ Mips::F_HI28, 60U },
3195	{ Mips::F_HI29, 61U },	3195	{ Mips::F_HI29, 61U },
3196	{ Mips::F_HI30, 62U },	3196	{ Mips::F_HI30, 62U },
3197	{ Mips::F_HI31, 63U },	3197	{ Mips::F_HI31, 63U },
3198	{ Mips::GP_64, 28U },	3198	{ Mips::GP_64, 28U },
3199	{ Mips::HI0, 64U },	3199	{ Mips::HI0, 64U },
3200	{ Mips::HI1, 176U },	3200	{ Mips::HI1, 176U },
3201	{ Mips::HI2, 178U },	3201	{ Mips::HI2, 178U },
3202	{ Mips::HI3, 180U },	3202	{ Mips::HI3, 180U },
3203	{ Mips::K0, 26U },	3203	{ Mips::K0, 26U },
3204	{ Mips::K1, 27U },	3204	{ Mips::K1, 27U },
3205	{ Mips::LO0, 65U },	3205	{ Mips::LO0, 65U },
3206	{ Mips::LO1, 177U },	3206	{ Mips::LO1, 177U },
3207	{ Mips::LO2, 179U },	3207	{ Mips::LO2, 179U },
3208	{ Mips::LO3, 181U },	3208	{ Mips::LO3, 181U },
3209	{ Mips::RA_64, 31U },	3209	{ Mips::RA_64, 31U },
3210	{ Mips::S0, 16U },	3210	{ Mips::S0, 16U },
3211	{ Mips::S1, 17U },	3211	{ Mips::S1, 17U },
3212	{ Mips::S2, 18U },	3212	{ Mips::S2, 18U },
3213	{ Mips::S3, 19U },	3213	{ Mips::S3, 19U },
3214	{ Mips::S4, 20U },	3214	{ Mips::S4, 20U },
3215	{ Mips::S5, 21U },	3215	{ Mips::S5, 21U },
3216	{ Mips::S6, 22U },	3216	{ Mips::S6, 22U },
3217	{ Mips::S7, 23U },	3217	{ Mips::S7, 23U },
3218	{ Mips::SP_64, 29U },	3218	{ Mips::SP_64, 29U },
3219	{ Mips::T0, 8U },	3219	{ Mips::T0, 8U },
3220	{ Mips::T1, 9U },	3220	{ Mips::T1, 9U },
3221	{ Mips::T2, 10U },	3221	{ Mips::T2, 10U },
3222	{ Mips::T3, 11U },	3222	{ Mips::T3, 11U },
3223	{ Mips::T4, 12U },	3223	{ Mips::T4, 12U },
3224	{ Mips::T5, 13U },	3224	{ Mips::T5, 13U },
3225	{ Mips::T6, 14U },	3225	{ Mips::T6, 14U },
3226	{ Mips::T7, 15U },	3226	{ Mips::T7, 15U },
3227	{ Mips::T8, 24U },	3227	{ Mips::T8, 24U },
3228	{ Mips::T9, 25U },	3228	{ Mips::T9, 25U },
3229	{ Mips::V0, 2U },	3229	{ Mips::V0, 2U },
3230	{ Mips::V1, 3U },	3230	{ Mips::V1, 3U },
3231	{ Mips::W0, 32U },	3231	{ Mips::W0, 32U },
3232	{ Mips::W1, 33U },	3232	{ Mips::W1, 33U },
3233	{ Mips::W2, 34U },	3233	{ Mips::W2, 34U },
3234	{ Mips::W3, 35U },	3234	{ Mips::W3, 35U },
3235	{ Mips::W4, 36U },	3235	{ Mips::W4, 36U },
3236	{ Mips::W5, 37U },	3236	{ Mips::W5, 37U },
3237	{ Mips::W6, 38U },	3237	{ Mips::W6, 38U },
3238	{ Mips::W7, 39U },	3238	{ Mips::W7, 39U },
3239	{ Mips::W8, 40U },	3239	{ Mips::W8, 40U },
3240	{ Mips::W9, 41U },	3240	{ Mips::W9, 41U },
3241	{ Mips::W10, 42U },	3241	{ Mips::W10, 42U },
3242	{ Mips::W11, 43U },	3242	{ Mips::W11, 43U },
3243	{ Mips::W12, 44U },	3243	{ Mips::W12, 44U },
3244	{ Mips::W13, 45U },	3244	{ Mips::W13, 45U },
3245	{ Mips::W14, 46U },	3245	{ Mips::W14, 46U },
3246	{ Mips::W15, 47U },	3246	{ Mips::W15, 47U },
3247	{ Mips::W16, 48U },	3247	{ Mips::W16, 48U },
3248	{ Mips::W17, 49U },	3248	{ Mips::W17, 49U },
3249	{ Mips::W18, 50U },	3249	{ Mips::W18, 50U },
3250	{ Mips::W19, 51U },	3250	{ Mips::W19, 51U },
3251	{ Mips::W20, 52U },	3251	{ Mips::W20, 52U },
3252	{ Mips::W21, 53U },	3252	{ Mips::W21, 53U },
3253	{ Mips::W22, 54U },	3253	{ Mips::W22, 54U },
3254	{ Mips::W23, 55U },	3254	{ Mips::W23, 55U },
3255	{ Mips::W24, 56U },	3255	{ Mips::W24, 56U },
3256	{ Mips::W25, 57U },	3256	{ Mips::W25, 57U },
3257	{ Mips::W26, 58U },	3257	{ Mips::W26, 58U },
3258	{ Mips::W27, 59U },	3258	{ Mips::W27, 59U },
3259	{ Mips::W28, 60U },	3259	{ Mips::W28, 60U },
3260	{ Mips::W29, 61U },	3260	{ Mips::W29, 61U },
3261	{ Mips::W30, 62U },	3261	{ Mips::W30, 62U },
3262	{ Mips::W31, 63U },	3262	{ Mips::W31, 63U },
3263	{ Mips::ZERO_64, 0U },	3263	{ Mips::ZERO_64, 0U },
3264	{ Mips::A0_64, 4U },	3264	{ Mips::A0_64, 4U },
3265	{ Mips::A1_64, 5U },	3265	{ Mips::A1_64, 5U },
3266	{ Mips::A2_64, 6U },	3266	{ Mips::A2_64, 6U },
3267	{ Mips::A3_64, 7U },	3267	{ Mips::A3_64, 7U },
3268	{ Mips::D0_64, 32U },	3268	{ Mips::D0_64, 32U },
3269	{ Mips::D1_64, 33U },	3269	{ Mips::D1_64, 33U },
3270	{ Mips::D2_64, 34U },	3270	{ Mips::D2_64, 34U },
3271	{ Mips::D3_64, 35U },	3271	{ Mips::D3_64, 35U },
3272	{ Mips::D4_64, 36U },	3272	{ Mips::D4_64, 36U },
3273	{ Mips::D5_64, 37U },	3273	{ Mips::D5_64, 37U },
3274	{ Mips::D6_64, 38U },	3274	{ Mips::D6_64, 38U },
3275	{ Mips::D7_64, 39U },	3275	{ Mips::D7_64, 39U },
3276	{ Mips::D8_64, 40U },	3276	{ Mips::D8_64, 40U },
3277	{ Mips::D9_64, 41U },	3277	{ Mips::D9_64, 41U },
3278	{ Mips::D10_64, 42U },	3278	{ Mips::D10_64, 42U },
3279	{ Mips::D11_64, 43U },	3279	{ Mips::D11_64, 43U },
3280	{ Mips::D12_64, 44U },	3280	{ Mips::D12_64, 44U },
3281	{ Mips::D13_64, 45U },	3281	{ Mips::D13_64, 45U },
3282	{ Mips::D14_64, 46U },	3282	{ Mips::D14_64, 46U },
3283	{ Mips::D15_64, 47U },	3283	{ Mips::D15_64, 47U },
3284	{ Mips::D16_64, 48U },	3284	{ Mips::D16_64, 48U },
3285	{ Mips::D17_64, 49U },	3285	{ Mips::D17_64, 49U },
3286	{ Mips::D18_64, 50U },	3286	{ Mips::D18_64, 50U },
3287	{ Mips::D19_64, 51U },	3287	{ Mips::D19_64, 51U },
3288	{ Mips::D20_64, 52U },	3288	{ Mips::D20_64, 52U },
3289	{ Mips::D21_64, 53U },	3289	{ Mips::D21_64, 53U },
3290	{ Mips::D22_64, 54U },	3290	{ Mips::D22_64, 54U },
3291	{ Mips::D23_64, 55U },	3291	{ Mips::D23_64, 55U },
3292	{ Mips::D24_64, 56U },	3292	{ Mips::D24_64, 56U },
3293	{ Mips::D25_64, 57U },	3293	{ Mips::D25_64, 57U },
3294	{ Mips::D26_64, 58U },	3294	{ Mips::D26_64, 58U },
3295	{ Mips::D27_64, 59U },	3295	{ Mips::D27_64, 59U },
3296	{ Mips::D28_64, 60U },	3296	{ Mips::D28_64, 60U },
3297	{ Mips::D29_64, 61U },	3297	{ Mips::D29_64, 61U },
3298	{ Mips::D30_64, 62U },	3298	{ Mips::D30_64, 62U },
3299	{ Mips::D31_64, 63U },	3299	{ Mips::D31_64, 63U },
3300	{ Mips::K0_64, 26U },	3300	{ Mips::K0_64, 26U },
3301	{ Mips::K1_64, 27U },	3301	{ Mips::K1_64, 27U },
3302	{ Mips::S0_64, 16U },	3302	{ Mips::S0_64, 16U },
3303	{ Mips::S1_64, 17U },	3303	{ Mips::S1_64, 17U },
3304	{ Mips::S2_64, 18U },	3304	{ Mips::S2_64, 18U },
3305	{ Mips::S3_64, 19U },	3305	{ Mips::S3_64, 19U },
3306	{ Mips::S4_64, 20U },	3306	{ Mips::S4_64, 20U },
3307	{ Mips::S5_64, 21U },	3307	{ Mips::S5_64, 21U },
3308	{ Mips::S6_64, 22U },	3308	{ Mips::S6_64, 22U },
3309	{ Mips::S7_64, 23U },	3309	{ Mips::S7_64, 23U },
3310	{ Mips::T0_64, 8U },	3310	{ Mips::T0_64, 8U },
3311	{ Mips::T1_64, 9U },	3311	{ Mips::T1_64, 9U },
3312	{ Mips::T2_64, 10U },	3312	{ Mips::T2_64, 10U },
3313	{ Mips::T3_64, 11U },	3313	{ Mips::T3_64, 11U },
3314	{ Mips::T4_64, 12U },	3314	{ Mips::T4_64, 12U },
3315	{ Mips::T5_64, 13U },	3315	{ Mips::T5_64, 13U },
3316	{ Mips::T6_64, 14U },	3316	{ Mips::T6_64, 14U },
3317	{ Mips::T7_64, 15U },	3317	{ Mips::T7_64, 15U },
3318	{ Mips::T8_64, 24U },	3318	{ Mips::T8_64, 24U },
3319	{ Mips::T9_64, 25U },	3319	{ Mips::T9_64, 25U },
3320	{ Mips::V0_64, 2U },	3320	{ Mips::V0_64, 2U },
3321	{ Mips::V1_64, 3U },	3321	{ Mips::V1_64, 3U },
3322	};	3322	};
3323	extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);	3323	extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);
3324		3324
3325	extern const uint16_t MipsRegEncodingTable[] = {	3325	extern const uint16_t MipsRegEncodingTable[] = {
3326	0,	3326	0,
3327	1,	3327	1,
3328	0,	3328	0,
3329	0,	3329	0,
3330	0,	3330	0,
3331	0,	3331	0,
3332	0,	3332	0,
3333	0,	3333	0,
3334	30,	3334	30,
3335	28,	3335	28,
3336	2,	3336	2,
3337	1,	3337	1,
3338	0,	3338	0,
3339	6,	3339	6,
3340	4,	3340	4,
3341	5,	3341	5,
3342	3,	3342	3,
3343	7,	3343	7,
3344	0,	3344	0,
3345	31,	3345	31,
3346	29,	3346	29,
3347	0,	3347	0,
3348	4,	3348	4,
3349	5,	3349	5,
3350	6,	3350	6,
3351	7,	3351	7,
3352	0,	3352	0,
3353	1,	3353	1,
3354	2,	3354	2,
3355	3,	3355	3,
3356	1,	3356	1,
3357	0,	3357	0,
3358	1,	3358	1,
3359	2,	3359	2,
3360	3,	3360	3,
3361	4,	3361	4,
3362	5,	3362	5,
3363	6,	3363	6,
3364	7,	3364	7,
3365	8,	3365	8,
3366	9,	3366	9,
3367	0,	3367	0,
3368	1,	3368	1,
3369	2,	3369	2,
3370	3,	3370	3,
3371	4,	3371	4,
3372	5,	3372	5,
3373	6,	3373	6,
3374	7,	3374	7,
3375	8,	3375	8,
3376	9,	3376	9,
3377	0,	3377	0,
3378	1,	3378	1,
3379	2,	3379	2,
3380	3,	3380	3,
3381	4,	3381	4,
3382	5,	3382	5,
3383	6,	3383	6,
3384	7,	3384	7,
3385	8,	3385	8,
3386	9,	3386	9,
3387	10,	3387	10,
3388	11,	3388	11,
3389	12,	3389	12,
3390	13,	3390	13,
3391	14,	3391	14,
3392	15,	3392	15,
3393	16,	3393	16,
3394	17,	3394	17,
3395	18,	3395	18,
3396	19,	3396	19,
3397	20,	3397	20,
3398	21,	3398	21,
3399	22,	3399	22,
3400	23,	3400	23,
3401	24,	3401	24,
3402	25,	3402	25,
3403	26,	3403	26,
3404	27,	3404	27,
3405	28,	3405	28,
3406	29,	3406	29,
3407	30,	3407	30,
3408	31,	3408	31,
3409	10,	3409	10,
3410	11,	3410	11,
3411	12,	3411	12,
3412	13,	3412	13,
3413	14,	3413	14,
3414	15,	3414	15,
3415	16,	3415	16,
3416	17,	3416	17,
3417	18,	3417	18,
3418	19,	3418	19,
3419	20,	3419	20,
3420	21,	3420	21,
3421	22,	3421	22,
3422	23,	3422	23,
3423	24,	3423	24,
3424	25,	3424	25,
3425	26,	3425	26,
3426	27,	3426	27,
3427	28,	3427	28,
3428	29,	3428	29,
3429	30,	3429	30,
3430	31,	3430	31,
3431	10,	3431	10,
3432	11,	3432	11,
3433	12,	3433	12,
3434	13,	3434	13,
3435	14,	3435	14,
3436	15,	3436	15,
3437	16,	3437	16,
3438	17,	3438	17,
3439	18,	3439	18,
3440	19,	3440	19,
3441	20,	3441	20,
3442	21,	3442	21,
3443	22,	3443	22,
3444	23,	3444	23,
3445	24,	3445	24,
3446	25,	3446	25,
3447	26,	3447	26,
3448	27,	3448	27,
3449	28,	3449	28,
3450	29,	3450	29,
3451	30,	3451	30,
3452	31,	3452	31,
3453	0,	3453	0,
3454	2,	3454	2,
3455	4,	3455	4,
3456	6,	3456	6,
3457	8,	3457	8,
3458	10,	3458	10,
3459	12,	3459	12,
3460	14,	3460	14,
3461	16,	3461	16,
3462	18,	3462	18,
3463	20,	3463	20,
3464	22,	3464	22,
3465	24,	3465	24,
3466	26,	3466	26,
3467	28,	3467	28,
3468	30,	3468	30,
3469	0,	3469	0,
3470	0,	3470	0,
3471	0,	3471	0,
3472	0,	3472	0,
3473	0,	3473	0,
3474	1,	3474	1,
3475	2,	3475	2,
3476	3,	3476	3,
3477	4,	3477	4,
3478	5,	3478	5,
3479	6,	3479	6,
3480	7,	3480	7,
3481	8,	3481	8,
3482	9,	3482	9,
3483	10,	3483	10,
3484	11,	3484	11,
3485	12,	3485	12,
3486	13,	3486	13,
3487	14,	3487	14,
3488	15,	3488	15,
3489	16,	3489	16,
3490	17,	3490	17,
3491	18,	3491	18,
3492	19,	3492	19,
3493	20,	3493	20,
3494	21,	3494	21,
3495	22,	3495	22,
3496	23,	3496	23,
3497	24,	3497	24,
3498	25,	3498	25,
3499	26,	3499	26,
3500	27,	3500	27,
3501	28,	3501	28,
3502	29,	3502	29,
3503	30,	3503	30,
3504	31,	3504	31,
3505	0,	3505	0,
3506	1,	3506	1,
3507	2,	3507	2,
3508	3,	3508	3,
3509	4,	3509	4,
3510	5,	3510	5,
3511	6,	3511	6,
3512	7,	3512	7,
3513	0,	3513	0,
3514	1,	3514	1,
3515	2,	3515	2,
3516	3,	3516	3,
3517	4,	3517	4,
3518	5,	3518	5,
3519	6,	3519	6,
3520	7,	3520	7,
3521	8,	3521	8,
3522	9,	3522	9,
3523	10,	3523	10,
3524	11,	3524	11,
3525	12,	3525	12,
3526	13,	3526	13,
3527	14,	3527	14,
3528	15,	3528	15,
3529	16,	3529	16,
3530	17,	3530	17,
3531	18,	3531	18,
3532	19,	3532	19,
3533	20,	3533	20,
3534	21,	3534	21,
3535	22,	3535	22,
3536	23,	3536	23,
3537	24,	3537	24,
3538	25,	3538	25,
3539	26,	3539	26,
3540	27,	3540	27,
3541	28,	3541	28,
3542	29,	3542	29,
3543	30,	3543	30,
3544	31,	3544	31,
3545	30,	3545	30,
3546	0,	3546	0,
3547	1,	3547	1,
3548	2,	3548	2,
3549	3,	3549	3,
3550	4,	3550	4,
3551	5,	3551	5,
3552	6,	3552	6,
3553	7,	3553	7,
3554	8,	3554	8,
3555	9,	3555	9,
3556	10,	3556	10,
3557	11,	3557	11,
3558	12,	3558	12,
3559	13,	3559	13,
3560	14,	3560	14,
3561	15,	3561	15,
3562	16,	3562	16,
3563	17,	3563	17,
3564	18,	3564	18,
3565	19,	3565	19,
3566	20,	3566	20,
3567	21,	3567	21,
3568	22,	3568	22,
3569	23,	3569	23,
3570	24,	3570	24,
3571	25,	3571	25,
3572	26,	3572	26,
3573	27,	3573	27,
3574	28,	3574	28,
3575	29,	3575	29,
3576	30,	3576	30,
3577	31,	3577	31,
3578	28,	3578	28,
3579	0,	3579	0,
3580	1,	3580	1,
3581	2,	3581	2,
3582	3,	3582	3,
3583	0,	3583	0,
3584	1,	3584	1,
3585	2,	3585	2,
3586	3,	3586	3,
3587	4,	3587	4,
3588	5,	3588	5,
3589	6,	3589	6,
3590	7,	3590	7,
3591	8,	3591	8,
3592	9,	3592	9,
3593	10,	3593	10,
3594	11,	3594	11,
3595	12,	3595	12,
3596	13,	3596	13,
3597	14,	3597	14,
3598	15,	3598	15,
3599	16,	3599	16,
3600	17,	3600	17,
3601	18,	3601	18,
3602	19,	3602	19,
3603	20,	3603	20,
3604	21,	3604	21,
3605	22,	3605	22,
3606	23,	3606	23,
3607	24,	3607	24,
3608	25,	3608	25,
3609	26,	3609	26,
3610	27,	3610	27,
3611	28,	3611	28,
3612	29,	3612	29,
3613	30,	3613	30,
3614	31,	3614	31,
3615	26,	3615	26,
3616	27,	3616	27,
3617	0,	3617	0,
3618	1,	3618	1,
3619	2,	3619	2,
3620	3,	3620	3,
3621	0,	3621	0,
3622	1,	3622	1,
3623	2,	3623	2,
3624	8,	3624	8,
3625	9,	3625	9,
3626	10,	3626	10,
3627	11,	3627	11,
3628	12,	3628	12,
3629	13,	3629	13,
3630	14,	3630	14,
3631	15,	3631	15,
3632	16,	3632	16,
3633	17,	3633	17,
3634	18,	3634	18,
3635	19,	3635	19,
3636	20,	3636	20,
3637	21,	3637	21,
3638	22,	3638	22,
3639	23,	3639	23,
3640	24,	3640	24,
3641	25,	3641	25,
3642	26,	3642	26,
3643	27,	3643	27,
3644	28,	3644	28,
3645	29,	3645	29,
3646	30,	3646	30,
3647	31,	3647	31,
3648	0,	3648	0,
3649	1,	3649	1,
3650	2,	3650	2,
3651	31,	3651	31,
3652	16,	3652	16,
3653	17,	3653	17,
3654	18,	3654	18,
3655	19,	3655	19,
3656	20,	3656	20,
3657	21,	3657	21,
3658	22,	3658	22,
3659	23,	3659	23,
3660	29,	3660	29,
3661	8,	3661	8,
3662	9,	3662	9,
3663	10,	3663	10,
3664	11,	3664	11,
3665	12,	3665	12,
3666	13,	3666	13,
3667	14,	3667	14,
3668	15,	3668	15,
3669	24,	3669	24,
3670	25,	3670	25,
3671	2,	3671	2,
3672	3,	3672	3,
3673	0,	3673	0,
3674	1,	3674	1,
3675	2,	3675	2,
3676	3,	3676	3,
3677	4,	3677	4,
3678	5,	3678	5,
3679	6,	3679	6,
3680	7,	3680	7,
3681	8,	3681	8,
3682	9,	3682	9,
3683	10,	3683	10,
3684	11,	3684	11,
3685	12,	3685	12,
3686	13,	3686	13,
3687	14,	3687	14,
3688	15,	3688	15,
3689	16,	3689	16,
3690	17,	3690	17,
3691	18,	3691	18,
3692	19,	3692	19,
3693	20,	3693	20,
3694	21,	3694	21,
3695	22,	3695	22,
3696	23,	3696	23,
3697	24,	3697	24,
3698	25,	3698	25,
3699	26,	3699	26,
3700	27,	3700	27,
3701	28,	3701	28,
3702	29,	3702	29,
3703	30,	3703	30,
3704	31,	3704	31,
3705	0,	3705	0,
3706	4,	3706	4,
3707	5,	3707	5,
3708	6,	3708	6,
3709	7,	3709	7,
3710	0,	3710	0,
3711	0,	3711	0,
3712	1,	3712	1,
3713	2,	3713	2,
3714	3,	3714	3,
3715	4,	3715	4,
3716	5,	3716	5,
3717	6,	3717	6,
3718	7,	3718	7,
3719	8,	3719	8,
3720	9,	3720	9,
3721	10,	3721	10,
3722	11,	3722	11,
3723	12,	3723	12,
3724	13,	3724	13,
3725	14,	3725	14,
3726	15,	3726	15,
3727	16,	3727	16,
3728	17,	3728	17,
3729	18,	3729	18,
3730	19,	3730	19,
3731	20,	3731	20,
3732	21,	3732	21,
3733	22,	3733	22,
3734	23,	3734	23,
3735	24,	3735	24,
3736	25,	3736	25,
3737	26,	3737	26,
3738	27,	3738	27,
3739	28,	3739	28,
3740	29,	3740	29,
3741	30,	3741	30,
3742	31,	3742	31,
3743	0,	3743	0,
3744	0,	3744	0,
3745	26,	3745	26,
3746	27,	3746	27,
3747	0,	3747	0,
3748	16,	3748	16,
3749	17,	3749	17,
3750	18,	3750	18,
3751	19,	3751	19,
3752	20,	3752	20,
3753	21,	3753	21,
3754	22,	3754	22,
3755	23,	3755	23,
3756	8,	3756	8,
3757	9,	3757	9,
3758	10,	3758	10,
3759	11,	3759	11,
3760	12,	3760	12,
3761	13,	3761	13,
3762	14,	3762	14,
3763	15,	3763	15,
3764	24,	3764	24,
3765	25,	3765	25,
3766	2,	3766	2,
3767	3,	3767	3,
3768	};	3768	};
3769	static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {	3769	static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
3770	RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,	3770	RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
3771	MipsSubRegIdxRanges, MipsRegEncodingTable);	3771	MipsSubRegIdxRanges, MipsRegEncodingTable);
3772		3772
3773	switch (DwarfFlavour) {	3773	switch (DwarfFlavour) {
3774	default:	3774	default:
3775	llvm_unreachable("Unknown DWARF flavour");	3775	llvm_unreachable("Unknown DWARF flavour");
3776	case 0:	3776	case 0:
3777	RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	3777	RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
3778	break;	3778	break;
3779	}	3779	}
3780	switch (EHFlavour) {	3780	switch (EHFlavour) {
3781	default:	3781	default:
3782	llvm_unreachable("Unknown DWARF flavour");	3782	llvm_unreachable("Unknown DWARF flavour");
3783	case 0:	3783	case 0:
3784	RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	3784	RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
3785	break;	3785	break;
3786	}	3786	}
3787	switch (DwarfFlavour) {	3787	switch (DwarfFlavour) {
3788	default:	3788	default:
3789	llvm_unreachable("Unknown DWARF flavour");	3789	llvm_unreachable("Unknown DWARF flavour");
3790	case 0:	3790	case 0:
3791	RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	3791	RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
3792	break;	3792	break;
3793	}	3793	}
3794	switch (EHFlavour) {	3794	switch (EHFlavour) {
3795	default:	3795	default:
3796	llvm_unreachable("Unknown DWARF flavour");	3796	llvm_unreachable("Unknown DWARF flavour");
3797	case 0:	3797	case 0:
3798	RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	3798	RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
3799	break;	3799	break;
3800	}	3800	}
3801	}	3801	}
3802		3802
3803	} // end namespace llvm	3803	} // end namespace llvm
3804		3804
3805	#endif // GET_REGINFO_MC_DESC	3805	#endif // GET_REGINFO_MC_DESC
3806		3806
3807	/===- TableGen'erated file -------------------------------------- C++ --===\	3807	/===- TableGen'erated file -------------------------------------- C++ --===\
3808	\|* *\|	3808	\|* *\|
3809	\|* Register Information Header Fragment *\|	3809	\|* Register Information Header Fragment *\|
3810	\|* *\|	3810	\|* *\|
3811	\|* Automatically generated file, do not edit! *\|	3811	\|* Automatically generated file, do not edit! *\|
3812	\|* *\|	3812	\|* *\|
3813	\===----------------------------------------------------------------------===/	3813	\===----------------------------------------------------------------------===/
3814		3814
3815		3815
3816	#ifdef GET_REGINFO_HEADER	3816	#ifdef GET_REGINFO_HEADER
3817	#undef GET_REGINFO_HEADER	3817	#undef GET_REGINFO_HEADER
3818		3818
3819	#include "llvm/CodeGen/TargetRegisterInfo.h"	3819	#include "llvm/CodeGen/TargetRegisterInfo.h"
3820		3820
3821	namespace llvm {	3821	namespace llvm {
3822		3822
3823	class MipsFrameLowering;	3823	class MipsFrameLowering;
3824		3824
3825	struct MipsGenRegisterInfo : public TargetRegisterInfo {	3825	struct MipsGenRegisterInfo : public TargetRegisterInfo {
3826	explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,	3826	explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
3827	unsigned PC = 0, unsigned HwMode = 0);	3827	unsigned PC = 0, unsigned HwMode = 0);
3828	unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;	3828	unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
3829	LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	3829	LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3830	LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	3830	LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
3831	const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;	3831	const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;
3832	const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;	3832	const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;
3833	const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;	3833	const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3834	unsigned getRegUnitWeight(unsigned RegUnit) const override;	3834	unsigned getRegUnitWeight(unsigned RegUnit) const override;
3835	unsigned getNumRegPressureSets() const override;	3835	unsigned getNumRegPressureSets() const override;
3836	const char *getRegPressureSetName(unsigned Idx) const override;	3836	const char *getRegPressureSetName(unsigned Idx) const override;
3837	unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;	3837	unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
3838	const int getRegClassPressureSets(const TargetRegisterClass RC) const override;	3838	const int getRegClassPressureSets(const TargetRegisterClass RC) const override;
3839	const int *getRegUnitPressureSets(unsigned RegUnit) const override;	3839	const int *getRegUnitPressureSets(unsigned RegUnit) const override;
3840	ArrayRef getRegMaskNames() const override;	3840	ArrayRef getRegMaskNames() const override;
3841	ArrayRef getRegMasks() const override;	3841	ArrayRef getRegMasks() const override;
3842	bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;	3842	bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
3843	bool isFixedRegister(const MachineFunction &, MCRegister) const override;	3843	bool isFixedRegister(const MachineFunction &, MCRegister) const override;
3844	bool isArgumentRegister(const MachineFunction &, MCRegister) const override;	3844	bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
3845	bool isConstantPhysReg(MCRegister PhysReg) const override final;	3845	bool isConstantPhysReg(MCRegister PhysReg) const override final;
3846	/// Devirtualized TargetFrameLowering.	3846	/// Devirtualized TargetFrameLowering.
3847	static const MipsFrameLowering *getFrameLowering(	3847	static const MipsFrameLowering *getFrameLowering(
3848	const MachineFunction &MF);	3848	const MachineFunction &MF);
3849	};	3849	};
3850		3850
3851	namespace Mips { // Register classes	3851	namespace Mips { // Register classes
3852	extern const TargetRegisterClass MSA128F16RegClass;	3852	extern const TargetRegisterClass MSA128F16RegClass;
3853	extern const TargetRegisterClass CCRRegClass;	3853	extern const TargetRegisterClass CCRRegClass;
3854	extern const TargetRegisterClass COP0RegClass;	3854	extern const TargetRegisterClass COP0RegClass;
3855	extern const TargetRegisterClass COP2RegClass;	3855	extern const TargetRegisterClass COP2RegClass;
3856	extern const TargetRegisterClass COP3RegClass;	3856	extern const TargetRegisterClass COP3RegClass;
3857	extern const TargetRegisterClass DSPRRegClass;	3857	extern const TargetRegisterClass DSPRRegClass;
3858	extern const TargetRegisterClass FGR32RegClass;	3858	extern const TargetRegisterClass FGR32RegClass;
3859	extern const TargetRegisterClass FGRCCRegClass;	3859	extern const TargetRegisterClass FGRCCRegClass;
3860	extern const TargetRegisterClass GPR32RegClass;	3860	extern const TargetRegisterClass GPR32RegClass;
3861	extern const TargetRegisterClass HWRegsRegClass;	3861	extern const TargetRegisterClass HWRegsRegClass;
3862	extern const TargetRegisterClass MSACtrlRegClass;	3862	extern const TargetRegisterClass MSACtrlRegClass;
3863	extern const TargetRegisterClass GPR32NONZERORegClass;	3863	extern const TargetRegisterClass GPR32NONZERORegClass;
3864	extern const TargetRegisterClass CPU16RegsPlusSPRegClass;	3864	extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3865	extern const TargetRegisterClass CPU16RegsRegClass;	3865	extern const TargetRegisterClass CPU16RegsRegClass;
3866	extern const TargetRegisterClass FCCRegClass;	3866	extern const TargetRegisterClass FCCRegClass;
3867	extern const TargetRegisterClass GPRMM16RegClass;	3867	extern const TargetRegisterClass GPRMM16RegClass;
3868	extern const TargetRegisterClass GPRMM16MovePRegClass;	3868	extern const TargetRegisterClass GPRMM16MovePRegClass;
3869	extern const TargetRegisterClass GPRMM16ZeroRegClass;	3869	extern const TargetRegisterClass GPRMM16ZeroRegClass;
3870	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;	3870	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3871	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;	3871	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3872	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;	3872	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3873	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;	3873	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3874	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;	3874	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3875	extern const TargetRegisterClass HI32DSPRegClass;	3875	extern const TargetRegisterClass HI32DSPRegClass;
3876	extern const TargetRegisterClass LO32DSPRegClass;	3876	extern const TargetRegisterClass LO32DSPRegClass;
3877	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	3877	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3878	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;	3878	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3879	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	3879	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3880	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	3880	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3881	extern const TargetRegisterClass CPURARegRegClass;	3881	extern const TargetRegisterClass CPURARegRegClass;
3882	extern const TargetRegisterClass CPUSPRegRegClass;	3882	extern const TargetRegisterClass CPUSPRegRegClass;
3883	extern const TargetRegisterClass DSPCCRegClass;	3883	extern const TargetRegisterClass DSPCCRegClass;
3884	extern const TargetRegisterClass GP32RegClass;	3884	extern const TargetRegisterClass GP32RegClass;
3885	extern const TargetRegisterClass GPR32ZERORegClass;	3885	extern const TargetRegisterClass GPR32ZERORegClass;
3886	extern const TargetRegisterClass HI32RegClass;	3886	extern const TargetRegisterClass HI32RegClass;
3887	extern const TargetRegisterClass LO32RegClass;	3887	extern const TargetRegisterClass LO32RegClass;
3888	extern const TargetRegisterClass SP32RegClass;	3888	extern const TargetRegisterClass SP32RegClass;
3889	extern const TargetRegisterClass FGR64RegClass;	3889	extern const TargetRegisterClass FGR64RegClass;
3890	extern const TargetRegisterClass GPR64RegClass;	3890	extern const TargetRegisterClass GPR64RegClass;
3891	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;	3891	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3892	extern const TargetRegisterClass AFGR64RegClass;	3892	extern const TargetRegisterClass AFGR64RegClass;
3893	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;	3893	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3894	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;	3894	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3895	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;	3895	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3896	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;	3896	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3897	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;	3897	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3898	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;	3898	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3899	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;	3899	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3900	extern const TargetRegisterClass ACC64DSPRegClass;	3900	extern const TargetRegisterClass ACC64DSPRegClass;
3901	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;	3901	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3902	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;	3902	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3903	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	3903	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3904	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;	3904	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3905	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	3905	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3906	extern const TargetRegisterClass OCTEON_MPLRegClass;	3906	extern const TargetRegisterClass OCTEON_MPLRegClass;
3907	extern const TargetRegisterClass OCTEON_PRegClass;	3907	extern const TargetRegisterClass OCTEON_PRegClass;
3908	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	3908	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3909	extern const TargetRegisterClass ACC64RegClass;	3909	extern const TargetRegisterClass ACC64RegClass;
3910	extern const TargetRegisterClass GP64RegClass;	3910	extern const TargetRegisterClass GP64RegClass;
3911	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;	3911	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3912	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;	3912	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3913	extern const TargetRegisterClass HI64RegClass;	3913	extern const TargetRegisterClass HI64RegClass;
3914	extern const TargetRegisterClass LO64RegClass;	3914	extern const TargetRegisterClass LO64RegClass;
3915	extern const TargetRegisterClass SP64RegClass;	3915	extern const TargetRegisterClass SP64RegClass;
3916	extern const TargetRegisterClass MSA128BRegClass;	3916	extern const TargetRegisterClass MSA128BRegClass;
3917	extern const TargetRegisterClass MSA128DRegClass;	3917	extern const TargetRegisterClass MSA128DRegClass;
3918	extern const TargetRegisterClass MSA128HRegClass;	3918	extern const TargetRegisterClass MSA128HRegClass;
3919	extern const TargetRegisterClass MSA128WRegClass;	3919	extern const TargetRegisterClass MSA128WRegClass;
3920	extern const TargetRegisterClass MSA128WEvensRegClass;	3920	extern const TargetRegisterClass MSA128WEvensRegClass;
3921	extern const TargetRegisterClass ACC128RegClass;	3921	extern const TargetRegisterClass ACC128RegClass;
3922	} // end namespace Mips	3922	} // end namespace Mips
3923		3923
3924	} // end namespace llvm	3924	} // end namespace llvm
3925		3925
3926	#endif // GET_REGINFO_HEADER	3926	#endif // GET_REGINFO_HEADER
3927		3927
3928	/===- TableGen'erated file -------------------------------------- C++ --===\	3928	/===- TableGen'erated file -------------------------------------- C++ --===\
3929	\|* *\|	3929	\|* *\|
3930	\|* Target Register and Register Classes Information *\|	3930	\|* Target Register and Register Classes Information *\|
3931	\|* *\|	3931	\|* *\|
3932	\|* Automatically generated file, do not edit! *\|	3932	\|* Automatically generated file, do not edit! *\|
3933	\|* *\|	3933	\|* *\|
3934	\===----------------------------------------------------------------------===/	3934	\===----------------------------------------------------------------------===/
3935		3935
3936		3936
3937	#ifdef GET_REGINFO_TARGET_DESC	3937	#ifdef GET_REGINFO_TARGET_DESC
3938	#undef GET_REGINFO_TARGET_DESC	3938	#undef GET_REGINFO_TARGET_DESC
3939		3939
3940	namespace llvm {	3940	namespace llvm {
3941		3941
3942	extern const MCRegisterClass MipsMCRegisterClasses[];	3942	extern const MCRegisterClass MipsMCRegisterClasses[];
3943		3943
3944	static const MVT::SimpleValueType VTLists[] = {	3944	static const MVT::SimpleValueType VTLists[] = {
3945	/* 0 */ MVT::i32, MVT::Other,	3945	/* 0 */ MVT::i32, MVT::Other,
3946	/* 2 */ MVT::i64, MVT::Other,	3946	/* 2 */ MVT::i64, MVT::Other,
3947	/* 4 */ MVT::f16, MVT::Other,	3947	/* 4 */ MVT::f16, MVT::Other,
3948	/* 6 */ MVT::f32, MVT::Other,	3948	/* 6 */ MVT::f32, MVT::Other,
3949	/* 8 */ MVT::f64, MVT::Other,	3949	/* 8 */ MVT::f64, MVT::Other,
3950	/* 10 */ MVT::v16i8, MVT::Other,	3950	/* 10 */ MVT::v16i8, MVT::Other,
3951	/* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,	3951	/* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
3952	/* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,	3952	/* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
3953	/* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,	3953	/* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
3954	/* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,	3954	/* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
3955	/* 24 */ MVT::Untyped, MVT::Other,	3955	/* 24 */ MVT::Untyped, MVT::Other,
3956	};	3956	};
3957		3957
3958	static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };	3958	static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
3959		3959
3960		3960
3961	static const LaneBitmask SubRegIndexLaneMaskTable[] = {	3961	static const LaneBitmask SubRegIndexLaneMaskTable[] = {
3962	LaneBitmask::getAll(),	3962	LaneBitmask::getAll(),
3963	LaneBitmask(0x0000000000000001), // sub_32	3963	LaneBitmask(0x0000000000000001), // sub_32
3964	LaneBitmask(0x0000000000000041), // sub_64	3964	LaneBitmask(0x0000000000000041), // sub_64
3965	LaneBitmask(0x0000000000000002), // sub_dsp16_19	3965	LaneBitmask(0x0000000000000002), // sub_dsp16_19
3966	LaneBitmask(0x0000000000000004), // sub_dsp20	3966	LaneBitmask(0x0000000000000004), // sub_dsp20
3967	LaneBitmask(0x0000000000000008), // sub_dsp21	3967	LaneBitmask(0x0000000000000008), // sub_dsp21
3968	LaneBitmask(0x0000000000000010), // sub_dsp22	3968	LaneBitmask(0x0000000000000010), // sub_dsp22
3969	LaneBitmask(0x0000000000000020), // sub_dsp23	3969	LaneBitmask(0x0000000000000020), // sub_dsp23
3970	LaneBitmask(0x0000000000000040), // sub_hi	3970	LaneBitmask(0x0000000000000040), // sub_hi
3971	LaneBitmask(0x0000000000000001), // sub_lo	3971	LaneBitmask(0x0000000000000001), // sub_lo
3972	LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32	3972	LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
3973	LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32	3973	LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
3974	};	3974	};
3975		3975
3976		3976
3977		3977
3978	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {	3978	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
3979	// Mode = 0 (Default)	3979	// Mode = 0 (Default)
3980	{ 16, 16, 128, VTLists+4 }, // MSA128F16	3980	{ 16, 16, 128, VTLists+4 }, // MSA128F16
3981	{ 32, 32, 32, VTLists+0 }, // CCR	3981	{ 32, 32, 32, VTLists+0 }, // CCR
3982	{ 32, 32, 32, VTLists+0 }, // COP0	3982	{ 32, 32, 32, VTLists+0 }, // COP0
3983	{ 32, 32, 32, VTLists+0 }, // COP2	3983	{ 32, 32, 32, VTLists+0 }, // COP2
3984	{ 32, 32, 32, VTLists+0 }, // COP3	3984	{ 32, 32, 32, VTLists+0 }, // COP3
3985	{ 32, 32, 32, VTLists+12 }, // DSPR	3985	{ 32, 32, 32, VTLists+12 }, // DSPR
3986	{ 32, 32, 32, VTLists+6 }, // FGR32	3986	{ 32, 32, 32, VTLists+6 }, // FGR32
3987	{ 32, 32, 32, VTLists+0 }, // FGRCC	3987	{ 32, 32, 32, VTLists+0 }, // FGRCC
3988	{ 32, 32, 32, VTLists+0 }, // GPR32	3988	{ 32, 32, 32, VTLists+0 }, // GPR32
3989	{ 32, 32, 32, VTLists+0 }, // HWRegs	3989	{ 32, 32, 32, VTLists+0 }, // HWRegs
3990	{ 32, 32, 32, VTLists+0 }, // MSACtrl	3990	{ 32, 32, 32, VTLists+0 }, // MSACtrl
3991	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO	3991	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO
3992	{ 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP	3992	{ 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP
3993	{ 32, 32, 32, VTLists+0 }, // CPU16Regs	3993	{ 32, 32, 32, VTLists+0 }, // CPU16Regs
3994	{ 32, 32, 32, VTLists+0 }, // FCC	3994	{ 32, 32, 32, VTLists+0 }, // FCC
3995	{ 32, 32, 32, VTLists+0 }, // GPRMM16	3995	{ 32, 32, 32, VTLists+0 }, // GPRMM16
3996	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP	3996	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP
3997	{ 32, 32, 32, VTLists+0 }, // GPRMM16Zero	3997	{ 32, 32, 32, VTLists+0 }, // GPRMM16Zero
3998	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero	3998	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero
3999	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP	3999	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP
4000	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond	4000	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond
4001	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP	4001	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP
4002	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero	4002	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero
4003	{ 32, 32, 32, VTLists+0 }, // HI32DSP	4003	{ 32, 32, 32, VTLists+0 }, // HI32DSP
4004	{ 32, 32, 32, VTLists+0 }, // LO32DSP	4004	{ 32, 32, 32, VTLists+0 }, // LO32DSP
4005	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond	4005	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond
4006	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst	4006	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst
4007	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	4007	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4008	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	4008	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4009	{ 32, 32, 32, VTLists+0 }, // CPURAReg	4009	{ 32, 32, 32, VTLists+0 }, // CPURAReg
4010	{ 32, 32, 32, VTLists+0 }, // CPUSPReg	4010	{ 32, 32, 32, VTLists+0 }, // CPUSPReg
4011	{ 32, 32, 32, VTLists+12 }, // DSPCC	4011	{ 32, 32, 32, VTLists+12 }, // DSPCC
4012	{ 32, 32, 32, VTLists+0 }, // GP32	4012	{ 32, 32, 32, VTLists+0 }, // GP32
4013	{ 32, 32, 32, VTLists+0 }, // GPR32ZERO	4013	{ 32, 32, 32, VTLists+0 }, // GPR32ZERO
4014	{ 32, 32, 32, VTLists+0 }, // HI32	4014	{ 32, 32, 32, VTLists+0 }, // HI32
4015	{ 32, 32, 32, VTLists+0 }, // LO32	4015	{ 32, 32, 32, VTLists+0 }, // LO32
4016	{ 32, 32, 32, VTLists+0 }, // SP32	4016	{ 32, 32, 32, VTLists+0 }, // SP32
4017	{ 64, 64, 64, VTLists+8 }, // FGR64	4017	{ 64, 64, 64, VTLists+8 }, // FGR64
4018	{ 64, 64, 64, VTLists+2 }, // GPR64	4018	{ 64, 64, 64, VTLists+2 }, // GPR64
4019	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO	4019	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO
4020	{ 64, 64, 64, VTLists+8 }, // AFGR64	4020	{ 64, 64, 64, VTLists+8 }, // AFGR64
4021	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP	4021	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
4022	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs	4022	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs
4023	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP	4023	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP
4024	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero	4024	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero
4025	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	4025	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
4026	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	4026	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
4027	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	4027	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
4028	{ 64, 64, 64, VTLists+24 }, // ACC64DSP	4028	{ 64, 64, 64, VTLists+24 }, // ACC64DSP
4029	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	4029	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
4030	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	4030	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
4031	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	4031	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
4032	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	4032	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
4033	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	4033	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
4034	{ 64, 64, 64, VTLists+2 }, // OCTEON_MPL	4034	{ 64, 64, 64, VTLists+2 }, // OCTEON_MPL
4035	{ 64, 64, 64, VTLists+2 }, // OCTEON_P	4035	{ 64, 64, 64, VTLists+2 }, // OCTEON_P
4036	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	4036	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
4037	{ 64, 64, 64, VTLists+24 }, // ACC64	4037	{ 64, 64, 64, VTLists+24 }, // ACC64
4038	{ 64, 64, 64, VTLists+2 }, // GP64	4038	{ 64, 64, 64, VTLists+2 }, // GP64
4039	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg	4039	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg
4040	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO	4040	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO
4041	{ 64, 64, 64, VTLists+2 }, // HI64	4041	{ 64, 64, 64, VTLists+2 }, // HI64
4042	{ 64, 64, 64, VTLists+2 }, // LO64	4042	{ 64, 64, 64, VTLists+2 }, // LO64
4043	{ 64, 64, 64, VTLists+2 }, // SP64	4043	{ 64, 64, 64, VTLists+2 }, // SP64
4044	{ 128, 128, 128, VTLists+10 }, // MSA128B	4044	{ 128, 128, 128, VTLists+10 }, // MSA128B
4045	{ 128, 128, 128, VTLists+21 }, // MSA128D	4045	{ 128, 128, 128, VTLists+21 }, // MSA128D
4046	{ 128, 128, 128, VTLists+15 }, // MSA128H	4046	{ 128, 128, 128, VTLists+15 }, // MSA128H
4047	{ 128, 128, 128, VTLists+18 }, // MSA128W	4047	{ 128, 128, 128, VTLists+18 }, // MSA128W
4048	{ 128, 128, 128, VTLists+18 }, // MSA128WEvens	4048	{ 128, 128, 128, VTLists+18 }, // MSA128WEvens
4049	{ 128, 128, 128, VTLists+24 }, // ACC128	4049	{ 128, 128, 128, VTLists+24 }, // ACC128
4050	};	4050	};
4051		4051
4052	static const TargetRegisterClass *const NullRegClasses[] = { nullptr };	4052	static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4053		4053
4054	static const uint32_t MSA128F16SubClassMask[] = {	4054	static const uint32_t MSA128F16SubClassMask[] = {
4055	0x00000001, 0x00000000, 0x0000001f,	4055	0x00000001, 0x00000000, 0x0000001f,
4056	};	4056	};
4057		4057
4058	static const uint32_t CCRSubClassMask[] = {	4058	static const uint32_t CCRSubClassMask[] = {
4059	0x00000002, 0x00000000, 0x00000000,	4059	0x00000002, 0x00000000, 0x00000000,
4060	};	4060	};
4061		4061
4062	static const uint32_t COP0SubClassMask[] = {	4062	static const uint32_t COP0SubClassMask[] = {
4063	0x00000004, 0x00000000, 0x00000000,	4063	0x00000004, 0x00000000, 0x00000000,
4064	};	4064	};
4065		4065
4066	static const uint32_t COP2SubClassMask[] = {	4066	static const uint32_t COP2SubClassMask[] = {
4067	0x00000008, 0x00000000, 0x00000000,	4067	0x00000008, 0x00000000, 0x00000000,
4068	};	4068	};
4069		4069
4070	static const uint32_t COP3SubClassMask[] = {	4070	static const uint32_t COP3SubClassMask[] = {
4071	0x00000010, 0x00000000, 0x00000000,	4071	0x00000010, 0x00000000, 0x00000000,
4072	};	4072	};
4073		4073
4074	static const uint32_t DSPRSubClassMask[] = {	4074	static const uint32_t DSPRSubClassMask[] = {
4075	0x7e7fb920, 0x00000013, 0x00000000,	4075	0x7e7fb920, 0x00000013, 0x00000000,
4076	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	4076	0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4077	};	4077	};
4078		4078
4079	static const uint32_t FGR32SubClassMask[] = {	4079	static const uint32_t FGR32SubClassMask[] = {
4080	0x000000c0, 0x00000000, 0x00000000,	4080	0x000000c0, 0x00000000, 0x00000000,
4081	0x00000000, 0x00000100, 0x00000000, // sub_hi	4081	0x00000000, 0x00000100, 0x00000000, // sub_hi
4082	0x00000001, 0x00000120, 0x0000001f, // sub_lo	4082	0x00000001, 0x00000120, 0x0000001f, // sub_lo
4083	};	4083	};
4084		4084
4085	static const uint32_t FGRCCSubClassMask[] = {	4085	static const uint32_t FGRCCSubClassMask[] = {
4086	0x000000c0, 0x00000000, 0x00000000,	4086	0x000000c0, 0x00000000, 0x00000000,
4087	0x00000000, 0x00000100, 0x00000000, // sub_hi	4087	0x00000000, 0x00000100, 0x00000000, // sub_hi
4088	0x00000001, 0x00000120, 0x0000001f, // sub_lo	4088	0x00000001, 0x00000120, 0x0000001f, // sub_lo
4089	};	4089	};
4090		4090
4091	static const uint32_t GPR32SubClassMask[] = {	4091	static const uint32_t GPR32SubClassMask[] = {
4092	0x7e7fb900, 0x00000013, 0x00000000,	4092	0x7e7fb900, 0x00000013, 0x00000000,
4093	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	4093	0x00000000, 0x9d3efec0, 0x00000000, // sub_32
4094	};	4094	};
4095		4095
4096	static const uint32_t HWRegsSubClassMask[] = {	4096	static const uint32_t HWRegsSubClassMask[] = {
4097	0x00000200, 0x00000000, 0x00000000,	4097	0x00000200, 0x00000000, 0x00000000,
4098	};	4098	};
4099		4099
4100	static const uint32_t MSACtrlSubClassMask[] = {	4100	static const uint32_t MSACtrlSubClassMask[] = {
4101	0x00000400, 0x00000000, 0x00000000,	4101	0x00000400, 0x00000000, 0x00000000,
4102	};	4102	};
4103		4103
4104	static const uint32_t GPR32NONZEROSubClassMask[] = {	4104	static const uint32_t GPR32NONZEROSubClassMask[] = {
4105	0x7e3cb800, 0x00000011, 0x00000000,	4105	0x7e3cb800, 0x00000011, 0x00000000,
4106	0x00000000, 0x8d3ae680, 0x00000000, // sub_32	4106	0x00000000, 0x8d3ae680, 0x00000000, // sub_32
4107	};	4107	};
4108		4108
4109	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {	4109	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
4110	0x5e24b000, 0x00000010, 0x00000000,	4110	0x5e24b000, 0x00000010, 0x00000000,
4111	0x00000000, 0x813a2600, 0x00000000, // sub_32	4111	0x00000000, 0x813a2600, 0x00000000, // sub_32
4112	};	4112	};
4113		4113
4114	static const uint32_t CPU16RegsSubClassMask[] = {	4114	static const uint32_t CPU16RegsSubClassMask[] = {
4115	0x1e24a000, 0x00000000, 0x00000000,	4115	0x1e24a000, 0x00000000, 0x00000000,
4116	0x00000000, 0x013a2400, 0x00000000, // sub_32	4116	0x00000000, 0x013a2400, 0x00000000, // sub_32
4117	};	4117	};
4118		4118
4119	static const uint32_t FCCSubClassMask[] = {	4119	static const uint32_t FCCSubClassMask[] = {
4120	0x00004000, 0x00000000, 0x00000000,	4120	0x00004000, 0x00000000, 0x00000000,
4121	};	4121	};
4122		4122
4123	static const uint32_t GPRMM16SubClassMask[] = {	4123	static const uint32_t GPRMM16SubClassMask[] = {
4124	0x1e248000, 0x00000000, 0x00000000,	4124	0x1e248000, 0x00000000, 0x00000000,
4125	0x00000000, 0x013a2400, 0x00000000, // sub_32	4125	0x00000000, 0x013a2400, 0x00000000, // sub_32
4126	};	4126	};
4127		4127
4128	static const uint32_t GPRMM16MovePSubClassMask[] = {	4128	static const uint32_t GPRMM16MovePSubClassMask[] = {
4129	0x08690000, 0x00000002, 0x00000000,	4129	0x08690000, 0x00000002, 0x00000000,
4130	0x00000000, 0x10264800, 0x00000000, // sub_32	4130	0x00000000, 0x10264800, 0x00000000, // sub_32
4131	};	4131	};
4132		4132
4133	static const uint32_t GPRMM16ZeroSubClassMask[] = {	4133	static const uint32_t GPRMM16ZeroSubClassMask[] = {
4134	0x1e460000, 0x00000002, 0x00000000,	4134	0x1e460000, 0x00000002, 0x00000000,
4135	0x00000000, 0x113c3000, 0x00000000, // sub_32	4135	0x00000000, 0x113c3000, 0x00000000, // sub_32
4136	};	4136	};
4137		4137
4138	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	4138	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4139	0x1e040000, 0x00000000, 0x00000000,	4139	0x1e040000, 0x00000000, 0x00000000,
4140	0x00000000, 0x01382000, 0x00000000, // sub_32	4140	0x00000000, 0x01382000, 0x00000000, // sub_32
4141	};	4141	};
4142		4142
4143	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	4143	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4144	0x08280000, 0x00000000, 0x00000000,	4144	0x08280000, 0x00000000, 0x00000000,
4145	0x00000000, 0x00224000, 0x00000000, // sub_32	4145	0x00000000, 0x00224000, 0x00000000, // sub_32
4146	};	4146	};
4147		4147
4148	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {	4148	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
4149	0x12100000, 0x00000000, 0x00000000,	4149	0x12100000, 0x00000000, 0x00000000,
4150	0x00000000, 0x01088000, 0x00000000, // sub_32	4150	0x00000000, 0x01088000, 0x00000000, // sub_32
4151	};	4151	};
4152		4152
4153	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	4153	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4154	0x08200000, 0x00000000, 0x00000000,	4154	0x08200000, 0x00000000, 0x00000000,
4155	0x00000000, 0x00220000, 0x00000000, // sub_32	4155	0x00000000, 0x00220000, 0x00000000, // sub_32
4156	};	4156	};
4157		4157
4158	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	4158	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4159	0x08400000, 0x00000002, 0x00000000,	4159	0x08400000, 0x00000002, 0x00000000,
4160	0x00000000, 0x10240000, 0x00000000, // sub_32	4160	0x00000000, 0x10240000, 0x00000000, // sub_32
4161	};	4161	};
4162		4162
4163	static const uint32_t HI32DSPSubClassMask[] = {	4163	static const uint32_t HI32DSPSubClassMask[] = {
4164	0x00800000, 0x00000004, 0x00000000,	4164	0x00800000, 0x00000004, 0x00000000,
4165	0x00000000, 0x20000000, 0x00000000, // sub_32	4165	0x00000000, 0x20000000, 0x00000000, // sub_32
4166	0x00000000, 0x02010000, 0x00000000, // sub_hi	4166	0x00000000, 0x02010000, 0x00000000, // sub_hi
4167	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	4167	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4168	};	4168	};
4169		4169
4170	static const uint32_t LO32DSPSubClassMask[] = {	4170	static const uint32_t LO32DSPSubClassMask[] = {
4171	0x01000000, 0x00000008, 0x00000000,	4171	0x01000000, 0x00000008, 0x00000000,
4172	0x00000000, 0x40000000, 0x00000020, // sub_32	4172	0x00000000, 0x40000000, 0x00000020, // sub_32
4173	0x00000000, 0x02010000, 0x00000000, // sub_lo	4173	0x00000000, 0x02010000, 0x00000000, // sub_lo
4174	};	4174	};
4175		4175
4176	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	4176	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4177	0x12000000, 0x00000000, 0x00000000,	4177	0x12000000, 0x00000000, 0x00000000,
4178	0x00000000, 0x01080000, 0x00000000, // sub_32	4178	0x00000000, 0x01080000, 0x00000000, // sub_32
4179	};	4179	};
4180		4180
4181	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {	4181	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
4182	0x14000000, 0x00000000, 0x00000000,	4182	0x14000000, 0x00000000, 0x00000000,
4183	0x00000000, 0x01100000, 0x00000000, // sub_32	4183	0x00000000, 0x01100000, 0x00000000, // sub_32
4184	};	4184	};
4185		4185
4186	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	4186	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4187	0x08000000, 0x00000000, 0x00000000,	4187	0x08000000, 0x00000000, 0x00000000,
4188	0x00000000, 0x00200000, 0x00000000, // sub_32	4188	0x00000000, 0x00200000, 0x00000000, // sub_32
4189	};	4189	};
4190		4190
4191	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	4191	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4192	0x10000000, 0x00000000, 0x00000000,	4192	0x10000000, 0x00000000, 0x00000000,
4193	0x00000000, 0x01000000, 0x00000000, // sub_32	4193	0x00000000, 0x01000000, 0x00000000, // sub_32
4194	};	4194	};
4195		4195
4196	static const uint32_t CPURARegSubClassMask[] = {	4196	static const uint32_t CPURARegSubClassMask[] = {
4197	0x20000000, 0x00000000, 0x00000000,	4197	0x20000000, 0x00000000, 0x00000000,
4198	0x00000000, 0x08000000, 0x00000000, // sub_32	4198	0x00000000, 0x08000000, 0x00000000, // sub_32
4199	};	4199	};
4200		4200
4201	static const uint32_t CPUSPRegSubClassMask[] = {	4201	static const uint32_t CPUSPRegSubClassMask[] = {
4202	0x40000000, 0x00000010, 0x00000000,	4202	0x40000000, 0x00000010, 0x00000000,
4203	0x00000000, 0x80000000, 0x00000000, // sub_32	4203	0x00000000, 0x80000000, 0x00000000, // sub_32
4204	};	4204	};
4205		4205
4206	static const uint32_t DSPCCSubClassMask[] = {	4206	static const uint32_t DSPCCSubClassMask[] = {
4207	0x80000000, 0x00000000, 0x00000000,	4207	0x80000000, 0x00000000, 0x00000000,
4208	};	4208	};
4209		4209
4210	static const uint32_t GP32SubClassMask[] = {	4210	static const uint32_t GP32SubClassMask[] = {
4211	0x00000000, 0x00000001, 0x00000000,	4211	0x00000000, 0x00000001, 0x00000000,
4212	0x00000000, 0x04000000, 0x00000000, // sub_32	4212	0x00000000, 0x04000000, 0x00000000, // sub_32
4213	};	4213	};
4214		4214
4215	static const uint32_t GPR32ZEROSubClassMask[] = {	4215	static const uint32_t GPR32ZEROSubClassMask[] = {
4216	0x00000000, 0x00000002, 0x00000000,	4216	0x00000000, 0x00000002, 0x00000000,
4217	0x00000000, 0x10000000, 0x00000000, // sub_32	4217	0x00000000, 0x10000000, 0x00000000, // sub_32
4218	};	4218	};
4219		4219
4220	static const uint32_t HI32SubClassMask[] = {	4220	static const uint32_t HI32SubClassMask[] = {
4221	0x00000000, 0x00000004, 0x00000000,	4221	0x00000000, 0x00000004, 0x00000000,
4222	0x00000000, 0x20000000, 0x00000000, // sub_32	4222	0x00000000, 0x20000000, 0x00000000, // sub_32
4223	0x00000000, 0x02000000, 0x00000000, // sub_hi	4223	0x00000000, 0x02000000, 0x00000000, // sub_hi
4224	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	4224	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
4225	};	4225	};
4226		4226
4227	static const uint32_t LO32SubClassMask[] = {	4227	static const uint32_t LO32SubClassMask[] = {
4228	0x00000000, 0x00000008, 0x00000000,	4228	0x00000000, 0x00000008, 0x00000000,
4229	0x00000000, 0x40000000, 0x00000020, // sub_32	4229	0x00000000, 0x40000000, 0x00000020, // sub_32
4230	0x00000000, 0x02000000, 0x00000000, // sub_lo	4230	0x00000000, 0x02000000, 0x00000000, // sub_lo
4231	};	4231	};
4232		4232
4233	static const uint32_t SP32SubClassMask[] = {	4233	static const uint32_t SP32SubClassMask[] = {
4234	0x00000000, 0x00000010, 0x00000000,	4234	0x00000000, 0x00000010, 0x00000000,
4235	0x00000000, 0x80000000, 0x00000000, // sub_32	4235	0x00000000, 0x80000000, 0x00000000, // sub_32
4236	};	4236	};
4237		4237
4238	static const uint32_t FGR64SubClassMask[] = {	4238	static const uint32_t FGR64SubClassMask[] = {
4239	0x00000000, 0x00000020, 0x00000000,	4239	0x00000000, 0x00000020, 0x00000000,
4240	0x00000001, 0x00000000, 0x0000001f, // sub_64	4240	0x00000001, 0x00000000, 0x0000001f, // sub_64
4241	};	4241	};
4242		4242
4243	static const uint32_t GPR64SubClassMask[] = {	4243	static const uint32_t GPR64SubClassMask[] = {
4244	0x00000000, 0x9d3efec0, 0x00000000,	4244	0x00000000, 0x9d3efec0, 0x00000000,
4245	};	4245	};
4246		4246
4247	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {	4247	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
4248	0x00000000, 0x8d3ae680, 0x00000000,	4248	0x00000000, 0x8d3ae680, 0x00000000,
4249	};	4249	};
4250		4250
4251	static const uint32_t AFGR64SubClassMask[] = {	4251	static const uint32_t AFGR64SubClassMask[] = {
4252	0x00000000, 0x00000100, 0x00000000,	4252	0x00000000, 0x00000100, 0x00000000,
4253	};	4253	};
4254		4254
4255	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {	4255	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
4256	0x00000000, 0x813a2600, 0x00000000,	4256	0x00000000, 0x813a2600, 0x00000000,
4257	};	4257	};
4258		4258
4259	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {	4259	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
4260	0x00000000, 0x013a2400, 0x00000000,	4260	0x00000000, 0x013a2400, 0x00000000,
4261	};	4261	};
4262		4262
4263	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {	4263	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
4264	0x00000000, 0x10264800, 0x00000000,	4264	0x00000000, 0x10264800, 0x00000000,
4265	};	4265	};
4266		4266
4267	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {	4267	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
4268	0x00000000, 0x113c3000, 0x00000000,	4268	0x00000000, 0x113c3000, 0x00000000,
4269	};	4269	};
4270		4270
4271	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	4271	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4272	0x00000000, 0x01382000, 0x00000000,	4272	0x00000000, 0x01382000, 0x00000000,
4273	};	4273	};
4274		4274
4275	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	4275	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
4276	0x00000000, 0x00224000, 0x00000000,	4276	0x00000000, 0x00224000, 0x00000000,
4277	};	4277	};
4278		4278
4279	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {	4279	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
4280	0x00000000, 0x01088000, 0x00000000,	4280	0x00000000, 0x01088000, 0x00000000,
4281	};	4281	};
4282		4282
4283	static const uint32_t ACC64DSPSubClassMask[] = {	4283	static const uint32_t ACC64DSPSubClassMask[] = {
4284	0x00000000, 0x02010000, 0x00000000,	4284	0x00000000, 0x02010000, 0x00000000,
4285	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	4285	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4286	};	4286	};
4287		4287
4288	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	4288	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
4289	0x00000000, 0x00220000, 0x00000000,	4289	0x00000000, 0x00220000, 0x00000000,
4290	};	4290	};
4291		4291
4292	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	4292	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
4293	0x00000000, 0x10240000, 0x00000000,	4293	0x00000000, 0x10240000, 0x00000000,
4294	};	4294	};
4295		4295
4296	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	4296	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
4297	0x00000000, 0x01080000, 0x00000000,	4297	0x00000000, 0x01080000, 0x00000000,
4298	};	4298	};
4299		4299
4300	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {	4300	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
4301	0x00000000, 0x01100000, 0x00000000,	4301	0x00000000, 0x01100000, 0x00000000,
4302	};	4302	};
4303		4303
4304	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	4304	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
4305	0x00000000, 0x00200000, 0x00000000,	4305	0x00000000, 0x00200000, 0x00000000,
4306	};	4306	};
4307		4307
4308	static const uint32_t OCTEON_MPLSubClassMask[] = {	4308	static const uint32_t OCTEON_MPLSubClassMask[] = {
4309	0x00000000, 0x00400000, 0x00000000,	4309	0x00000000, 0x00400000, 0x00000000,
4310	};	4310	};
4311		4311
4312	static const uint32_t OCTEON_PSubClassMask[] = {	4312	static const uint32_t OCTEON_PSubClassMask[] = {
4313	0x00000000, 0x00800000, 0x00000000,	4313	0x00000000, 0x00800000, 0x00000000,
4314	};	4314	};
4315		4315
4316	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	4316	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
4317	0x00000000, 0x01000000, 0x00000000,	4317	0x00000000, 0x01000000, 0x00000000,
4318	};	4318	};
4319		4319
4320	static const uint32_t ACC64SubClassMask[] = {	4320	static const uint32_t ACC64SubClassMask[] = {
4321	0x00000000, 0x02000000, 0x00000000,	4321	0x00000000, 0x02000000, 0x00000000,
4322	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	4322	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
4323	};	4323	};
4324		4324
4325	static const uint32_t GP64SubClassMask[] = {	4325	static const uint32_t GP64SubClassMask[] = {
4326	0x00000000, 0x04000000, 0x00000000,	4326	0x00000000, 0x04000000, 0x00000000,
4327	};	4327	};
4328		4328
4329	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {	4329	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
4330	0x00000000, 0x08000000, 0x00000000,	4330	0x00000000, 0x08000000, 0x00000000,
4331	};	4331	};
4332		4332
4333	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {	4333	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
4334	0x00000000, 0x10000000, 0x00000000,	4334	0x00000000, 0x10000000, 0x00000000,
4335	};	4335	};
4336		4336
4337	static const uint32_t HI64SubClassMask[] = {	4337	static const uint32_t HI64SubClassMask[] = {
4338	0x00000000, 0x20000000, 0x00000000,	4338	0x00000000, 0x20000000, 0x00000000,
4339	0x00000000, 0x00000000, 0x00000020, // sub_hi	4339	0x00000000, 0x00000000, 0x00000020, // sub_hi
4340	};	4340	};
4341		4341
4342	static const uint32_t LO64SubClassMask[] = {	4342	static const uint32_t LO64SubClassMask[] = {
4343	0x00000000, 0x40000000, 0x00000000,	4343	0x00000000, 0x40000000, 0x00000000,
4344	0x00000000, 0x00000000, 0x00000020, // sub_lo	4344	0x00000000, 0x00000000, 0x00000020, // sub_lo
4345	};	4345	};
4346		4346
4347	static const uint32_t SP64SubClassMask[] = {	4347	static const uint32_t SP64SubClassMask[] = {
4348	0x00000000, 0x80000000, 0x00000000,	4348	0x00000000, 0x80000000, 0x00000000,
4349	};	4349	};
4350		4350
4351	static const uint32_t MSA128BSubClassMask[] = {	4351	static const uint32_t MSA128BSubClassMask[] = {
4352	0x00000000, 0x00000000, 0x0000001f,	4352	0x00000000, 0x00000000, 0x0000001f,
4353	};	4353	};
4354		4354
4355	static const uint32_t MSA128DSubClassMask[] = {	4355	static const uint32_t MSA128DSubClassMask[] = {
4356	0x00000000, 0x00000000, 0x0000001f,	4356	0x00000000, 0x00000000, 0x0000001f,
4357	};	4357	};
4358		4358
4359	static const uint32_t MSA128HSubClassMask[] = {	4359	static const uint32_t MSA128HSubClassMask[] = {
4360	0x00000000, 0x00000000, 0x0000001f,	4360	0x00000000, 0x00000000, 0x0000001f,
4361	};	4361	};
4362		4362
4363	static const uint32_t MSA128WSubClassMask[] = {	4363	static const uint32_t MSA128WSubClassMask[] = {
4364	0x00000000, 0x00000000, 0x0000001f,	4364	0x00000000, 0x00000000, 0x0000001f,
4365	};	4365	};
4366		4366
4367	static const uint32_t MSA128WEvensSubClassMask[] = {	4367	static const uint32_t MSA128WEvensSubClassMask[] = {
4368	0x00000000, 0x00000000, 0x00000010,	4368	0x00000000, 0x00000000, 0x00000010,
4369	};	4369	};
4370		4370
4371	static const uint32_t ACC128SubClassMask[] = {	4371	static const uint32_t ACC128SubClassMask[] = {
4372	0x00000000, 0x00000000, 0x00000020,	4372	0x00000000, 0x00000000, 0x00000020,
4373	};	4373	};
4374		4374
4375	static const uint16_t SuperRegIdxSeqs[] = {	4375	static const uint16_t SuperRegIdxSeqs[] = {
4376	/* 0 */ 1, 0,	4376	/* 0 */ 1, 0,
4377	/* 2 */ 2, 0,	4377	/* 2 */ 2, 0,
4378	/* 4 */ 8, 0,	4378	/* 4 */ 8, 0,
4379	/* 6 */ 1, 9, 0,	4379	/* 6 */ 1, 9, 0,
4380	/* 9 */ 8, 9, 0,	4380	/* 9 */ 8, 9, 0,
4381	/* 12 */ 1, 8, 10, 0,	4381	/* 12 */ 1, 8, 10, 0,
4382	/* 16 */ 11, 0,	4382	/* 16 */ 11, 0,
4383	};	4383	};
4384		4384
4385	static const TargetRegisterClass *const FGR32Superclasses[] = {	4385	static const TargetRegisterClass *const FGR32Superclasses[] = {
4386	&Mips::FGRCCRegClass,	4386	&Mips::FGRCCRegClass,
4387	nullptr	4387	nullptr
4388	};	4388	};
4389		4389
4390	static const TargetRegisterClass *const FGRCCSuperclasses[] = {	4390	static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4391	&Mips::FGR32RegClass,	4391	&Mips::FGR32RegClass,
4392	nullptr	4392	nullptr
4393	};	4393	};
4394		4394
4395	static const TargetRegisterClass *const GPR32Superclasses[] = {	4395	static const TargetRegisterClass *const GPR32Superclasses[] = {
4396	&Mips::DSPRRegClass,	4396	&Mips::DSPRRegClass,
4397	nullptr	4397	nullptr
4398	};	4398	};
4399		4399
4400	static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {	4400	static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4401	&Mips::DSPRRegClass,	4401	&Mips::DSPRRegClass,
4402	&Mips::GPR32RegClass,	4402	&Mips::GPR32RegClass,
4403	nullptr	4403	nullptr
4404	};	4404	};
4405		4405
4406	static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {	4406	static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4407	&Mips::DSPRRegClass,	4407	&Mips::DSPRRegClass,
4408	&Mips::GPR32RegClass,	4408	&Mips::GPR32RegClass,
4409	&Mips::GPR32NONZERORegClass,	4409	&Mips::GPR32NONZERORegClass,
4410	nullptr	4410	nullptr
4411	};	4411	};
4412		4412
4413	static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {	4413	static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4414	&Mips::DSPRRegClass,	4414	&Mips::DSPRRegClass,
4415	&Mips::GPR32RegClass,	4415	&Mips::GPR32RegClass,
4416	&Mips::GPR32NONZERORegClass,	4416	&Mips::GPR32NONZERORegClass,
4417	&Mips::CPU16RegsPlusSPRegClass,	4417	&Mips::CPU16RegsPlusSPRegClass,
4418	nullptr	4418	nullptr
4419	};	4419	};
4420		4420
4421	static const TargetRegisterClass *const GPRMM16Superclasses[] = {	4421	static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4422	&Mips::DSPRRegClass,	4422	&Mips::DSPRRegClass,
4423	&Mips::GPR32RegClass,	4423	&Mips::GPR32RegClass,
4424	&Mips::GPR32NONZERORegClass,	4424	&Mips::GPR32NONZERORegClass,
4425	&Mips::CPU16RegsPlusSPRegClass,	4425	&Mips::CPU16RegsPlusSPRegClass,
4426	&Mips::CPU16RegsRegClass,	4426	&Mips::CPU16RegsRegClass,
4427	nullptr	4427	nullptr
4428	};	4428	};
4429		4429
4430	static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {	4430	static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4431	&Mips::DSPRRegClass,	4431	&Mips::DSPRRegClass,
4432	&Mips::GPR32RegClass,	4432	&Mips::GPR32RegClass,
4433	nullptr	4433	nullptr
4434	};	4434	};
4435		4435
4436	static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {	4436	static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4437	&Mips::DSPRRegClass,	4437	&Mips::DSPRRegClass,
4438	&Mips::GPR32RegClass,	4438	&Mips::GPR32RegClass,
4439	nullptr	4439	nullptr
4440	};	4440	};
4441		4441
4442	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	4442	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4443	&Mips::DSPRRegClass,	4443	&Mips::DSPRRegClass,
4444	&Mips::GPR32RegClass,	4444	&Mips::GPR32RegClass,
4445	&Mips::GPR32NONZERORegClass,	4445	&Mips::GPR32NONZERORegClass,
4446	&Mips::CPU16RegsPlusSPRegClass,	4446	&Mips::CPU16RegsPlusSPRegClass,
4447	&Mips::CPU16RegsRegClass,	4447	&Mips::CPU16RegsRegClass,
4448	&Mips::GPRMM16RegClass,	4448	&Mips::GPRMM16RegClass,
4449	&Mips::GPRMM16ZeroRegClass,	4449	&Mips::GPRMM16ZeroRegClass,
4450	nullptr	4450	nullptr
4451	};	4451	};
4452		4452
4453	static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	4453	static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4454	&Mips::DSPRRegClass,	4454	&Mips::DSPRRegClass,
4455	&Mips::GPR32RegClass,	4455	&Mips::GPR32RegClass,
4456	&Mips::GPR32NONZERORegClass,	4456	&Mips::GPR32NONZERORegClass,
4457	&Mips::GPRMM16MovePRegClass,	4457	&Mips::GPRMM16MovePRegClass,
4458	nullptr	4458	nullptr
4459	};	4459	};
4460		4460
4461	static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {	4461	static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4462	&Mips::DSPRRegClass,	4462	&Mips::DSPRRegClass,
4463	&Mips::GPR32RegClass,	4463	&Mips::GPR32RegClass,
4464	&Mips::GPR32NONZERORegClass,	4464	&Mips::GPR32NONZERORegClass,
4465	nullptr	4465	nullptr
4466	};	4466	};
4467		4467
4468	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	4468	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4469	&Mips::DSPRRegClass,	4469	&Mips::DSPRRegClass,
4470	&Mips::GPR32RegClass,	4470	&Mips::GPR32RegClass,
4471	&Mips::GPR32NONZERORegClass,	4471	&Mips::GPR32NONZERORegClass,
4472	&Mips::CPU16RegsPlusSPRegClass,	4472	&Mips::CPU16RegsPlusSPRegClass,
4473	&Mips::CPU16RegsRegClass,	4473	&Mips::CPU16RegsRegClass,
4474	&Mips::GPRMM16RegClass,	4474	&Mips::GPRMM16RegClass,
4475	&Mips::GPRMM16MovePRegClass,	4475	&Mips::GPRMM16MovePRegClass,
4476	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	4476	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4477	nullptr	4477	nullptr
4478	};	4478	};
4479		4479
4480	static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	4480	static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4481	&Mips::DSPRRegClass,	4481	&Mips::DSPRRegClass,
4482	&Mips::GPR32RegClass,	4482	&Mips::GPR32RegClass,
4483	&Mips::GPRMM16MovePRegClass,	4483	&Mips::GPRMM16MovePRegClass,
4484	&Mips::GPRMM16ZeroRegClass,	4484	&Mips::GPRMM16ZeroRegClass,
4485	nullptr	4485	nullptr
4486	};	4486	};
4487		4487
4488	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	4488	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4489	&Mips::DSPRRegClass,	4489	&Mips::DSPRRegClass,
4490	&Mips::GPR32RegClass,	4490	&Mips::GPR32RegClass,
4491	&Mips::GPR32NONZERORegClass,	4491	&Mips::GPR32NONZERORegClass,
4492	&Mips::CPU16RegsPlusSPRegClass,	4492	&Mips::CPU16RegsPlusSPRegClass,
4493	&Mips::CPU16RegsRegClass,	4493	&Mips::CPU16RegsRegClass,
4494	&Mips::GPRMM16RegClass,	4494	&Mips::GPRMM16RegClass,
4495	&Mips::GPRMM16ZeroRegClass,	4495	&Mips::GPRMM16ZeroRegClass,
4496	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	4496	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4497	&Mips::GPRMM16MovePPairSecondRegClass,	4497	&Mips::GPRMM16MovePPairSecondRegClass,
4498	nullptr	4498	nullptr
4499	};	4499	};
4500		4500
4501	static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {	4501	static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4502	&Mips::DSPRRegClass,	4502	&Mips::DSPRRegClass,
4503	&Mips::GPR32RegClass,	4503	&Mips::GPR32RegClass,
4504	&Mips::GPR32NONZERORegClass,	4504	&Mips::GPR32NONZERORegClass,
4505	&Mips::CPU16RegsPlusSPRegClass,	4505	&Mips::CPU16RegsPlusSPRegClass,
4506	&Mips::CPU16RegsRegClass,	4506	&Mips::CPU16RegsRegClass,
4507	&Mips::GPRMM16RegClass,	4507	&Mips::GPRMM16RegClass,
4508	&Mips::GPRMM16ZeroRegClass,	4508	&Mips::GPRMM16ZeroRegClass,
4509	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	4509	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4510	nullptr	4510	nullptr
4511	};	4511	};
4512		4512
4513	static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	4513	static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4514	&Mips::DSPRRegClass,	4514	&Mips::DSPRRegClass,
4515	&Mips::GPR32RegClass,	4515	&Mips::GPR32RegClass,
4516	&Mips::GPR32NONZERORegClass,	4516	&Mips::GPR32NONZERORegClass,
4517	&Mips::CPU16RegsPlusSPRegClass,	4517	&Mips::CPU16RegsPlusSPRegClass,
4518	&Mips::CPU16RegsRegClass,	4518	&Mips::CPU16RegsRegClass,
4519	&Mips::GPRMM16RegClass,	4519	&Mips::GPRMM16RegClass,
4520	&Mips::GPRMM16MovePRegClass,	4520	&Mips::GPRMM16MovePRegClass,
4521	&Mips::GPRMM16ZeroRegClass,	4521	&Mips::GPRMM16ZeroRegClass,
4522	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	4522	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4523	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	4523	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
4524	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	4524	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,
4525	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	4525	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4526	nullptr	4526	nullptr
4527	};	4527	};
4528		4528
4529	static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	4529	static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4530	&Mips::DSPRRegClass,	4530	&Mips::DSPRRegClass,
4531	&Mips::GPR32RegClass,	4531	&Mips::GPR32RegClass,
4532	&Mips::GPR32NONZERORegClass,	4532	&Mips::GPR32NONZERORegClass,
4533	&Mips::CPU16RegsPlusSPRegClass,	4533	&Mips::CPU16RegsPlusSPRegClass,
4534	&Mips::CPU16RegsRegClass,	4534	&Mips::CPU16RegsRegClass,
4535	&Mips::GPRMM16RegClass,	4535	&Mips::GPRMM16RegClass,
4536	&Mips::GPRMM16ZeroRegClass,	4536	&Mips::GPRMM16ZeroRegClass,
4537	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	4537	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
4538	&Mips::GPRMM16MovePPairSecondRegClass,	4538	&Mips::GPRMM16MovePPairSecondRegClass,
4539	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	4539	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4540	&Mips::GPRMM16MovePPairFirstRegClass,	4540	&Mips::GPRMM16MovePPairFirstRegClass,
4541	nullptr	4541	nullptr
4542	};	4542	};
4543		4543
4544	static const TargetRegisterClass *const CPURARegSuperclasses[] = {	4544	static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4545	&Mips::DSPRRegClass,	4545	&Mips::DSPRRegClass,
4546	&Mips::GPR32RegClass,	4546	&Mips::GPR32RegClass,
4547	&Mips::GPR32NONZERORegClass,	4547	&Mips::GPR32NONZERORegClass,
4548	nullptr	4548	nullptr
4549	};	4549	};
4550		4550
4551	static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {	4551	static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4552	&Mips::DSPRRegClass,	4552	&Mips::DSPRRegClass,
4553	&Mips::GPR32RegClass,	4553	&Mips::GPR32RegClass,
4554	&Mips::GPR32NONZERORegClass,	4554	&Mips::GPR32NONZERORegClass,
4555	&Mips::CPU16RegsPlusSPRegClass,	4555	&Mips::CPU16RegsPlusSPRegClass,
4556	nullptr	4556	nullptr
4557	};	4557	};
4558		4558
4559	static const TargetRegisterClass *const GP32Superclasses[] = {	4559	static const TargetRegisterClass *const GP32Superclasses[] = {
4560	&Mips::DSPRRegClass,	4560	&Mips::DSPRRegClass,
4561	&Mips::GPR32RegClass,	4561	&Mips::GPR32RegClass,
4562	&Mips::GPR32NONZERORegClass,	4562	&Mips::GPR32NONZERORegClass,
4563	nullptr	4563	nullptr
4564	};	4564	};
4565		4565
4566	static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {	4566	static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4567	&Mips::DSPRRegClass,	4567	&Mips::DSPRRegClass,
4568	&Mips::GPR32RegClass,	4568	&Mips::GPR32RegClass,
4569	&Mips::GPRMM16MovePRegClass,	4569	&Mips::GPRMM16MovePRegClass,
4570	&Mips::GPRMM16ZeroRegClass,	4570	&Mips::GPRMM16ZeroRegClass,
4571	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	4571	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4572	nullptr	4572	nullptr
4573	};	4573	};
4574		4574
4575	static const TargetRegisterClass *const HI32Superclasses[] = {	4575	static const TargetRegisterClass *const HI32Superclasses[] = {
4576	&Mips::HI32DSPRegClass,	4576	&Mips::HI32DSPRegClass,
4577	nullptr	4577	nullptr
4578	};	4578	};
4579		4579
4580	static const TargetRegisterClass *const LO32Superclasses[] = {	4580	static const TargetRegisterClass *const LO32Superclasses[] = {
4581	&Mips::LO32DSPRegClass,	4581	&Mips::LO32DSPRegClass,
4582	nullptr	4582	nullptr
4583	};	4583	};
4584		4584
4585	static const TargetRegisterClass *const SP32Superclasses[] = {	4585	static const TargetRegisterClass *const SP32Superclasses[] = {
4586	&Mips::DSPRRegClass,	4586	&Mips::DSPRRegClass,
4587	&Mips::GPR32RegClass,	4587	&Mips::GPR32RegClass,
4588	&Mips::GPR32NONZERORegClass,	4588	&Mips::GPR32NONZERORegClass,
4589	&Mips::CPU16RegsPlusSPRegClass,	4589	&Mips::CPU16RegsPlusSPRegClass,
4590	&Mips::CPUSPRegRegClass,	4590	&Mips::CPUSPRegRegClass,
4591	nullptr	4591	nullptr
4592	};	4592	};
4593		4593
4594	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {	4594	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4595	&Mips::GPR64RegClass,	4595	&Mips::GPR64RegClass,
4596	nullptr	4596	nullptr
4597	};	4597	};
4598		4598
4599	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {	4599	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4600	&Mips::GPR64RegClass,	4600	&Mips::GPR64RegClass,
4601	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4601	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4602	nullptr	4602	nullptr
4603	};	4603	};
4604		4604
4605	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {	4605	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4606	&Mips::GPR64RegClass,	4606	&Mips::GPR64RegClass,
4607	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4607	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4608	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4608	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4609	nullptr	4609	nullptr
4610	};	4610	};
4611		4611
4612	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {	4612	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4613	&Mips::GPR64RegClass,	4613	&Mips::GPR64RegClass,
4614	nullptr	4614	nullptr
4615	};	4615	};
4616		4616
4617	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {	4617	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4618	&Mips::GPR64RegClass,	4618	&Mips::GPR64RegClass,
4619	nullptr	4619	nullptr
4620	};	4620	};
4621		4621
4622	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	4622	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4623	&Mips::GPR64RegClass,	4623	&Mips::GPR64RegClass,
4624	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4624	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4625	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4625	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4626	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4626	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4627	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4627	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4628	nullptr	4628	nullptr
4629	};	4629	};
4630		4630
4631	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	4631	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4632	&Mips::GPR64RegClass,	4632	&Mips::GPR64RegClass,
4633	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4633	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4634	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	4634	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4635	nullptr	4635	nullptr
4636	};	4636	};
4637		4637
4638	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {	4638	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4639	&Mips::GPR64RegClass,	4639	&Mips::GPR64RegClass,
4640	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4640	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4641	nullptr	4641	nullptr
4642	};	4642	};
4643		4643
4644	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	4644	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4645	&Mips::GPR64RegClass,	4645	&Mips::GPR64RegClass,
4646	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4646	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4647	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4647	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4648	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4648	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4649	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	4649	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4650	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	4650	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4651	nullptr	4651	nullptr
4652	};	4652	};
4653		4653
4654	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	4654	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4655	&Mips::GPR64RegClass,	4655	&Mips::GPR64RegClass,
4656	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	4656	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4657	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4657	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4658	nullptr	4658	nullptr
4659	};	4659	};
4660		4660
4661	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	4661	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4662	&Mips::GPR64RegClass,	4662	&Mips::GPR64RegClass,
4663	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4663	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4664	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4664	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4665	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4665	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4666	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4666	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4667	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	4667	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4668	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	4668	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4669	nullptr	4669	nullptr
4670	};	4670	};
4671		4671
4672	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {	4672	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4673	&Mips::GPR64RegClass,	4673	&Mips::GPR64RegClass,
4674	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4674	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4675	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4675	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4676	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4676	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4677	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4677	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4678	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	4678	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4679	nullptr	4679	nullptr
4680	};	4680	};
4681		4681
4682	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	4682	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4683	&Mips::GPR64RegClass,	4683	&Mips::GPR64RegClass,
4684	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4684	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4685	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4685	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4686	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4686	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4687	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	4687	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4688	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4688	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4689	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	4689	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4690	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	4690	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
4691	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	4691	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
4692	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	4692	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4693	nullptr	4693	nullptr
4694	};	4694	};
4695		4695
4696	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	4696	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4697	&Mips::GPR64RegClass,	4697	&Mips::GPR64RegClass,
4698	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4698	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4699	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4699	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4700	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	4700	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
4701	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4701	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4702	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	4702	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
4703	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	4703	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
4704	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	4704	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
4705	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	4705	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
4706	nullptr	4706	nullptr
4707	};	4707	};
4708		4708
4709	static const TargetRegisterClass *const ACC64Superclasses[] = {	4709	static const TargetRegisterClass *const ACC64Superclasses[] = {
4710	&Mips::ACC64DSPRegClass,	4710	&Mips::ACC64DSPRegClass,
4711	nullptr	4711	nullptr
4712	};	4712	};
4713		4713
4714	static const TargetRegisterClass *const GP64Superclasses[] = {	4714	static const TargetRegisterClass *const GP64Superclasses[] = {
4715	&Mips::GPR64RegClass,	4715	&Mips::GPR64RegClass,
4716	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4716	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4717	nullptr	4717	nullptr
4718	};	4718	};
4719		4719
4720	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {	4720	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4721	&Mips::GPR64RegClass,	4721	&Mips::GPR64RegClass,
4722	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4722	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4723	nullptr	4723	nullptr
4724	};	4724	};
4725		4725
4726	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {	4726	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4727	&Mips::GPR64RegClass,	4727	&Mips::GPR64RegClass,
4728	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	4728	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
4729	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	4729	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
4730	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	4730	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
4731	nullptr	4731	nullptr
4732	};	4732	};
4733		4733
4734	static const TargetRegisterClass *const SP64Superclasses[] = {	4734	static const TargetRegisterClass *const SP64Superclasses[] = {
4735	&Mips::GPR64RegClass,	4735	&Mips::GPR64RegClass,
4736	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	4736	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
4737	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	4737	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
4738	nullptr	4738	nullptr
4739	};	4739	};
4740		4740
4741	static const TargetRegisterClass *const MSA128BSuperclasses[] = {	4741	static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4742	&Mips::MSA128F16RegClass,	4742	&Mips::MSA128F16RegClass,
4743	&Mips::MSA128DRegClass,	4743	&Mips::MSA128DRegClass,
4744	&Mips::MSA128HRegClass,	4744	&Mips::MSA128HRegClass,
4745	&Mips::MSA128WRegClass,	4745	&Mips::MSA128WRegClass,
4746	nullptr	4746	nullptr
4747	};	4747	};
4748		4748
4749	static const TargetRegisterClass *const MSA128DSuperclasses[] = {	4749	static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4750	&Mips::MSA128F16RegClass,	4750	&Mips::MSA128F16RegClass,
4751	&Mips::MSA128BRegClass,	4751	&Mips::MSA128BRegClass,
4752	&Mips::MSA128HRegClass,	4752	&Mips::MSA128HRegClass,
4753	&Mips::MSA128WRegClass,	4753	&Mips::MSA128WRegClass,
4754	nullptr	4754	nullptr
4755	};	4755	};
4756		4756
4757	static const TargetRegisterClass *const MSA128HSuperclasses[] = {	4757	static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4758	&Mips::MSA128F16RegClass,	4758	&Mips::MSA128F16RegClass,
4759	&Mips::MSA128BRegClass,	4759	&Mips::MSA128BRegClass,
4760	&Mips::MSA128DRegClass,	4760	&Mips::MSA128DRegClass,
4761	&Mips::MSA128WRegClass,	4761	&Mips::MSA128WRegClass,
4762	nullptr	4762	nullptr
4763	};	4763	};
4764		4764
4765	static const TargetRegisterClass *const MSA128WSuperclasses[] = {	4765	static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4766	&Mips::MSA128F16RegClass,	4766	&Mips::MSA128F16RegClass,
4767	&Mips::MSA128BRegClass,	4767	&Mips::MSA128BRegClass,
4768	&Mips::MSA128DRegClass,	4768	&Mips::MSA128DRegClass,
4769	&Mips::MSA128HRegClass,	4769	&Mips::MSA128HRegClass,
4770	nullptr	4770	nullptr
4771	};	4771	};
4772		4772
4773	static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {	4773	static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4774	&Mips::MSA128F16RegClass,	4774	&Mips::MSA128F16RegClass,
4775	&Mips::MSA128BRegClass,	4775	&Mips::MSA128BRegClass,
4776	&Mips::MSA128DRegClass,	4776	&Mips::MSA128DRegClass,
4777	&Mips::MSA128HRegClass,	4777	&Mips::MSA128HRegClass,
4778	&Mips::MSA128WRegClass,	4778	&Mips::MSA128WRegClass,
4779	nullptr	4779	nullptr
4780	};	4780	};
4781		4781
4782		4782
4783	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {	4783	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {
4784	const auto & S = MF.getSubtarget();	4784	const auto & S = MF.getSubtarget();
4785	return S.isABI_O32() && !S.useOddSPReg();	4785	return S.isABI_O32() && !S.useOddSPReg();
4786	}	4786	}
4787		4787
4788	static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) {	4788	static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) {
4789	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };	4789	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
4790	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];	4790	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4791	const ArrayRef Order[] = {	4791	const ArrayRef Order[] = {
4792	ArrayRef(MCR.begin(), MCR.getNumRegs()),	4792	ArrayRef(MCR.begin(), MCR.getNumRegs()),
4793	ArrayRef(AltOrder1)	4793	ArrayRef(AltOrder1)
4794	};	4794	};
4795	const unsigned Select = FGR32AltOrderSelect(MF);	4795	const unsigned Select = FGR32AltOrderSelect(MF);
4796	assert(Select < 2);	4796	assert(Select < 2);
4797	return Order[Select];	4797	return Order[Select];
4798	}	4798	}
4799		4799
4800	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {	4800	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {
4801	const auto & S = MF.getSubtarget();	4801	const auto & S = MF.getSubtarget();
4802	return S.isABI_O32() && !S.useOddSPReg();	4802	return S.isABI_O32() && !S.useOddSPReg();
4803	}	4803	}
4804		4804
4805	static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) {	4805	static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) {
4806	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };	4806	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
4807	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];	4807	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4808	const ArrayRef Order[] = {	4808	const ArrayRef Order[] = {
4809	ArrayRef(MCR.begin(), MCR.getNumRegs()),	4809	ArrayRef(MCR.begin(), MCR.getNumRegs()),
4810	ArrayRef(AltOrder1)	4810	ArrayRef(AltOrder1)
4811	};	4811	};
4812	const unsigned Select = FGR64AltOrderSelect(MF);	4812	const unsigned Select = FGR64AltOrderSelect(MF);
4813	assert(Select < 2);	4813	assert(Select < 2);
4814	return Order[Select];	4814	return Order[Select];
4815	}	4815	}
4816		4816
4817	namespace Mips { // Register class instances	4817	namespace Mips { // Register class instances
4818	extern const TargetRegisterClass MSA128F16RegClass = {	4818	extern const TargetRegisterClass MSA128F16RegClass = {
4819	&MipsMCRegisterClasses[MSA128F16RegClassID],	4819	&MipsMCRegisterClasses[MSA128F16RegClassID],
4820	MSA128F16SubClassMask,	4820	MSA128F16SubClassMask,
4821	SuperRegIdxSeqs + 1,	4821	SuperRegIdxSeqs + 1,
4822	LaneBitmask(0x0000000000000041),	4822	LaneBitmask(0x0000000000000041),
4823	0,	4823	0,
4824	false,	4824	false,
4825	0x00, /* TSFlags */	4825	0x00, /* TSFlags */
4826	true, /* HasDisjunctSubRegs */	4826	true, /* HasDisjunctSubRegs */
4827	false, /* CoveredBySubRegs */	4827	false, /* CoveredBySubRegs */
4828	NullRegClasses,	4828	NullRegClasses,
4829	nullptr	4829	nullptr
4830	};	4830	};
4831		4831
4832	extern const TargetRegisterClass CCRRegClass = {	4832	extern const TargetRegisterClass CCRRegClass = {
4833	&MipsMCRegisterClasses[CCRRegClassID],	4833	&MipsMCRegisterClasses[CCRRegClassID],
4834	CCRSubClassMask,	4834	CCRSubClassMask,
4835	SuperRegIdxSeqs + 1,	4835	SuperRegIdxSeqs + 1,
4836	LaneBitmask(0x0000000000000001),	4836	LaneBitmask(0x0000000000000001),
4837	0,	4837	0,
4838	false,	4838	false,
4839	0x00, /* TSFlags */	4839	0x00, /* TSFlags */
4840	false, /* HasDisjunctSubRegs */	4840	false, /* HasDisjunctSubRegs */
4841	false, /* CoveredBySubRegs */	4841	false, /* CoveredBySubRegs */
4842	NullRegClasses,	4842	NullRegClasses,
4843	nullptr	4843	nullptr
4844	};	4844	};
4845		4845
4846	extern const TargetRegisterClass COP0RegClass = {	4846	extern const TargetRegisterClass COP0RegClass = {
4847	&MipsMCRegisterClasses[COP0RegClassID],	4847	&MipsMCRegisterClasses[COP0RegClassID],
4848	COP0SubClassMask,	4848	COP0SubClassMask,
4849	SuperRegIdxSeqs + 1,	4849	SuperRegIdxSeqs + 1,
4850	LaneBitmask(0x0000000000000001),	4850	LaneBitmask(0x0000000000000001),
4851	0,	4851	0,
4852	false,	4852	false,
4853	0x00, /* TSFlags */	4853	0x00, /* TSFlags */
4854	false, /* HasDisjunctSubRegs */	4854	false, /* HasDisjunctSubRegs */
4855	false, /* CoveredBySubRegs */	4855	false, /* CoveredBySubRegs */
4856	NullRegClasses,	4856	NullRegClasses,
4857	nullptr	4857	nullptr
4858	};	4858	};
4859		4859
4860	extern const TargetRegisterClass COP2RegClass = {	4860	extern const TargetRegisterClass COP2RegClass = {
4861	&MipsMCRegisterClasses[COP2RegClassID],	4861	&MipsMCRegisterClasses[COP2RegClassID],
4862	COP2SubClassMask,	4862	COP2SubClassMask,
4863	SuperRegIdxSeqs + 1,	4863	SuperRegIdxSeqs + 1,
4864	LaneBitmask(0x0000000000000001),	4864	LaneBitmask(0x0000000000000001),
4865	0,	4865	0,
4866	false,	4866	false,
4867	0x00, /* TSFlags */	4867	0x00, /* TSFlags */
4868	false, /* HasDisjunctSubRegs */	4868	false, /* HasDisjunctSubRegs */
4869	false, /* CoveredBySubRegs */	4869	false, /* CoveredBySubRegs */
4870	NullRegClasses,	4870	NullRegClasses,
4871	nullptr	4871	nullptr
4872	};	4872	};
4873		4873
4874	extern const TargetRegisterClass COP3RegClass = {	4874	extern const TargetRegisterClass COP3RegClass = {
4875	&MipsMCRegisterClasses[COP3RegClassID],	4875	&MipsMCRegisterClasses[COP3RegClassID],
4876	COP3SubClassMask,	4876	COP3SubClassMask,
4877	SuperRegIdxSeqs + 1,	4877	SuperRegIdxSeqs + 1,
4878	LaneBitmask(0x0000000000000001),	4878	LaneBitmask(0x0000000000000001),
4879	0,	4879	0,
4880	false,	4880	false,
4881	0x00, /* TSFlags */	4881	0x00, /* TSFlags */
4882	false, /* HasDisjunctSubRegs */	4882	false, /* HasDisjunctSubRegs */
4883	false, /* CoveredBySubRegs */	4883	false, /* CoveredBySubRegs */
4884	NullRegClasses,	4884	NullRegClasses,
4885	nullptr	4885	nullptr
4886	};	4886	};
4887		4887
4888	extern const TargetRegisterClass DSPRRegClass = {	4888	extern const TargetRegisterClass DSPRRegClass = {
4889	&MipsMCRegisterClasses[DSPRRegClassID],	4889	&MipsMCRegisterClasses[DSPRRegClassID],
4890	DSPRSubClassMask,	4890	DSPRSubClassMask,
4891	SuperRegIdxSeqs + 0,	4891	SuperRegIdxSeqs + 0,
4892	LaneBitmask(0x0000000000000001),	4892	LaneBitmask(0x0000000000000001),
4893	0,	4893	0,
4894	false,	4894	false,
4895	0x00, /* TSFlags */	4895	0x00, /* TSFlags */
4896	false, /* HasDisjunctSubRegs */	4896	false, /* HasDisjunctSubRegs */
4897	false, /* CoveredBySubRegs */	4897	false, /* CoveredBySubRegs */
4898	NullRegClasses,	4898	NullRegClasses,
4899	nullptr	4899	nullptr
4900	};	4900	};
4901		4901
4902	extern const TargetRegisterClass FGR32RegClass = {	4902	extern const TargetRegisterClass FGR32RegClass = {
4903	&MipsMCRegisterClasses[FGR32RegClassID],	4903	&MipsMCRegisterClasses[FGR32RegClassID],
4904	FGR32SubClassMask,	4904	FGR32SubClassMask,
4905	SuperRegIdxSeqs + 9,	4905	SuperRegIdxSeqs + 9,
4906	LaneBitmask(0x0000000000000001),	4906	LaneBitmask(0x0000000000000001),
4907	0,	4907	0,
4908	false,	4908	false,
4909	0x00, /* TSFlags */	4909	0x00, /* TSFlags */
4910	false, /* HasDisjunctSubRegs */	4910	false, /* HasDisjunctSubRegs */
4911	false, /* CoveredBySubRegs */	4911	false, /* CoveredBySubRegs */
4912	FGR32Superclasses,	4912	FGR32Superclasses,
4913	FGR32GetRawAllocationOrder	4913	FGR32GetRawAllocationOrder
4914	};	4914	};
4915		4915
4916	extern const TargetRegisterClass FGRCCRegClass = {	4916	extern const TargetRegisterClass FGRCCRegClass = {
4917	&MipsMCRegisterClasses[FGRCCRegClassID],	4917	&MipsMCRegisterClasses[FGRCCRegClassID],
4918	FGRCCSubClassMask,	4918	FGRCCSubClassMask,
4919	SuperRegIdxSeqs + 9,	4919	SuperRegIdxSeqs + 9,
4920	LaneBitmask(0x0000000000000001),	4920	LaneBitmask(0x0000000000000001),
4921	0,	4921	0,
4922	false,	4922	false,
4923	0x00, /* TSFlags */	4923	0x00, /* TSFlags */
4924	false, /* HasDisjunctSubRegs */	4924	false, /* HasDisjunctSubRegs */
4925	false, /* CoveredBySubRegs */	4925	false, /* CoveredBySubRegs */
4926	FGRCCSuperclasses,	4926	FGRCCSuperclasses,
4927	nullptr	4927	nullptr
4928	};	4928	};
4929		4929
4930	extern const TargetRegisterClass GPR32RegClass = {	4930	extern const TargetRegisterClass GPR32RegClass = {
4931	&MipsMCRegisterClasses[GPR32RegClassID],	4931	&MipsMCRegisterClasses[GPR32RegClassID],
4932	GPR32SubClassMask,	4932	GPR32SubClassMask,
4933	SuperRegIdxSeqs + 0,	4933	SuperRegIdxSeqs + 0,
4934	LaneBitmask(0x0000000000000001),	4934	LaneBitmask(0x0000000000000001),
4935	0,	4935	0,
4936	false,	4936	false,
4937	0x00, /* TSFlags */	4937	0x00, /* TSFlags */
4938	false, /* HasDisjunctSubRegs */	4938	false, /* HasDisjunctSubRegs */
4939	false, /* CoveredBySubRegs */	4939	false, /* CoveredBySubRegs */
4940	GPR32Superclasses,	4940	GPR32Superclasses,
4941	nullptr	4941	nullptr
4942	};	4942	};
4943		4943
4944	extern const TargetRegisterClass HWRegsRegClass = {	4944	extern const TargetRegisterClass HWRegsRegClass = {
4945	&MipsMCRegisterClasses[HWRegsRegClassID],	4945	&MipsMCRegisterClasses[HWRegsRegClassID],
4946	HWRegsSubClassMask,	4946	HWRegsSubClassMask,
4947	SuperRegIdxSeqs + 1,	4947	SuperRegIdxSeqs + 1,
4948	LaneBitmask(0x0000000000000001),	4948	LaneBitmask(0x0000000000000001),
4949	0,	4949	0,
4950	false,	4950	false,
4951	0x00, /* TSFlags */	4951	0x00, /* TSFlags */
4952	false, /* HasDisjunctSubRegs */	4952	false, /* HasDisjunctSubRegs */
4953	false, /* CoveredBySubRegs */	4953	false, /* CoveredBySubRegs */
4954	NullRegClasses,	4954	NullRegClasses,
4955	nullptr	4955	nullptr
4956	};	4956	};
4957		4957
4958	extern const TargetRegisterClass MSACtrlRegClass = {	4958	extern const TargetRegisterClass MSACtrlRegClass = {
4959	&MipsMCRegisterClasses[MSACtrlRegClassID],	4959	&MipsMCRegisterClasses[MSACtrlRegClassID],
4960	MSACtrlSubClassMask,	4960	MSACtrlSubClassMask,
4961	SuperRegIdxSeqs + 1,	4961	SuperRegIdxSeqs + 1,
4962	LaneBitmask(0x0000000000000001),	4962	LaneBitmask(0x0000000000000001),
4963	0,	4963	0,
4964	false,	4964	false,
4965	0x00, /* TSFlags */	4965	0x00, /* TSFlags */
4966	false, /* HasDisjunctSubRegs */	4966	false, /* HasDisjunctSubRegs */
4967	false, /* CoveredBySubRegs */	4967	false, /* CoveredBySubRegs */
4968	NullRegClasses,	4968	NullRegClasses,
4969	nullptr	4969	nullptr
4970	};	4970	};
4971		4971
4972	extern const TargetRegisterClass GPR32NONZERORegClass = {	4972	extern const TargetRegisterClass GPR32NONZERORegClass = {
4973	&MipsMCRegisterClasses[GPR32NONZERORegClassID],	4973	&MipsMCRegisterClasses[GPR32NONZERORegClassID],
4974	GPR32NONZEROSubClassMask,	4974	GPR32NONZEROSubClassMask,
4975	SuperRegIdxSeqs + 0,	4975	SuperRegIdxSeqs + 0,
4976	LaneBitmask(0x0000000000000001),	4976	LaneBitmask(0x0000000000000001),
4977	0,	4977	0,
4978	false,	4978	false,
4979	0x00, /* TSFlags */	4979	0x00, /* TSFlags */
4980	false, /* HasDisjunctSubRegs */	4980	false, /* HasDisjunctSubRegs */
4981	false, /* CoveredBySubRegs */	4981	false, /* CoveredBySubRegs */
4982	GPR32NONZEROSuperclasses,	4982	GPR32NONZEROSuperclasses,
4983	nullptr	4983	nullptr
4984	};	4984	};
4985		4985
4986	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {	4986	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4987	&MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],	4987	&MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
4988	CPU16RegsPlusSPSubClassMask,	4988	CPU16RegsPlusSPSubClassMask,
4989	SuperRegIdxSeqs + 0,	4989	SuperRegIdxSeqs + 0,
4990	LaneBitmask(0x0000000000000001),	4990	LaneBitmask(0x0000000000000001),
4991	0,	4991	0,
4992	false,	4992	false,
4993	0x00, /* TSFlags */	4993	0x00, /* TSFlags */
4994	false, /* HasDisjunctSubRegs */	4994	false, /* HasDisjunctSubRegs */
4995	false, /* CoveredBySubRegs */	4995	false, /* CoveredBySubRegs */
4996	CPU16RegsPlusSPSuperclasses,	4996	CPU16RegsPlusSPSuperclasses,
4997	nullptr	4997	nullptr
4998	};	4998	};
4999		4999
5000	extern const TargetRegisterClass CPU16RegsRegClass = {	5000	extern const TargetRegisterClass CPU16RegsRegClass = {
5001	&MipsMCRegisterClasses[CPU16RegsRegClassID],	5001	&MipsMCRegisterClasses[CPU16RegsRegClassID],
5002	CPU16RegsSubClassMask,	5002	CPU16RegsSubClassMask,
5003	SuperRegIdxSeqs + 0,	5003	SuperRegIdxSeqs + 0,
5004	LaneBitmask(0x0000000000000001),	5004	LaneBitmask(0x0000000000000001),
5005	0,	5005	0,
5006	false,	5006	false,
5007	0x00, /* TSFlags */	5007	0x00, /* TSFlags */
5008	false, /* HasDisjunctSubRegs */	5008	false, /* HasDisjunctSubRegs */
5009	false, /* CoveredBySubRegs */	5009	false, /* CoveredBySubRegs */
5010	CPU16RegsSuperclasses,	5010	CPU16RegsSuperclasses,
5011	nullptr	5011	nullptr
5012	};	5012	};
5013		5013
5014	extern const TargetRegisterClass FCCRegClass = {	5014	extern const TargetRegisterClass FCCRegClass = {
5015	&MipsMCRegisterClasses[FCCRegClassID],	5015	&MipsMCRegisterClasses[FCCRegClassID],
5016	FCCSubClassMask,	5016	FCCSubClassMask,
5017	SuperRegIdxSeqs + 1,	5017	SuperRegIdxSeqs + 1,
5018	LaneBitmask(0x0000000000000001),	5018	LaneBitmask(0x0000000000000001),
5019	0,	5019	0,
5020	false,	5020	false,
5021	0x00, /* TSFlags */	5021	0x00, /* TSFlags */
5022	false, /* HasDisjunctSubRegs */	5022	false, /* HasDisjunctSubRegs */
5023	false, /* CoveredBySubRegs */	5023	false, /* CoveredBySubRegs */
5024	NullRegClasses,	5024	NullRegClasses,
5025	nullptr	5025	nullptr
5026	};	5026	};
5027		5027
5028	extern const TargetRegisterClass GPRMM16RegClass = {	5028	extern const TargetRegisterClass GPRMM16RegClass = {
5029	&MipsMCRegisterClasses[GPRMM16RegClassID],	5029	&MipsMCRegisterClasses[GPRMM16RegClassID],
5030	GPRMM16SubClassMask,	5030	GPRMM16SubClassMask,
5031	SuperRegIdxSeqs + 0,	5031	SuperRegIdxSeqs + 0,
5032	LaneBitmask(0x0000000000000001),	5032	LaneBitmask(0x0000000000000001),
5033	0,	5033	0,
5034	false,	5034	false,
5035	0x00, /* TSFlags */	5035	0x00, /* TSFlags */
5036	false, /* HasDisjunctSubRegs */	5036	false, /* HasDisjunctSubRegs */
5037	false, /* CoveredBySubRegs */	5037	false, /* CoveredBySubRegs */
5038	GPRMM16Superclasses,	5038	GPRMM16Superclasses,
5039	nullptr	5039	nullptr
5040	};	5040	};
5041		5041
5042	extern const TargetRegisterClass GPRMM16MovePRegClass = {	5042	extern const TargetRegisterClass GPRMM16MovePRegClass = {
5043	&MipsMCRegisterClasses[GPRMM16MovePRegClassID],	5043	&MipsMCRegisterClasses[GPRMM16MovePRegClassID],
5044	GPRMM16MovePSubClassMask,	5044	GPRMM16MovePSubClassMask,
5045	SuperRegIdxSeqs + 0,	5045	SuperRegIdxSeqs + 0,
5046	LaneBitmask(0x0000000000000001),	5046	LaneBitmask(0x0000000000000001),
5047	0,	5047	0,
5048	false,	5048	false,
5049	0x00, /* TSFlags */	5049	0x00, /* TSFlags */
5050	false, /* HasDisjunctSubRegs */	5050	false, /* HasDisjunctSubRegs */
5051	false, /* CoveredBySubRegs */	5051	false, /* CoveredBySubRegs */
5052	GPRMM16MovePSuperclasses,	5052	GPRMM16MovePSuperclasses,
5053	nullptr	5053	nullptr
5054	};	5054	};
5055		5055
5056	extern const TargetRegisterClass GPRMM16ZeroRegClass = {	5056	extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5057	&MipsMCRegisterClasses[GPRMM16ZeroRegClassID],	5057	&MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
5058	GPRMM16ZeroSubClassMask,	5058	GPRMM16ZeroSubClassMask,
5059	SuperRegIdxSeqs + 0,	5059	SuperRegIdxSeqs + 0,
5060	LaneBitmask(0x0000000000000001),	5060	LaneBitmask(0x0000000000000001),
5061	0,	5061	0,
5062	false,	5062	false,
5063	0x00, /* TSFlags */	5063	0x00, /* TSFlags */
5064	false, /* HasDisjunctSubRegs */	5064	false, /* HasDisjunctSubRegs */
5065	false, /* CoveredBySubRegs */	5065	false, /* CoveredBySubRegs */
5066	GPRMM16ZeroSuperclasses,	5066	GPRMM16ZeroSuperclasses,
5067	nullptr	5067	nullptr
5068	};	5068	};
5069		5069
5070	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {	5070	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5071	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],	5071	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
5072	CPU16Regs_and_GPRMM16ZeroSubClassMask,	5072	CPU16Regs_and_GPRMM16ZeroSubClassMask,
5073	SuperRegIdxSeqs + 0,	5073	SuperRegIdxSeqs + 0,
5074	LaneBitmask(0x0000000000000001),	5074	LaneBitmask(0x0000000000000001),
5075	0,	5075	0,
5076	false,	5076	false,
5077	0x00, /* TSFlags */	5077	0x00, /* TSFlags */
5078	false, /* HasDisjunctSubRegs */	5078	false, /* HasDisjunctSubRegs */
5079	false, /* CoveredBySubRegs */	5079	false, /* CoveredBySubRegs */
5080	CPU16Regs_and_GPRMM16ZeroSuperclasses,	5080	CPU16Regs_and_GPRMM16ZeroSuperclasses,
5081	nullptr	5081	nullptr
5082	};	5082	};
5083		5083
5084	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {	5084	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5085	&MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],	5085	&MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
5086	GPR32NONZERO_and_GPRMM16MovePSubClassMask,	5086	GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5087	SuperRegIdxSeqs + 0,	5087	SuperRegIdxSeqs + 0,
5088	LaneBitmask(0x0000000000000001),	5088	LaneBitmask(0x0000000000000001),
5089	0,	5089	0,
5090	false,	5090	false,
5091	0x00, /* TSFlags */	5091	0x00, /* TSFlags */
5092	false, /* HasDisjunctSubRegs */	5092	false, /* HasDisjunctSubRegs */
5093	false, /* CoveredBySubRegs */	5093	false, /* CoveredBySubRegs */
5094	GPR32NONZERO_and_GPRMM16MovePSuperclasses,	5094	GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5095	nullptr	5095	nullptr
5096	};	5096	};
5097		5097
5098	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {	5098	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5099	&MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],	5099	&MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
5100	GPRMM16MovePPairSecondSubClassMask,	5100	GPRMM16MovePPairSecondSubClassMask,
5101	SuperRegIdxSeqs + 0,	5101	SuperRegIdxSeqs + 0,
5102	LaneBitmask(0x0000000000000001),	5102	LaneBitmask(0x0000000000000001),
5103	0,	5103	0,
5104	false,	5104	false,
5105	0x00, /* TSFlags */	5105	0x00, /* TSFlags */
5106	false, /* HasDisjunctSubRegs */	5106	false, /* HasDisjunctSubRegs */
5107	false, /* CoveredBySubRegs */	5107	false, /* CoveredBySubRegs */
5108	GPRMM16MovePPairSecondSuperclasses,	5108	GPRMM16MovePPairSecondSuperclasses,
5109	nullptr	5109	nullptr
5110	};	5110	};
5111		5111
5112	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {	5112	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5113	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],	5113	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
5114	CPU16Regs_and_GPRMM16MovePSubClassMask,	5114	CPU16Regs_and_GPRMM16MovePSubClassMask,
5115	SuperRegIdxSeqs + 0,	5115	SuperRegIdxSeqs + 0,
5116	LaneBitmask(0x0000000000000001),	5116	LaneBitmask(0x0000000000000001),
5117	0,	5117	0,
5118	false,	5118	false,
5119	0x00, /* TSFlags */	5119	0x00, /* TSFlags */
5120	false, /* HasDisjunctSubRegs */	5120	false, /* HasDisjunctSubRegs */
5121	false, /* CoveredBySubRegs */	5121	false, /* CoveredBySubRegs */
5122	CPU16Regs_and_GPRMM16MovePSuperclasses,	5122	CPU16Regs_and_GPRMM16MovePSuperclasses,
5123	nullptr	5123	nullptr
5124	};	5124	};
5125		5125
5126	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	5126	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5127	&MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	5127	&MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5128	GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	5128	GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5129	SuperRegIdxSeqs + 0,	5129	SuperRegIdxSeqs + 0,
5130	LaneBitmask(0x0000000000000001),	5130	LaneBitmask(0x0000000000000001),
5131	0,	5131	0,
5132	false,	5132	false,
5133	0x00, /* TSFlags */	5133	0x00, /* TSFlags */
5134	false, /* HasDisjunctSubRegs */	5134	false, /* HasDisjunctSubRegs */
5135	false, /* CoveredBySubRegs */	5135	false, /* CoveredBySubRegs */
5136	GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	5136	GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5137	nullptr	5137	nullptr
5138	};	5138	};
5139		5139
5140	extern const TargetRegisterClass HI32DSPRegClass = {	5140	extern const TargetRegisterClass HI32DSPRegClass = {
5141	&MipsMCRegisterClasses[HI32DSPRegClassID],	5141	&MipsMCRegisterClasses[HI32DSPRegClassID],
5142	HI32DSPSubClassMask,	5142	HI32DSPSubClassMask,
5143	SuperRegIdxSeqs + 12,	5143	SuperRegIdxSeqs + 12,
5144	LaneBitmask(0x0000000000000001),	5144	LaneBitmask(0x0000000000000001),
5145	0,	5145	0,
5146	false,	5146	false,
5147	0x00, /* TSFlags */	5147	0x00, /* TSFlags */
5148	false, /* HasDisjunctSubRegs */	5148	false, /* HasDisjunctSubRegs */
5149	false, /* CoveredBySubRegs */	5149	false, /* CoveredBySubRegs */
5150	NullRegClasses,	5150	NullRegClasses,
5151	nullptr	5151	nullptr
5152	};	5152	};
5153		5153
5154	extern const TargetRegisterClass LO32DSPRegClass = {	5154	extern const TargetRegisterClass LO32DSPRegClass = {
5155	&MipsMCRegisterClasses[LO32DSPRegClassID],	5155	&MipsMCRegisterClasses[LO32DSPRegClassID],
5156	LO32DSPSubClassMask,	5156	LO32DSPSubClassMask,
5157	SuperRegIdxSeqs + 6,	5157	SuperRegIdxSeqs + 6,
5158	LaneBitmask(0x0000000000000001),	5158	LaneBitmask(0x0000000000000001),
5159	0,	5159	0,
5160	false,	5160	false,
5161	0x00, /* TSFlags */	5161	0x00, /* TSFlags */
5162	false, /* HasDisjunctSubRegs */	5162	false, /* HasDisjunctSubRegs */
5163	false, /* CoveredBySubRegs */	5163	false, /* CoveredBySubRegs */
5164	NullRegClasses,	5164	NullRegClasses,
5165	nullptr	5165	nullptr
5166	};	5166	};
5167		5167
5168	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	5168	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5169	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	5169	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5170	CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	5170	CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5171	SuperRegIdxSeqs + 0,	5171	SuperRegIdxSeqs + 0,
5172	LaneBitmask(0x0000000000000001),	5172	LaneBitmask(0x0000000000000001),
5173	0,	5173	0,
5174	false,	5174	false,
5175	0x00, /* TSFlags */	5175	0x00, /* TSFlags */
5176	false, /* HasDisjunctSubRegs */	5176	false, /* HasDisjunctSubRegs */
5177	false, /* CoveredBySubRegs */	5177	false, /* CoveredBySubRegs */
5178	CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	5178	CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5179	nullptr	5179	nullptr
5180	};	5180	};
5181		5181
5182	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {	5182	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5183	&MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],	5183	&MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
5184	GPRMM16MovePPairFirstSubClassMask,	5184	GPRMM16MovePPairFirstSubClassMask,
5185	SuperRegIdxSeqs + 0,	5185	SuperRegIdxSeqs + 0,
5186	LaneBitmask(0x0000000000000001),	5186	LaneBitmask(0x0000000000000001),
5187	0,	5187	0,
5188	false,	5188	false,
5189	0x00, /* TSFlags */	5189	0x00, /* TSFlags */
5190	false, /* HasDisjunctSubRegs */	5190	false, /* HasDisjunctSubRegs */
5191	false, /* CoveredBySubRegs */	5191	false, /* CoveredBySubRegs */
5192	GPRMM16MovePPairFirstSuperclasses,	5192	GPRMM16MovePPairFirstSuperclasses,
5193	nullptr	5193	nullptr
5194	};	5194	};
5195		5195
5196	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	5196	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5197	&MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	5197	&MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5198	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	5198	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5199	SuperRegIdxSeqs + 0,	5199	SuperRegIdxSeqs + 0,
5200	LaneBitmask(0x0000000000000001),	5200	LaneBitmask(0x0000000000000001),
5201	0,	5201	0,
5202	false,	5202	false,
5203	0x00, /* TSFlags */	5203	0x00, /* TSFlags */
5204	false, /* HasDisjunctSubRegs */	5204	false, /* HasDisjunctSubRegs */
5205	false, /* CoveredBySubRegs */	5205	false, /* CoveredBySubRegs */
5206	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	5206	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5207	nullptr	5207	nullptr
5208	};	5208	};
5209		5209
5210	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	5210	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5211	&MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	5211	&MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5212	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	5212	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5213	SuperRegIdxSeqs + 0,	5213	SuperRegIdxSeqs + 0,
5214	LaneBitmask(0x0000000000000001),	5214	LaneBitmask(0x0000000000000001),
5215	0,	5215	0,
5216	false,	5216	false,
5217	0x00, /* TSFlags */	5217	0x00, /* TSFlags */
5218	false, /* HasDisjunctSubRegs */	5218	false, /* HasDisjunctSubRegs */
5219	false, /* CoveredBySubRegs */	5219	false, /* CoveredBySubRegs */
5220	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	5220	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5221	nullptr	5221	nullptr
5222	};	5222	};
5223		5223
5224	extern const TargetRegisterClass CPURARegRegClass = {	5224	extern const TargetRegisterClass CPURARegRegClass = {
5225	&MipsMCRegisterClasses[CPURARegRegClassID],	5225	&MipsMCRegisterClasses[CPURARegRegClassID],
5226	CPURARegSubClassMask,	5226	CPURARegSubClassMask,
5227	SuperRegIdxSeqs + 0,	5227	SuperRegIdxSeqs + 0,
5228	LaneBitmask(0x0000000000000001),	5228	LaneBitmask(0x0000000000000001),
5229	0,	5229	0,
5230	false,	5230	false,
5231	0x00, /* TSFlags */	5231	0x00, /* TSFlags */
5232	false, /* HasDisjunctSubRegs */	5232	false, /* HasDisjunctSubRegs */
5233	false, /* CoveredBySubRegs */	5233	false, /* CoveredBySubRegs */
5234	CPURARegSuperclasses,	5234	CPURARegSuperclasses,
5235	nullptr	5235	nullptr
5236	};	5236	};
5237		5237
5238	extern const TargetRegisterClass CPUSPRegRegClass = {	5238	extern const TargetRegisterClass CPUSPRegRegClass = {
5239	&MipsMCRegisterClasses[CPUSPRegRegClassID],	5239	&MipsMCRegisterClasses[CPUSPRegRegClassID],
5240	CPUSPRegSubClassMask,	5240	CPUSPRegSubClassMask,
5241	SuperRegIdxSeqs + 0,	5241	SuperRegIdxSeqs + 0,
5242	LaneBitmask(0x0000000000000001),	5242	LaneBitmask(0x0000000000000001),
5243	0,	5243	0,
5244	false,	5244	false,
5245	0x00, /* TSFlags */	5245	0x00, /* TSFlags */
5246	false, /* HasDisjunctSubRegs */	5246	false, /* HasDisjunctSubRegs */
5247	false, /* CoveredBySubRegs */	5247	false, /* CoveredBySubRegs */
5248	CPUSPRegSuperclasses,	5248	CPUSPRegSuperclasses,
5249	nullptr	5249	nullptr
5250	};	5250	};
5251		5251
5252	extern const TargetRegisterClass DSPCCRegClass = {	5252	extern const TargetRegisterClass DSPCCRegClass = {
5253	&MipsMCRegisterClasses[DSPCCRegClassID],	5253	&MipsMCRegisterClasses[DSPCCRegClassID],
5254	DSPCCSubClassMask,	5254	DSPCCSubClassMask,
5255	SuperRegIdxSeqs + 1,	5255	SuperRegIdxSeqs + 1,
5256	LaneBitmask(0x0000000000000001),	5256	LaneBitmask(0x0000000000000001),
5257	0,	5257	0,
5258	false,	5258	false,
5259	0x00, /* TSFlags */	5259	0x00, /* TSFlags */
5260	false, /* HasDisjunctSubRegs */	5260	false, /* HasDisjunctSubRegs */
5261	false, /* CoveredBySubRegs */	5261	false, /* CoveredBySubRegs */
5262	NullRegClasses,	5262	NullRegClasses,
5263	nullptr	5263	nullptr
5264	};	5264	};
5265		5265
5266	extern const TargetRegisterClass GP32RegClass = {	5266	extern const TargetRegisterClass GP32RegClass = {
5267	&MipsMCRegisterClasses[GP32RegClassID],	5267	&MipsMCRegisterClasses[GP32RegClassID],
5268	GP32SubClassMask,	5268	GP32SubClassMask,
5269	SuperRegIdxSeqs + 0,	5269	SuperRegIdxSeqs + 0,
5270	LaneBitmask(0x0000000000000001),	5270	LaneBitmask(0x0000000000000001),
5271	0,	5271	0,
5272	false,	5272	false,
5273	0x00, /* TSFlags */	5273	0x00, /* TSFlags */
5274	false, /* HasDisjunctSubRegs */	5274	false, /* HasDisjunctSubRegs */
5275	false, /* CoveredBySubRegs */	5275	false, /* CoveredBySubRegs */
5276	GP32Superclasses,	5276	GP32Superclasses,
5277	nullptr	5277	nullptr
5278	};	5278	};
5279		5279
5280	extern const TargetRegisterClass GPR32ZERORegClass = {	5280	extern const TargetRegisterClass GPR32ZERORegClass = {
5281	&MipsMCRegisterClasses[GPR32ZERORegClassID],	5281	&MipsMCRegisterClasses[GPR32ZERORegClassID],
5282	GPR32ZEROSubClassMask,	5282	GPR32ZEROSubClassMask,
5283	SuperRegIdxSeqs + 0,	5283	SuperRegIdxSeqs + 0,
5284	LaneBitmask(0x0000000000000001),	5284	LaneBitmask(0x0000000000000001),
5285	0,	5285	0,
5286	false,	5286	false,
5287	0x00, /* TSFlags */	5287	0x00, /* TSFlags */
5288	false, /* HasDisjunctSubRegs */	5288	false, /* HasDisjunctSubRegs */
5289	false, /* CoveredBySubRegs */	5289	false, /* CoveredBySubRegs */
5290	GPR32ZEROSuperclasses,	5290	GPR32ZEROSuperclasses,
5291	nullptr	5291	nullptr
5292	};	5292	};
5293		5293
5294	extern const TargetRegisterClass HI32RegClass = {	5294	extern const TargetRegisterClass HI32RegClass = {
5295	&MipsMCRegisterClasses[HI32RegClassID],	5295	&MipsMCRegisterClasses[HI32RegClassID],
5296	HI32SubClassMask,	5296	HI32SubClassMask,
5297	SuperRegIdxSeqs + 12,	5297	SuperRegIdxSeqs + 12,
5298	LaneBitmask(0x0000000000000001),	5298	LaneBitmask(0x0000000000000001),
5299	0,	5299	0,
5300	false,	5300	false,
5301	0x00, /* TSFlags */	5301	0x00, /* TSFlags */
5302	false, /* HasDisjunctSubRegs */	5302	false, /* HasDisjunctSubRegs */
5303	false, /* CoveredBySubRegs */	5303	false, /* CoveredBySubRegs */
5304	HI32Superclasses,	5304	HI32Superclasses,
5305	nullptr	5305	nullptr
5306	};	5306	};
5307		5307
5308	extern const TargetRegisterClass LO32RegClass = {	5308	extern const TargetRegisterClass LO32RegClass = {
5309	&MipsMCRegisterClasses[LO32RegClassID],	5309	&MipsMCRegisterClasses[LO32RegClassID],
5310	LO32SubClassMask,	5310	LO32SubClassMask,
5311	SuperRegIdxSeqs + 6,	5311	SuperRegIdxSeqs + 6,
5312	LaneBitmask(0x0000000000000001),	5312	LaneBitmask(0x0000000000000001),
5313	0,	5313	0,
5314	false,	5314	false,
5315	0x00, /* TSFlags */	5315	0x00, /* TSFlags */
5316	false, /* HasDisjunctSubRegs */	5316	false, /* HasDisjunctSubRegs */
5317	false, /* CoveredBySubRegs */	5317	false, /* CoveredBySubRegs */
5318	LO32Superclasses,	5318	LO32Superclasses,
5319	nullptr	5319	nullptr
5320	};	5320	};
5321		5321
5322	extern const TargetRegisterClass SP32RegClass = {	5322	extern const TargetRegisterClass SP32RegClass = {
5323	&MipsMCRegisterClasses[SP32RegClassID],	5323	&MipsMCRegisterClasses[SP32RegClassID],
5324	SP32SubClassMask,	5324	SP32SubClassMask,
5325	SuperRegIdxSeqs + 0,	5325	SuperRegIdxSeqs + 0,
5326	LaneBitmask(0x0000000000000001),	5326	LaneBitmask(0x0000000000000001),
5327	0,	5327	0,
5328	false,	5328	false,
5329	0x00, /* TSFlags */	5329	0x00, /* TSFlags */
5330	false, /* HasDisjunctSubRegs */	5330	false, /* HasDisjunctSubRegs */
5331	false, /* CoveredBySubRegs */	5331	false, /* CoveredBySubRegs */
5332	SP32Superclasses,	5332	SP32Superclasses,
5333	nullptr	5333	nullptr
5334	};	5334	};
5335		5335
5336	extern const TargetRegisterClass FGR64RegClass = {	5336	extern const TargetRegisterClass FGR64RegClass = {
5337	&MipsMCRegisterClasses[FGR64RegClassID],	5337	&MipsMCRegisterClasses[FGR64RegClassID],
5338	FGR64SubClassMask,	5338	FGR64SubClassMask,
5339	SuperRegIdxSeqs + 2,	5339	SuperRegIdxSeqs + 2,
5340	LaneBitmask(0x0000000000000041),	5340	LaneBitmask(0x0000000000000041),
5341	0,	5341	0,
5342	false,	5342	false,
5343	0x00, /* TSFlags */	5343	0x00, /* TSFlags */
5344	true, /* HasDisjunctSubRegs */	5344	true, /* HasDisjunctSubRegs */
5345	true, /* CoveredBySubRegs */	5345	true, /* CoveredBySubRegs */
5346	NullRegClasses,	5346	NullRegClasses,
5347	FGR64GetRawAllocationOrder	5347	FGR64GetRawAllocationOrder
5348	};	5348	};
5349		5349
5350	extern const TargetRegisterClass GPR64RegClass = {	5350	extern const TargetRegisterClass GPR64RegClass = {
5351	&MipsMCRegisterClasses[GPR64RegClassID],	5351	&MipsMCRegisterClasses[GPR64RegClassID],
5352	GPR64SubClassMask,	5352	GPR64SubClassMask,
5353	SuperRegIdxSeqs + 1,	5353	SuperRegIdxSeqs + 1,
5354	LaneBitmask(0x0000000000000001),	5354	LaneBitmask(0x0000000000000001),
5355	0,	5355	0,
5356	false,	5356	false,
5357	0x00, /* TSFlags */	5357	0x00, /* TSFlags */
5358	false, /* HasDisjunctSubRegs */	5358	false, /* HasDisjunctSubRegs */
5359	false, /* CoveredBySubRegs */	5359	false, /* CoveredBySubRegs */
5360	NullRegClasses,	5360	NullRegClasses,
5361	nullptr	5361	nullptr
5362	};	5362	};
5363		5363
5364	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {	5364	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5365	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],	5365	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
5366	GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,	5366	GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
5367	SuperRegIdxSeqs + 1,	5367	SuperRegIdxSeqs + 1,
5368	LaneBitmask(0x0000000000000001),	5368	LaneBitmask(0x0000000000000001),
5369	0,	5369	0,
5370	false,	5370	false,
5371	0x00, /* TSFlags */	5371	0x00, /* TSFlags */
5372	false, /* HasDisjunctSubRegs */	5372	false, /* HasDisjunctSubRegs */
5373	false, /* CoveredBySubRegs */	5373	false, /* CoveredBySubRegs */
5374	GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,	5374	GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
5375	nullptr	5375	nullptr
5376	};	5376	};
5377		5377
5378	extern const TargetRegisterClass AFGR64RegClass = {	5378	extern const TargetRegisterClass AFGR64RegClass = {
5379	&MipsMCRegisterClasses[AFGR64RegClassID],	5379	&MipsMCRegisterClasses[AFGR64RegClassID],
5380	AFGR64SubClassMask,	5380	AFGR64SubClassMask,
5381	SuperRegIdxSeqs + 1,	5381	SuperRegIdxSeqs + 1,
5382	LaneBitmask(0x0000000000000041),	5382	LaneBitmask(0x0000000000000041),
5383	0,	5383	0,
5384	false,	5384	false,
5385	0x00, /* TSFlags */	5385	0x00, /* TSFlags */
5386	true, /* HasDisjunctSubRegs */	5386	true, /* HasDisjunctSubRegs */
5387	true, /* CoveredBySubRegs */	5387	true, /* CoveredBySubRegs */
5388	NullRegClasses,	5388	NullRegClasses,
5389	nullptr	5389	nullptr
5390	};	5390	};
5391		5391
5392	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {	5392	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5393	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],	5393	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
5394	GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,	5394	GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
5395	SuperRegIdxSeqs + 1,	5395	SuperRegIdxSeqs + 1,
5396	LaneBitmask(0x0000000000000001),	5396	LaneBitmask(0x0000000000000001),
5397	0,	5397	0,
5398	false,	5398	false,
5399	0x00, /* TSFlags */	5399	0x00, /* TSFlags */
5400	false, /* HasDisjunctSubRegs */	5400	false, /* HasDisjunctSubRegs */
5401	false, /* CoveredBySubRegs */	5401	false, /* CoveredBySubRegs */
5402	GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,	5402	GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
5403	nullptr	5403	nullptr
5404	};	5404	};
5405		5405
5406	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {	5406	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5407	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],	5407	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
5408	GPR64_with_sub_32_in_CPU16RegsSubClassMask,	5408	GPR64_with_sub_32_in_CPU16RegsSubClassMask,
5409	SuperRegIdxSeqs + 1,	5409	SuperRegIdxSeqs + 1,
5410	LaneBitmask(0x0000000000000001),	5410	LaneBitmask(0x0000000000000001),
5411	0,	5411	0,
5412	false,	5412	false,
5413	0x00, /* TSFlags */	5413	0x00, /* TSFlags */
5414	false, /* HasDisjunctSubRegs */	5414	false, /* HasDisjunctSubRegs */
5415	false, /* CoveredBySubRegs */	5415	false, /* CoveredBySubRegs */
5416	GPR64_with_sub_32_in_CPU16RegsSuperclasses,	5416	GPR64_with_sub_32_in_CPU16RegsSuperclasses,
5417	nullptr	5417	nullptr
5418	};	5418	};
5419		5419
5420	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {	5420	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5421	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],	5421	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
5422	GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,	5422	GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
5423	SuperRegIdxSeqs + 1,	5423	SuperRegIdxSeqs + 1,
5424	LaneBitmask(0x0000000000000001),	5424	LaneBitmask(0x0000000000000001),
5425	0,	5425	0,
5426	false,	5426	false,
5427	0x00, /* TSFlags */	5427	0x00, /* TSFlags */
5428	false, /* HasDisjunctSubRegs */	5428	false, /* HasDisjunctSubRegs */
5429	false, /* CoveredBySubRegs */	5429	false, /* CoveredBySubRegs */
5430	GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,	5430	GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
5431	nullptr	5431	nullptr
5432	};	5432	};
5433		5433
5434	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {	5434	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5435	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],	5435	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
5436	GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,	5436	GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
5437	SuperRegIdxSeqs + 1,	5437	SuperRegIdxSeqs + 1,
5438	LaneBitmask(0x0000000000000001),	5438	LaneBitmask(0x0000000000000001),
5439	0,	5439	0,
5440	false,	5440	false,
5441	0x00, /* TSFlags */	5441	0x00, /* TSFlags */
5442	false, /* HasDisjunctSubRegs */	5442	false, /* HasDisjunctSubRegs */
5443	false, /* CoveredBySubRegs */	5443	false, /* CoveredBySubRegs */
5444	GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,	5444	GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
5445	nullptr	5445	nullptr
5446	};	5446	};
5447		5447
5448	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {	5448	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5449	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],	5449	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
5450	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,	5450	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5451	SuperRegIdxSeqs + 1,	5451	SuperRegIdxSeqs + 1,
5452	LaneBitmask(0x0000000000000001),	5452	LaneBitmask(0x0000000000000001),
5453	0,	5453	0,
5454	false,	5454	false,
5455	0x00, /* TSFlags */	5455	0x00, /* TSFlags */
5456	false, /* HasDisjunctSubRegs */	5456	false, /* HasDisjunctSubRegs */
5457	false, /* CoveredBySubRegs */	5457	false, /* CoveredBySubRegs */
5458	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,	5458	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5459	nullptr	5459	nullptr
5460	};	5460	};
5461		5461
5462	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {	5462	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5463	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],	5463	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
5464	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,	5464	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
5465	SuperRegIdxSeqs + 1,	5465	SuperRegIdxSeqs + 1,
5466	LaneBitmask(0x0000000000000001),	5466	LaneBitmask(0x0000000000000001),
5467	0,	5467	0,
5468	false,	5468	false,
5469	0x00, /* TSFlags */	5469	0x00, /* TSFlags */
5470	false, /* HasDisjunctSubRegs */	5470	false, /* HasDisjunctSubRegs */
5471	false, /* CoveredBySubRegs */	5471	false, /* CoveredBySubRegs */
5472	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,	5472	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
5473	nullptr	5473	nullptr
5474	};	5474	};
5475		5475
5476	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {	5476	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5477	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],	5477	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
5478	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,	5478	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
5479	SuperRegIdxSeqs + 1,	5479	SuperRegIdxSeqs + 1,
5480	LaneBitmask(0x0000000000000001),	5480	LaneBitmask(0x0000000000000001),
5481	0,	5481	0,
5482	false,	5482	false,
5483	0x00, /* TSFlags */	5483	0x00, /* TSFlags */
5484	false, /* HasDisjunctSubRegs */	5484	false, /* HasDisjunctSubRegs */
5485	false, /* CoveredBySubRegs */	5485	false, /* CoveredBySubRegs */
5486	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,	5486	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,
5487	nullptr	5487	nullptr
5488	};	5488	};
5489		5489
5490	extern const TargetRegisterClass ACC64DSPRegClass = {	5490	extern const TargetRegisterClass ACC64DSPRegClass = {
5491	&MipsMCRegisterClasses[ACC64DSPRegClassID],	5491	&MipsMCRegisterClasses[ACC64DSPRegClassID],
5492	ACC64DSPSubClassMask,	5492	ACC64DSPSubClassMask,
5493	SuperRegIdxSeqs + 16,	5493	SuperRegIdxSeqs + 16,
5494	LaneBitmask(0x0000000000000041),	5494	LaneBitmask(0x0000000000000041),
5495	0,	5495	0,
5496	false,	5496	false,
5497	0x00, /* TSFlags */	5497	0x00, /* TSFlags */
5498	true, /* HasDisjunctSubRegs */	5498	true, /* HasDisjunctSubRegs */
5499	true, /* CoveredBySubRegs */	5499	true, /* CoveredBySubRegs */
5500	NullRegClasses,	5500	NullRegClasses,
5501	nullptr	5501	nullptr
5502	};	5502	};
5503		5503
5504	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {	5504	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5505	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],	5505	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
5506	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,	5506	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
5507	SuperRegIdxSeqs + 1,	5507	SuperRegIdxSeqs + 1,
5508	LaneBitmask(0x0000000000000001),	5508	LaneBitmask(0x0000000000000001),
5509	0,	5509	0,
5510	false,	5510	false,
5511	0x00, /* TSFlags */	5511	0x00, /* TSFlags */
5512	false, /* HasDisjunctSubRegs */	5512	false, /* HasDisjunctSubRegs */
5513	false, /* CoveredBySubRegs */	5513	false, /* CoveredBySubRegs */
5514	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,	5514	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
5515	nullptr	5515	nullptr
5516	};	5516	};
5517		5517
5518	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	5518	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5519	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	5519	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
5520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	5520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
5521	SuperRegIdxSeqs + 1,	5521	SuperRegIdxSeqs + 1,
5522	LaneBitmask(0x0000000000000001),	5522	LaneBitmask(0x0000000000000001),
5523	0,	5523	0,
5524	false,	5524	false,
5525	0x00, /* TSFlags */	5525	0x00, /* TSFlags */
5526	false, /* HasDisjunctSubRegs */	5526	false, /* HasDisjunctSubRegs */
5527	false, /* CoveredBySubRegs */	5527	false, /* CoveredBySubRegs */
5528	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	5528	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
5529	nullptr	5529	nullptr
5530	};	5530	};
5531		5531
5532	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	5532	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5533	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	5533	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
5534	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	5534	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
5535	SuperRegIdxSeqs + 1,	5535	SuperRegIdxSeqs + 1,
5536	LaneBitmask(0x0000000000000001),	5536	LaneBitmask(0x0000000000000001),
5537	0,	5537	0,
5538	false,	5538	false,
5539	0x00, /* TSFlags */	5539	0x00, /* TSFlags */
5540	false, /* HasDisjunctSubRegs */	5540	false, /* HasDisjunctSubRegs */
5541	false, /* CoveredBySubRegs */	5541	false, /* CoveredBySubRegs */
5542	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	5542	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
5543	nullptr	5543	nullptr
5544	};	5544	};
5545		5545
5546	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {	5546	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5547	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],	5547	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
5548	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,	5548	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
5549	SuperRegIdxSeqs + 1,	5549	SuperRegIdxSeqs + 1,
5550	LaneBitmask(0x0000000000000001),	5550	LaneBitmask(0x0000000000000001),
5551	0,	5551	0,
5552	false,	5552	false,
5553	0x00, /* TSFlags */	5553	0x00, /* TSFlags */
5554	false, /* HasDisjunctSubRegs */	5554	false, /* HasDisjunctSubRegs */
5555	false, /* CoveredBySubRegs */	5555	false, /* CoveredBySubRegs */
5556	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,	5556	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,
5557	nullptr	5557	nullptr
5558	};	5558	};
5559		5559
5560	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	5560	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5561	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	5561	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
5562	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	5562	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
5563	SuperRegIdxSeqs + 1,	5563	SuperRegIdxSeqs + 1,
5564	LaneBitmask(0x0000000000000001),	5564	LaneBitmask(0x0000000000000001),
5565	0,	5565	0,
5566	false,	5566	false,
5567	0x00, /* TSFlags */	5567	0x00, /* TSFlags */
5568	false, /* HasDisjunctSubRegs */	5568	false, /* HasDisjunctSubRegs */
5569	false, /* CoveredBySubRegs */	5569	false, /* CoveredBySubRegs */
5570	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	5570	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
5571	nullptr	5571	nullptr
5572	};	5572	};
5573		5573
5574	extern const TargetRegisterClass OCTEON_MPLRegClass = {	5574	extern const TargetRegisterClass OCTEON_MPLRegClass = {
5575	&MipsMCRegisterClasses[OCTEON_MPLRegClassID],	5575	&MipsMCRegisterClasses[OCTEON_MPLRegClassID],
5576	OCTEON_MPLSubClassMask,	5576	OCTEON_MPLSubClassMask,
5577	SuperRegIdxSeqs + 1,	5577	SuperRegIdxSeqs + 1,
5578	LaneBitmask(0x0000000000000001),	5578	LaneBitmask(0x0000000000000001),
5579	0,	5579	0,
5580	false,	5580	false,
5581	0x00, /* TSFlags */	5581	0x00, /* TSFlags */
5582	false, /* HasDisjunctSubRegs */	5582	false, /* HasDisjunctSubRegs */
5583	false, /* CoveredBySubRegs */	5583	false, /* CoveredBySubRegs */
5584	NullRegClasses,	5584	NullRegClasses,
5585	nullptr	5585	nullptr
5586	};	5586	};
5587		5587
5588	extern const TargetRegisterClass OCTEON_PRegClass = {	5588	extern const TargetRegisterClass OCTEON_PRegClass = {
5589	&MipsMCRegisterClasses[OCTEON_PRegClassID],	5589	&MipsMCRegisterClasses[OCTEON_PRegClassID],
5590	OCTEON_PSubClassMask,	5590	OCTEON_PSubClassMask,
5591	SuperRegIdxSeqs + 1,	5591	SuperRegIdxSeqs + 1,
5592	LaneBitmask(0x0000000000000001),	5592	LaneBitmask(0x0000000000000001),
5593	0,	5593	0,
5594	false,	5594	false,
5595	0x00, /* TSFlags */	5595	0x00, /* TSFlags */
5596	false, /* HasDisjunctSubRegs */	5596	false, /* HasDisjunctSubRegs */
5597	false, /* CoveredBySubRegs */	5597	false, /* CoveredBySubRegs */
5598	NullRegClasses,	5598	NullRegClasses,
5599	nullptr	5599	nullptr
5600	};	5600	};
5601		5601
5602	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	5602	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5603	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	5603	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
5604	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	5604	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
5605	SuperRegIdxSeqs + 1,	5605	SuperRegIdxSeqs + 1,
5606	LaneBitmask(0x0000000000000001),	5606	LaneBitmask(0x0000000000000001),
5607	0,	5607	0,
5608	false,	5608	false,
5609	0x00, /* TSFlags */	5609	0x00, /* TSFlags */
5610	false, /* HasDisjunctSubRegs */	5610	false, /* HasDisjunctSubRegs */
5611	false, /* CoveredBySubRegs */	5611	false, /* CoveredBySubRegs */
5612	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	5612	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
5613	nullptr	5613	nullptr
5614	};	5614	};
5615		5615
5616	extern const TargetRegisterClass ACC64RegClass = {	5616	extern const TargetRegisterClass ACC64RegClass = {
5617	&MipsMCRegisterClasses[ACC64RegClassID],	5617	&MipsMCRegisterClasses[ACC64RegClassID],
5618	ACC64SubClassMask,	5618	ACC64SubClassMask,
5619	SuperRegIdxSeqs + 16,	5619	SuperRegIdxSeqs + 16,
5620	LaneBitmask(0x0000000000000041),	5620	LaneBitmask(0x0000000000000041),
5621	0,	5621	0,
5622	false,	5622	false,
5623	0x00, /* TSFlags */	5623	0x00, /* TSFlags */
5624	true, /* HasDisjunctSubRegs */	5624	true, /* HasDisjunctSubRegs */
5625	true, /* CoveredBySubRegs */	5625	true, /* CoveredBySubRegs */
5626	ACC64Superclasses,	5626	ACC64Superclasses,
5627	nullptr	5627	nullptr
5628	};	5628	};
5629		5629
5630	extern const TargetRegisterClass GP64RegClass = {	5630	extern const TargetRegisterClass GP64RegClass = {
5631	&MipsMCRegisterClasses[GP64RegClassID],	5631	&MipsMCRegisterClasses[GP64RegClassID],
5632	GP64SubClassMask,	5632	GP64SubClassMask,
5633	SuperRegIdxSeqs + 1,	5633	SuperRegIdxSeqs + 1,
5634	LaneBitmask(0x0000000000000001),	5634	LaneBitmask(0x0000000000000001),
5635	0,	5635	0,
5636	false,	5636	false,
5637	0x00, /* TSFlags */	5637	0x00, /* TSFlags */
5638	false, /* HasDisjunctSubRegs */	5638	false, /* HasDisjunctSubRegs */
5639	false, /* CoveredBySubRegs */	5639	false, /* CoveredBySubRegs */
5640	GP64Superclasses,	5640	GP64Superclasses,
5641	nullptr	5641	nullptr
5642	};	5642	};
5643		5643
5644	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {	5644	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5645	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],	5645	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
5646	GPR64_with_sub_32_in_CPURARegSubClassMask,	5646	GPR64_with_sub_32_in_CPURARegSubClassMask,
5647	SuperRegIdxSeqs + 1,	5647	SuperRegIdxSeqs + 1,
5648	LaneBitmask(0x0000000000000001),	5648	LaneBitmask(0x0000000000000001),
5649	0,	5649	0,
5650	false,	5650	false,
5651	0x00, /* TSFlags */	5651	0x00, /* TSFlags */
5652	false, /* HasDisjunctSubRegs */	5652	false, /* HasDisjunctSubRegs */
5653	false, /* CoveredBySubRegs */	5653	false, /* CoveredBySubRegs */
5654	GPR64_with_sub_32_in_CPURARegSuperclasses,	5654	GPR64_with_sub_32_in_CPURARegSuperclasses,
5655	nullptr	5655	nullptr
5656	};	5656	};
5657		5657
5658	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {	5658	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5659	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],	5659	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
5660	GPR64_with_sub_32_in_GPR32ZEROSubClassMask,	5660	GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
5661	SuperRegIdxSeqs + 1,	5661	SuperRegIdxSeqs + 1,
5662	LaneBitmask(0x0000000000000001),	5662	LaneBitmask(0x0000000000000001),
5663	0,	5663	0,
5664	false,	5664	false,
5665	0x00, /* TSFlags */	5665	0x00, /* TSFlags */
5666	false, /* HasDisjunctSubRegs */	5666	false, /* HasDisjunctSubRegs */
5667	false, /* CoveredBySubRegs */	5667	false, /* CoveredBySubRegs */
5668	GPR64_with_sub_32_in_GPR32ZEROSuperclasses,	5668	GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
5669	nullptr	5669	nullptr
5670	};	5670	};
5671		5671
5672	extern const TargetRegisterClass HI64RegClass = {	5672	extern const TargetRegisterClass HI64RegClass = {
5673	&MipsMCRegisterClasses[HI64RegClassID],	5673	&MipsMCRegisterClasses[HI64RegClassID],
5674	HI64SubClassMask,	5674	HI64SubClassMask,
5675	SuperRegIdxSeqs + 4,	5675	SuperRegIdxSeqs + 4,
5676	LaneBitmask(0x0000000000000001),	5676	LaneBitmask(0x0000000000000001),
5677	0,	5677	0,
5678	false,	5678	false,
5679	0x00, /* TSFlags */	5679	0x00, /* TSFlags */
5680	false, /* HasDisjunctSubRegs */	5680	false, /* HasDisjunctSubRegs */
5681	false, /* CoveredBySubRegs */	5681	false, /* CoveredBySubRegs */
5682	NullRegClasses,	5682	NullRegClasses,
5683	nullptr	5683	nullptr
5684	};	5684	};
5685		5685
5686	extern const TargetRegisterClass LO64RegClass = {	5686	extern const TargetRegisterClass LO64RegClass = {
5687	&MipsMCRegisterClasses[LO64RegClassID],	5687	&MipsMCRegisterClasses[LO64RegClassID],
5688	LO64SubClassMask,	5688	LO64SubClassMask,
5689	SuperRegIdxSeqs + 7,	5689	SuperRegIdxSeqs + 7,
5690	LaneBitmask(0x0000000000000001),	5690	LaneBitmask(0x0000000000000001),
5691	0,	5691	0,
5692	false,	5692	false,
5693	0x00, /* TSFlags */	5693	0x00, /* TSFlags */
5694	false, /* HasDisjunctSubRegs */	5694	false, /* HasDisjunctSubRegs */
5695	false, /* CoveredBySubRegs */	5695	false, /* CoveredBySubRegs */
5696	NullRegClasses,	5696	NullRegClasses,
5697	nullptr	5697	nullptr
5698	};	5698	};
5699		5699
5700	extern const TargetRegisterClass SP64RegClass = {	5700	extern const TargetRegisterClass SP64RegClass = {
5701	&MipsMCRegisterClasses[SP64RegClassID],	5701	&MipsMCRegisterClasses[SP64RegClassID],
5702	SP64SubClassMask,	5702	SP64SubClassMask,
5703	SuperRegIdxSeqs + 1,	5703	SuperRegIdxSeqs + 1,
5704	LaneBitmask(0x0000000000000001),	5704	LaneBitmask(0x0000000000000001),
5705	0,	5705	0,
5706	false,	5706	false,
5707	0x00, /* TSFlags */	5707	0x00, /* TSFlags */
5708	false, /* HasDisjunctSubRegs */	5708	false, /* HasDisjunctSubRegs */
5709	false, /* CoveredBySubRegs */	5709	false, /* CoveredBySubRegs */
5710	SP64Superclasses,	5710	SP64Superclasses,
5711	nullptr	5711	nullptr
5712	};	5712	};
5713		5713
5714	extern const TargetRegisterClass MSA128BRegClass = {	5714	extern const TargetRegisterClass MSA128BRegClass = {
5715	&MipsMCRegisterClasses[MSA128BRegClassID],	5715	&MipsMCRegisterClasses[MSA128BRegClassID],
5716	MSA128BSubClassMask,	5716	MSA128BSubClassMask,
5717	SuperRegIdxSeqs + 1,	5717	SuperRegIdxSeqs + 1,
5718	LaneBitmask(0x0000000000000041),	5718	LaneBitmask(0x0000000000000041),
5719	0,	5719	0,
5720	false,	5720	false,
5721	0x00, /* TSFlags */	5721	0x00, /* TSFlags */
5722	true, /* HasDisjunctSubRegs */	5722	true, /* HasDisjunctSubRegs */
5723	false, /* CoveredBySubRegs */	5723	false, /* CoveredBySubRegs */
5724	MSA128BSuperclasses,	5724	MSA128BSuperclasses,
5725	nullptr	5725	nullptr
5726	};	5726	};
5727		5727
5728	extern const TargetRegisterClass MSA128DRegClass = {	5728	extern const TargetRegisterClass MSA128DRegClass = {
5729	&MipsMCRegisterClasses[MSA128DRegClassID],	5729	&MipsMCRegisterClasses[MSA128DRegClassID],
5730	MSA128DSubClassMask,	5730	MSA128DSubClassMask,
5731	SuperRegIdxSeqs + 1,	5731	SuperRegIdxSeqs + 1,
5732	LaneBitmask(0x0000000000000041),	5732	LaneBitmask(0x0000000000000041),
5733	0,	5733	0,
5734	false,	5734	false,
5735	0x00, /* TSFlags */	5735	0x00, /* TSFlags */
5736	true, /* HasDisjunctSubRegs */	5736	true, /* HasDisjunctSubRegs */
5737	false, /* CoveredBySubRegs */	5737	false, /* CoveredBySubRegs */
5738	MSA128DSuperclasses,	5738	MSA128DSuperclasses,
5739	nullptr	5739	nullptr
5740	};	5740	};
5741		5741
5742	extern const TargetRegisterClass MSA128HRegClass = {	5742	extern const TargetRegisterClass MSA128HRegClass = {
5743	&MipsMCRegisterClasses[MSA128HRegClassID],	5743	&MipsMCRegisterClasses[MSA128HRegClassID],
5744	MSA128HSubClassMask,	5744	MSA128HSubClassMask,
5745	SuperRegIdxSeqs + 1,	5745	SuperRegIdxSeqs + 1,
5746	LaneBitmask(0x0000000000000041),	5746	LaneBitmask(0x0000000000000041),
5747	0,	5747	0,
5748	false,	5748	false,
5749	0x00, /* TSFlags */	5749	0x00, /* TSFlags */
5750	true, /* HasDisjunctSubRegs */	5750	true, /* HasDisjunctSubRegs */
5751	false, /* CoveredBySubRegs */	5751	false, /* CoveredBySubRegs */
5752	MSA128HSuperclasses,	5752	MSA128HSuperclasses,
5753	nullptr	5753	nullptr
5754	};	5754	};
5755		5755
5756	extern const TargetRegisterClass MSA128WRegClass = {	5756	extern const TargetRegisterClass MSA128WRegClass = {
5757	&MipsMCRegisterClasses[MSA128WRegClassID],	5757	&MipsMCRegisterClasses[MSA128WRegClassID],
5758	MSA128WSubClassMask,	5758	MSA128WSubClassMask,
5759	SuperRegIdxSeqs + 1,	5759	SuperRegIdxSeqs + 1,
5760	LaneBitmask(0x0000000000000041),	5760	LaneBitmask(0x0000000000000041),
5761	0,	5761	0,
5762	false,	5762	false,
5763	0x00, /* TSFlags */	5763	0x00, /* TSFlags */
5764	true, /* HasDisjunctSubRegs */	5764	true, /* HasDisjunctSubRegs */
5765	false, /* CoveredBySubRegs */	5765	false, /* CoveredBySubRegs */
5766	MSA128WSuperclasses,	5766	MSA128WSuperclasses,
5767	nullptr	5767	nullptr
5768	};	5768	};
5769		5769
5770	extern const TargetRegisterClass MSA128WEvensRegClass = {	5770	extern const TargetRegisterClass MSA128WEvensRegClass = {
5771	&MipsMCRegisterClasses[MSA128WEvensRegClassID],	5771	&MipsMCRegisterClasses[MSA128WEvensRegClassID],
5772	MSA128WEvensSubClassMask,	5772	MSA128WEvensSubClassMask,
5773	SuperRegIdxSeqs + 1,	5773	SuperRegIdxSeqs + 1,
5774	LaneBitmask(0x0000000000000041),	5774	LaneBitmask(0x0000000000000041),
5775	0,	5775	0,
5776	false,	5776	false,
5777	0x00, /* TSFlags */	5777	0x00, /* TSFlags */
5778	true, /* HasDisjunctSubRegs */	5778	true, /* HasDisjunctSubRegs */
5779	false, /* CoveredBySubRegs */	5779	false, /* CoveredBySubRegs */
5780	MSA128WEvensSuperclasses,	5780	MSA128WEvensSuperclasses,
5781	nullptr	5781	nullptr
5782	};	5782	};
5783		5783
5784	extern const TargetRegisterClass ACC128RegClass = {	5784	extern const TargetRegisterClass ACC128RegClass = {
5785	&MipsMCRegisterClasses[ACC128RegClassID],	5785	&MipsMCRegisterClasses[ACC128RegClassID],
5786	ACC128SubClassMask,	5786	ACC128SubClassMask,
5787	SuperRegIdxSeqs + 1,	5787	SuperRegIdxSeqs + 1,
5788	LaneBitmask(0x0000000000000041),	5788	LaneBitmask(0x0000000000000041),
5789	0,	5789	0,
5790	false,	5790	false,
5791	0x00, /* TSFlags */	5791	0x00, /* TSFlags */
5792	true, /* HasDisjunctSubRegs */	5792	true, /* HasDisjunctSubRegs */
5793	true, /* CoveredBySubRegs */	5793	true, /* CoveredBySubRegs */
5794	NullRegClasses,	5794	NullRegClasses,
5795	nullptr	5795	nullptr
5796	};	5796	};
5797		5797
5798	} // end namespace Mips	5798	} // end namespace Mips
5799		5799
5800	namespace {	5800	namespace {
5801	const TargetRegisterClass *const RegisterClasses[] = {	5801	const TargetRegisterClass *const RegisterClasses[] = {
5802	&Mips::MSA128F16RegClass,	5802	&Mips::MSA128F16RegClass,
5803	&Mips::CCRRegClass,	5803	&Mips::CCRRegClass,
5804	&Mips::COP0RegClass,	5804	&Mips::COP0RegClass,
5805	&Mips::COP2RegClass,	5805	&Mips::COP2RegClass,
5806	&Mips::COP3RegClass,	5806	&Mips::COP3RegClass,
5807	&Mips::DSPRRegClass,	5807	&Mips::DSPRRegClass,
5808	&Mips::FGR32RegClass,	5808	&Mips::FGR32RegClass,
5809	&Mips::FGRCCRegClass,	5809	&Mips::FGRCCRegClass,
5810	&Mips::GPR32RegClass,	5810	&Mips::GPR32RegClass,
5811	&Mips::HWRegsRegClass,	5811	&Mips::HWRegsRegClass,
5812	&Mips::MSACtrlRegClass,	5812	&Mips::MSACtrlRegClass,
5813	&Mips::GPR32NONZERORegClass,	5813	&Mips::GPR32NONZERORegClass,
5814	&Mips::CPU16RegsPlusSPRegClass,	5814	&Mips::CPU16RegsPlusSPRegClass,
5815	&Mips::CPU16RegsRegClass,	5815	&Mips::CPU16RegsRegClass,
5816	&Mips::FCCRegClass,	5816	&Mips::FCCRegClass,
5817	&Mips::GPRMM16RegClass,	5817	&Mips::GPRMM16RegClass,
5818	&Mips::GPRMM16MovePRegClass,	5818	&Mips::GPRMM16MovePRegClass,
5819	&Mips::GPRMM16ZeroRegClass,	5819	&Mips::GPRMM16ZeroRegClass,
5820	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	5820	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
5821	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	5821	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
5822	&Mips::GPRMM16MovePPairSecondRegClass,	5822	&Mips::GPRMM16MovePPairSecondRegClass,
5823	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	5823	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,
5824	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	5824	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5825	&Mips::HI32DSPRegClass,	5825	&Mips::HI32DSPRegClass,
5826	&Mips::LO32DSPRegClass,	5826	&Mips::LO32DSPRegClass,
5827	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	5827	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5828	&Mips::GPRMM16MovePPairFirstRegClass,	5828	&Mips::GPRMM16MovePPairFirstRegClass,
5829	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	5829	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5830	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	5830	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5831	&Mips::CPURARegRegClass,	5831	&Mips::CPURARegRegClass,
5832	&Mips::CPUSPRegRegClass,	5832	&Mips::CPUSPRegRegClass,
5833	&Mips::DSPCCRegClass,	5833	&Mips::DSPCCRegClass,
5834	&Mips::GP32RegClass,	5834	&Mips::GP32RegClass,
5835	&Mips::GPR32ZERORegClass,	5835	&Mips::GPR32ZERORegClass,
5836	&Mips::HI32RegClass,	5836	&Mips::HI32RegClass,
5837	&Mips::LO32RegClass,	5837	&Mips::LO32RegClass,
5838	&Mips::SP32RegClass,	5838	&Mips::SP32RegClass,
5839	&Mips::FGR64RegClass,	5839	&Mips::FGR64RegClass,
5840	&Mips::GPR64RegClass,	5840	&Mips::GPR64RegClass,
5841	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	5841	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
5842	&Mips::AFGR64RegClass,	5842	&Mips::AFGR64RegClass,
5843	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	5843	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
5844	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	5844	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
5845	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	5845	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
5846	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	5846	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
5847	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	5847	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
5848	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	5848	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
5849	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	5849	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
5850	&Mips::ACC64DSPRegClass,	5850	&Mips::ACC64DSPRegClass,
5851	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	5851	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
5852	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	5852	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
5853	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	5853	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
5854	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	5854	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
5855	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	5855	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
5856	&Mips::OCTEON_MPLRegClass,	5856	&Mips::OCTEON_MPLRegClass,
5857	&Mips::OCTEON_PRegClass,	5857	&Mips::OCTEON_PRegClass,
5858	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	5858	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
5859	&Mips::ACC64RegClass,	5859	&Mips::ACC64RegClass,
5860	&Mips::GP64RegClass,	5860	&Mips::GP64RegClass,
5861	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,	5861	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,
5862	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,	5862	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
5863	&Mips::HI64RegClass,	5863	&Mips::HI64RegClass,
5864	&Mips::LO64RegClass,	5864	&Mips::LO64RegClass,
5865	&Mips::SP64RegClass,	5865	&Mips::SP64RegClass,
5866	&Mips::MSA128BRegClass,	5866	&Mips::MSA128BRegClass,
5867	&Mips::MSA128DRegClass,	5867	&Mips::MSA128DRegClass,
5868	&Mips::MSA128HRegClass,	5868	&Mips::MSA128HRegClass,
5869	&Mips::MSA128WRegClass,	5869	&Mips::MSA128WRegClass,
5870	&Mips::MSA128WEvensRegClass,	5870	&Mips::MSA128WEvensRegClass,
5871	&Mips::ACC128RegClass,	5871	&Mips::ACC128RegClass,
5872	};	5872	};
5873	} // end anonymous namespace	5873	} // end anonymous namespace
5874		5874
5875	static const uint8_t CostPerUseTable[] = {	5875	static const uint8_t CostPerUseTable[] = {
5876	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };	5876	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
5877		5877
5878		5878
5879	static const bool InAllocatableClassTable[] = {	5879	static const bool InAllocatableClassTable[] = {
5880	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };	5880	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
5881		5881
5882		5882
5883	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors	5883	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
5884	CostPerUseTable, 1, InAllocatableClassTable};	5884	CostPerUseTable, 1, InAllocatableClassTable};
5885		5885
5886	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {	5886	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
5887	static const uint8_t RowMap[11] = {	5887	static const uint8_t RowMap[11] = {
5888	0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,	5888	0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
5889	};	5889	};
5890	static const uint8_t Rows[2][11] = {	5890	static const uint8_t Rows[2][11] = {
5891	{ Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },	5891	{ Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
5892	{ Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },	5892	{ Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
5893	};	5893	};
5894		5894
5895	--IdxA; assert(IdxA < 11); (void) IdxA;	5895	--IdxA; assert(IdxA < 11); (void) IdxA;
5896	--IdxB; assert(IdxB < 11);	5896	--IdxB; assert(IdxB < 11);
5897	return Rows[RowMap[IdxA]][IdxB];	5897	return Rows[RowMap[IdxA]][IdxB];
5898	}	5898	}
5899		5899
5900	struct MaskRolOp {	5900	struct MaskRolOp {
5901	LaneBitmask Mask;	5901	LaneBitmask Mask;
5902	uint8_t RotateLeft;	5902	uint8_t RotateLeft;
5903	};	5903	};
5904	static const MaskRolOp LaneMaskComposeSequences[] = {	5904	static const MaskRolOp LaneMaskComposeSequences[] = {
5905	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0	5905	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
5906	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2	5906	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
5907	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4	5907	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
5908	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6	5908	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
5909	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8	5909	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
5910	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10	5910	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
5911	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12	5911	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
5912	};	5912	};
5913	static const uint8_t CompositeSequences[] = {	5913	static const uint8_t CompositeSequences[] = {
5914	0, // to sub_32	5914	0, // to sub_32
5915	0, // to sub_64	5915	0, // to sub_64
5916	2, // to sub_dsp16_19	5916	2, // to sub_dsp16_19
5917	4, // to sub_dsp20	5917	4, // to sub_dsp20
5918	6, // to sub_dsp21	5918	6, // to sub_dsp21
5919	8, // to sub_dsp22	5919	8, // to sub_dsp22
5920	10, // to sub_dsp23	5920	10, // to sub_dsp23
5921	12, // to sub_hi	5921	12, // to sub_hi
5922	0, // to sub_lo	5922	0, // to sub_lo
5923	12, // to sub_hi_then_sub_32	5923	12, // to sub_hi_then_sub_32
5924	0 // to sub_32_sub_hi_then_sub_32	5924	0 // to sub_32_sub_hi_then_sub_32
5925	};	5925	};
5926		5926
5927	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	5927	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5928	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	5928	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5929	LaneBitmask Result;	5929	LaneBitmask Result;
5930	for (const MaskRolOp *Ops =	5930	for (const MaskRolOp *Ops =
5931	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	5931	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
5932	Ops->Mask.any(); ++Ops) {	5932	Ops->Mask.any(); ++Ops) {
5933	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();	5933	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
5934	if (unsigned S = Ops->RotateLeft)	5934	if (unsigned S = Ops->RotateLeft)
5935	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));	5935	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));
5936	else	5936	else
5937	Result \|= LaneBitmask(M);	5937	Result \|= LaneBitmask(M);
5938	}	5938	}
5939	return Result;	5939	return Result;
5940	}	5940	}
5941		5941
5942	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	5942	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
5943	LaneMask &= getSubRegIndexLaneMask(IdxA);	5943	LaneMask &= getSubRegIndexLaneMask(IdxA);
5944	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	5944	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
5945	LaneBitmask Result;	5945	LaneBitmask Result;
5946	for (const MaskRolOp *Ops =	5946	for (const MaskRolOp *Ops =
5947	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	5947	&LaneMaskComposeSequences[CompositeSequences[IdxA]];
5948	Ops->Mask.any(); ++Ops) {	5948	Ops->Mask.any(); ++Ops) {
5949	LaneBitmask::Type M = LaneMask.getAsInteger();	5949	LaneBitmask::Type M = LaneMask.getAsInteger();
5950	if (unsigned S = Ops->RotateLeft)	5950	if (unsigned S = Ops->RotateLeft)
5951	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));	5951	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));
5952	else	5952	else
5953	Result \|= LaneBitmask(M);	5953	Result \|= LaneBitmask(M);
5954	}	5954	}
5955	return Result;	5955	return Result;
5956	}	5956	}
5957		5957
5958	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {	5958	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {
5959	static const uint8_t Table[70][11] = {	5959	static const uint8_t Table[70][11] = {
5960	{ // MSA128F16	5960	{ // MSA128F16
5961	0, // sub_32	5961	0, // sub_32
5962	1, // sub_64 -> MSA128F16	5962	1, // sub_64 -> MSA128F16
5963	0, // sub_dsp16_19	5963	0, // sub_dsp16_19
5964	0, // sub_dsp20	5964	0, // sub_dsp20
5965	0, // sub_dsp21	5965	0, // sub_dsp21
5966	0, // sub_dsp22	5966	0, // sub_dsp22
5967	0, // sub_dsp23	5967	0, // sub_dsp23
5968	1, // sub_hi -> MSA128F16	5968	1, // sub_hi -> MSA128F16
5969	1, // sub_lo -> MSA128F16	5969	1, // sub_lo -> MSA128F16
5970	0, // sub_hi_then_sub_32	5970	0, // sub_hi_then_sub_32
5971	0, // sub_32_sub_hi_then_sub_32	5971	0, // sub_32_sub_hi_then_sub_32
5972	},	5972	},
5973	{ // CCR	5973	{ // CCR
5974	0, // sub_32	5974	0, // sub_32
5975	0, // sub_64	5975	0, // sub_64
5976	0, // sub_dsp16_19	5976	0, // sub_dsp16_19
5977	0, // sub_dsp20	5977	0, // sub_dsp20
5978	0, // sub_dsp21	5978	0, // sub_dsp21
5979	0, // sub_dsp22	5979	0, // sub_dsp22
5980	0, // sub_dsp23	5980	0, // sub_dsp23
5981	0, // sub_hi	5981	0, // sub_hi
5982	0, // sub_lo	5982	0, // sub_lo
5983	0, // sub_hi_then_sub_32	5983	0, // sub_hi_then_sub_32
5984	0, // sub_32_sub_hi_then_sub_32	5984	0, // sub_32_sub_hi_then_sub_32
5985	},	5985	},
5986	{ // COP0	5986	{ // COP0
5987	0, // sub_32	5987	0, // sub_32
5988	0, // sub_64	5988	0, // sub_64
5989	0, // sub_dsp16_19	5989	0, // sub_dsp16_19
5990	0, // sub_dsp20	5990	0, // sub_dsp20
5991	0, // sub_dsp21	5991	0, // sub_dsp21
5992	0, // sub_dsp22	5992	0, // sub_dsp22
5993	0, // sub_dsp23	5993	0, // sub_dsp23
5994	0, // sub_hi	5994	0, // sub_hi
5995	0, // sub_lo	5995	0, // sub_lo
5996	0, // sub_hi_then_sub_32	5996	0, // sub_hi_then_sub_32
5997	0, // sub_32_sub_hi_then_sub_32	5997	0, // sub_32_sub_hi_then_sub_32
5998	},	5998	},
5999	{ // COP2	5999	{ // COP2
6000	0, // sub_32	6000	0, // sub_32
6001	0, // sub_64	6001	0, // sub_64
6002	0, // sub_dsp16_19	6002	0, // sub_dsp16_19
6003	0, // sub_dsp20	6003	0, // sub_dsp20
6004	0, // sub_dsp21	6004	0, // sub_dsp21
6005	0, // sub_dsp22	6005	0, // sub_dsp22
6006	0, // sub_dsp23	6006	0, // sub_dsp23
6007	0, // sub_hi	6007	0, // sub_hi
6008	0, // sub_lo	6008	0, // sub_lo
6009	0, // sub_hi_then_sub_32	6009	0, // sub_hi_then_sub_32
6010	0, // sub_32_sub_hi_then_sub_32	6010	0, // sub_32_sub_hi_then_sub_32
6011	},	6011	},
6012	{ // COP3	6012	{ // COP3
6013	0, // sub_32	6013	0, // sub_32
6014	0, // sub_64	6014	0, // sub_64
6015	0, // sub_dsp16_19	6015	0, // sub_dsp16_19
6016	0, // sub_dsp20	6016	0, // sub_dsp20
6017	0, // sub_dsp21	6017	0, // sub_dsp21
6018	0, // sub_dsp22	6018	0, // sub_dsp22
6019	0, // sub_dsp23	6019	0, // sub_dsp23
6020	0, // sub_hi	6020	0, // sub_hi
6021	0, // sub_lo	6021	0, // sub_lo
6022	0, // sub_hi_then_sub_32	6022	0, // sub_hi_then_sub_32
6023	0, // sub_32_sub_hi_then_sub_32	6023	0, // sub_32_sub_hi_then_sub_32
6024	},	6024	},
6025	{ // DSPR	6025	{ // DSPR
6026	0, // sub_32	6026	0, // sub_32
6027	0, // sub_64	6027	0, // sub_64
6028	0, // sub_dsp16_19	6028	0, // sub_dsp16_19
6029	0, // sub_dsp20	6029	0, // sub_dsp20
6030	0, // sub_dsp21	6030	0, // sub_dsp21
6031	0, // sub_dsp22	6031	0, // sub_dsp22
6032	0, // sub_dsp23	6032	0, // sub_dsp23
6033	0, // sub_hi	6033	0, // sub_hi
6034	0, // sub_lo	6034	0, // sub_lo
6035	0, // sub_hi_then_sub_32	6035	0, // sub_hi_then_sub_32
6036	0, // sub_32_sub_hi_then_sub_32	6036	0, // sub_32_sub_hi_then_sub_32
6037	},	6037	},
6038	{ // FGR32	6038	{ // FGR32
6039	0, // sub_32	6039	0, // sub_32
6040	0, // sub_64	6040	0, // sub_64
6041	0, // sub_dsp16_19	6041	0, // sub_dsp16_19
6042	0, // sub_dsp20	6042	0, // sub_dsp20
6043	0, // sub_dsp21	6043	0, // sub_dsp21
6044	0, // sub_dsp22	6044	0, // sub_dsp22
6045	0, // sub_dsp23	6045	0, // sub_dsp23
6046	0, // sub_hi	6046	0, // sub_hi
6047	0, // sub_lo	6047	0, // sub_lo
6048	0, // sub_hi_then_sub_32	6048	0, // sub_hi_then_sub_32
6049	0, // sub_32_sub_hi_then_sub_32	6049	0, // sub_32_sub_hi_then_sub_32
6050	},	6050	},
6051	{ // FGRCC	6051	{ // FGRCC
6052	0, // sub_32	6052	0, // sub_32
6053	0, // sub_64	6053	0, // sub_64
6054	0, // sub_dsp16_19	6054	0, // sub_dsp16_19
6055	0, // sub_dsp20	6055	0, // sub_dsp20
6056	0, // sub_dsp21	6056	0, // sub_dsp21
6057	0, // sub_dsp22	6057	0, // sub_dsp22
6058	0, // sub_dsp23	6058	0, // sub_dsp23
6059	0, // sub_hi	6059	0, // sub_hi
6060	0, // sub_lo	6060	0, // sub_lo
6061	0, // sub_hi_then_sub_32	6061	0, // sub_hi_then_sub_32
6062	0, // sub_32_sub_hi_then_sub_32	6062	0, // sub_32_sub_hi_then_sub_32
6063	},	6063	},
6064	{ // GPR32	6064	{ // GPR32
6065	0, // sub_32	6065	0, // sub_32
6066	0, // sub_64	6066	0, // sub_64
6067	0, // sub_dsp16_19	6067	0, // sub_dsp16_19
6068	0, // sub_dsp20	6068	0, // sub_dsp20
6069	0, // sub_dsp21	6069	0, // sub_dsp21
6070	0, // sub_dsp22	6070	0, // sub_dsp22
6071	0, // sub_dsp23	6071	0, // sub_dsp23
6072	0, // sub_hi	6072	0, // sub_hi
6073	0, // sub_lo	6073	0, // sub_lo
6074	0, // sub_hi_then_sub_32	6074	0, // sub_hi_then_sub_32
6075	0, // sub_32_sub_hi_then_sub_32	6075	0, // sub_32_sub_hi_then_sub_32
6076	},	6076	},
6077	{ // HWRegs	6077	{ // HWRegs
6078	0, // sub_32	6078	0, // sub_32
6079	0, // sub_64	6079	0, // sub_64
6080	0, // sub_dsp16_19	6080	0, // sub_dsp16_19
6081	0, // sub_dsp20	6081	0, // sub_dsp20
6082	0, // sub_dsp21	6082	0, // sub_dsp21
6083	0, // sub_dsp22	6083	0, // sub_dsp22
6084	0, // sub_dsp23	6084	0, // sub_dsp23
6085	0, // sub_hi	6085	0, // sub_hi
6086	0, // sub_lo	6086	0, // sub_lo
6087	0, // sub_hi_then_sub_32	6087	0, // sub_hi_then_sub_32
6088	0, // sub_32_sub_hi_then_sub_32	6088	0, // sub_32_sub_hi_then_sub_32
6089	},	6089	},
6090	{ // MSACtrl	6090	{ // MSACtrl
6091	0, // sub_32	6091	0, // sub_32
6092	0, // sub_64	6092	0, // sub_64
6093	0, // sub_dsp16_19	6093	0, // sub_dsp16_19
6094	0, // sub_dsp20	6094	0, // sub_dsp20
6095	0, // sub_dsp21	6095	0, // sub_dsp21
6096	0, // sub_dsp22	6096	0, // sub_dsp22
6097	0, // sub_dsp23	6097	0, // sub_dsp23
6098	0, // sub_hi	6098	0, // sub_hi
6099	0, // sub_lo	6099	0, // sub_lo
6100	0, // sub_hi_then_sub_32	6100	0, // sub_hi_then_sub_32
6101	0, // sub_32_sub_hi_then_sub_32	6101	0, // sub_32_sub_hi_then_sub_32
6102	},	6102	},
6103	{ // GPR32NONZERO	6103	{ // GPR32NONZERO
6104	0, // sub_32	6104	0, // sub_32
6105	0, // sub_64	6105	0, // sub_64
6106	0, // sub_dsp16_19	6106	0, // sub_dsp16_19
6107	0, // sub_dsp20	6107	0, // sub_dsp20
6108	0, // sub_dsp21	6108	0, // sub_dsp21
6109	0, // sub_dsp22	6109	0, // sub_dsp22
6110	0, // sub_dsp23	6110	0, // sub_dsp23
6111	0, // sub_hi	6111	0, // sub_hi
6112	0, // sub_lo	6112	0, // sub_lo
6113	0, // sub_hi_then_sub_32	6113	0, // sub_hi_then_sub_32
6114	0, // sub_32_sub_hi_then_sub_32	6114	0, // sub_32_sub_hi_then_sub_32
6115	},	6115	},
6116	{ // CPU16RegsPlusSP	6116	{ // CPU16RegsPlusSP
6117	0, // sub_32	6117	0, // sub_32
6118	0, // sub_64	6118	0, // sub_64
6119	0, // sub_dsp16_19	6119	0, // sub_dsp16_19
6120	0, // sub_dsp20	6120	0, // sub_dsp20
6121	0, // sub_dsp21	6121	0, // sub_dsp21
6122	0, // sub_dsp22	6122	0, // sub_dsp22
6123	0, // sub_dsp23	6123	0, // sub_dsp23
6124	0, // sub_hi	6124	0, // sub_hi
6125	0, // sub_lo	6125	0, // sub_lo
6126	0, // sub_hi_then_sub_32	6126	0, // sub_hi_then_sub_32
6127	0, // sub_32_sub_hi_then_sub_32	6127	0, // sub_32_sub_hi_then_sub_32
6128	},	6128	},
6129	{ // CPU16Regs	6129	{ // CPU16Regs
6130	0, // sub_32	6130	0, // sub_32
6131	0, // sub_64	6131	0, // sub_64
6132	0, // sub_dsp16_19	6132	0, // sub_dsp16_19
6133	0, // sub_dsp20	6133	0, // sub_dsp20
6134	0, // sub_dsp21	6134	0, // sub_dsp21
6135	0, // sub_dsp22	6135	0, // sub_dsp22
6136	0, // sub_dsp23	6136	0, // sub_dsp23
6137	0, // sub_hi	6137	0, // sub_hi
6138	0, // sub_lo	6138	0, // sub_lo
6139	0, // sub_hi_then_sub_32	6139	0, // sub_hi_then_sub_32
6140	0, // sub_32_sub_hi_then_sub_32	6140	0, // sub_32_sub_hi_then_sub_32
6141	},	6141	},
6142	{ // FCC	6142	{ // FCC
6143	0, // sub_32	6143	0, // sub_32
6144	0, // sub_64	6144	0, // sub_64
6145	0, // sub_dsp16_19	6145	0, // sub_dsp16_19
6146	0, // sub_dsp20	6146	0, // sub_dsp20
6147	0, // sub_dsp21	6147	0, // sub_dsp21
6148	0, // sub_dsp22	6148	0, // sub_dsp22
6149	0, // sub_dsp23	6149	0, // sub_dsp23
6150	0, // sub_hi	6150	0, // sub_hi
6151	0, // sub_lo	6151	0, // sub_lo
6152	0, // sub_hi_then_sub_32	6152	0, // sub_hi_then_sub_32
6153	0, // sub_32_sub_hi_then_sub_32	6153	0, // sub_32_sub_hi_then_sub_32
6154	},	6154	},
6155	{ // GPRMM16	6155	{ // GPRMM16
6156	0, // sub_32	6156	0, // sub_32
6157	0, // sub_64	6157	0, // sub_64
6158	0, // sub_dsp16_19	6158	0, // sub_dsp16_19
6159	0, // sub_dsp20	6159	0, // sub_dsp20
6160	0, // sub_dsp21	6160	0, // sub_dsp21
6161	0, // sub_dsp22	6161	0, // sub_dsp22
6162	0, // sub_dsp23	6162	0, // sub_dsp23
6163	0, // sub_hi	6163	0, // sub_hi
6164	0, // sub_lo	6164	0, // sub_lo
6165	0, // sub_hi_then_sub_32	6165	0, // sub_hi_then_sub_32
6166	0, // sub_32_sub_hi_then_sub_32	6166	0, // sub_32_sub_hi_then_sub_32
6167	},	6167	},
6168	{ // GPRMM16MoveP	6168	{ // GPRMM16MoveP
6169	0, // sub_32	6169	0, // sub_32
6170	0, // sub_64	6170	0, // sub_64
6171	0, // sub_dsp16_19	6171	0, // sub_dsp16_19
6172	0, // sub_dsp20	6172	0, // sub_dsp20
6173	0, // sub_dsp21	6173	0, // sub_dsp21
6174	0, // sub_dsp22	6174	0, // sub_dsp22
6175	0, // sub_dsp23	6175	0, // sub_dsp23
6176	0, // sub_hi	6176	0, // sub_hi
6177	0, // sub_lo	6177	0, // sub_lo
6178	0, // sub_hi_then_sub_32	6178	0, // sub_hi_then_sub_32
6179	0, // sub_32_sub_hi_then_sub_32	6179	0, // sub_32_sub_hi_then_sub_32
6180	},	6180	},
6181	{ // GPRMM16Zero	6181	{ // GPRMM16Zero
6182	0, // sub_32	6182	0, // sub_32
6183	0, // sub_64	6183	0, // sub_64
6184	0, // sub_dsp16_19	6184	0, // sub_dsp16_19
6185	0, // sub_dsp20	6185	0, // sub_dsp20
6186	0, // sub_dsp21	6186	0, // sub_dsp21
6187	0, // sub_dsp22	6187	0, // sub_dsp22
6188	0, // sub_dsp23	6188	0, // sub_dsp23
6189	0, // sub_hi	6189	0, // sub_hi
6190	0, // sub_lo	6190	0, // sub_lo
6191	0, // sub_hi_then_sub_32	6191	0, // sub_hi_then_sub_32
6192	0, // sub_32_sub_hi_then_sub_32	6192	0, // sub_32_sub_hi_then_sub_32
6193	},	6193	},
6194	{ // CPU16Regs_and_GPRMM16Zero	6194	{ // CPU16Regs_and_GPRMM16Zero
6195	0, // sub_32	6195	0, // sub_32
6196	0, // sub_64	6196	0, // sub_64
6197	0, // sub_dsp16_19	6197	0, // sub_dsp16_19
6198	0, // sub_dsp20	6198	0, // sub_dsp20
6199	0, // sub_dsp21	6199	0, // sub_dsp21
6200	0, // sub_dsp22	6200	0, // sub_dsp22
6201	0, // sub_dsp23	6201	0, // sub_dsp23
6202	0, // sub_hi	6202	0, // sub_hi
6203	0, // sub_lo	6203	0, // sub_lo
6204	0, // sub_hi_then_sub_32	6204	0, // sub_hi_then_sub_32
6205	0, // sub_32_sub_hi_then_sub_32	6205	0, // sub_32_sub_hi_then_sub_32
6206	},	6206	},
6207	{ // GPR32NONZERO_and_GPRMM16MoveP	6207	{ // GPR32NONZERO_and_GPRMM16MoveP
6208	0, // sub_32	6208	0, // sub_32
6209	0, // sub_64	6209	0, // sub_64
6210	0, // sub_dsp16_19	6210	0, // sub_dsp16_19
6211	0, // sub_dsp20	6211	0, // sub_dsp20
6212	0, // sub_dsp21	6212	0, // sub_dsp21
6213	0, // sub_dsp22	6213	0, // sub_dsp22
6214	0, // sub_dsp23	6214	0, // sub_dsp23
6215	0, // sub_hi	6215	0, // sub_hi
6216	0, // sub_lo	6216	0, // sub_lo
6217	0, // sub_hi_then_sub_32	6217	0, // sub_hi_then_sub_32
6218	0, // sub_32_sub_hi_then_sub_32	6218	0, // sub_32_sub_hi_then_sub_32
6219	},	6219	},
6220	{ // GPRMM16MovePPairSecond	6220	{ // GPRMM16MovePPairSecond
6221	0, // sub_32	6221	0, // sub_32
6222	0, // sub_64	6222	0, // sub_64
6223	0, // sub_dsp16_19	6223	0, // sub_dsp16_19
6224	0, // sub_dsp20	6224	0, // sub_dsp20
6225	0, // sub_dsp21	6225	0, // sub_dsp21
6226	0, // sub_dsp22	6226	0, // sub_dsp22
6227	0, // sub_dsp23	6227	0, // sub_dsp23
6228	0, // sub_hi	6228	0, // sub_hi
6229	0, // sub_lo	6229	0, // sub_lo
6230	0, // sub_hi_then_sub_32	6230	0, // sub_hi_then_sub_32
6231	0, // sub_32_sub_hi_then_sub_32	6231	0, // sub_32_sub_hi_then_sub_32
6232	},	6232	},
6233	{ // CPU16Regs_and_GPRMM16MoveP	6233	{ // CPU16Regs_and_GPRMM16MoveP
6234	0, // sub_32	6234	0, // sub_32
6235	0, // sub_64	6235	0, // sub_64
6236	0, // sub_dsp16_19	6236	0, // sub_dsp16_19
6237	0, // sub_dsp20	6237	0, // sub_dsp20
6238	0, // sub_dsp21	6238	0, // sub_dsp21
6239	0, // sub_dsp22	6239	0, // sub_dsp22
6240	0, // sub_dsp23	6240	0, // sub_dsp23
6241	0, // sub_hi	6241	0, // sub_hi
6242	0, // sub_lo	6242	0, // sub_lo
6243	0, // sub_hi_then_sub_32	6243	0, // sub_hi_then_sub_32
6244	0, // sub_32_sub_hi_then_sub_32	6244	0, // sub_32_sub_hi_then_sub_32
6245	},	6245	},
6246	{ // GPRMM16MoveP_and_GPRMM16Zero	6246	{ // GPRMM16MoveP_and_GPRMM16Zero
6247	0, // sub_32	6247	0, // sub_32
6248	0, // sub_64	6248	0, // sub_64
6249	0, // sub_dsp16_19	6249	0, // sub_dsp16_19
6250	0, // sub_dsp20	6250	0, // sub_dsp20
6251	0, // sub_dsp21	6251	0, // sub_dsp21
6252	0, // sub_dsp22	6252	0, // sub_dsp22
6253	0, // sub_dsp23	6253	0, // sub_dsp23
6254	0, // sub_hi	6254	0, // sub_hi
6255	0, // sub_lo	6255	0, // sub_lo
6256	0, // sub_hi_then_sub_32	6256	0, // sub_hi_then_sub_32
6257	0, // sub_32_sub_hi_then_sub_32	6257	0, // sub_32_sub_hi_then_sub_32
6258	},	6258	},
6259	{ // HI32DSP	6259	{ // HI32DSP
6260	0, // sub_32	6260	0, // sub_32
6261	0, // sub_64	6261	0, // sub_64
6262	0, // sub_dsp16_19	6262	0, // sub_dsp16_19
6263	0, // sub_dsp20	6263	0, // sub_dsp20
6264	0, // sub_dsp21	6264	0, // sub_dsp21
6265	0, // sub_dsp22	6265	0, // sub_dsp22
6266	0, // sub_dsp23	6266	0, // sub_dsp23
6267	0, // sub_hi	6267	0, // sub_hi
6268	0, // sub_lo	6268	0, // sub_lo
6269	0, // sub_hi_then_sub_32	6269	0, // sub_hi_then_sub_32
6270	0, // sub_32_sub_hi_then_sub_32	6270	0, // sub_32_sub_hi_then_sub_32
6271	},	6271	},
6272	{ // LO32DSP	6272	{ // LO32DSP
6273	0, // sub_32	6273	0, // sub_32
6274	0, // sub_64	6274	0, // sub_64
6275	0, // sub_dsp16_19	6275	0, // sub_dsp16_19
6276	0, // sub_dsp20	6276	0, // sub_dsp20
6277	0, // sub_dsp21	6277	0, // sub_dsp21
6278	0, // sub_dsp22	6278	0, // sub_dsp22
6279	0, // sub_dsp23	6279	0, // sub_dsp23
6280	0, // sub_hi	6280	0, // sub_hi
6281	0, // sub_lo	6281	0, // sub_lo
6282	0, // sub_hi_then_sub_32	6282	0, // sub_hi_then_sub_32
6283	0, // sub_32_sub_hi_then_sub_32	6283	0, // sub_32_sub_hi_then_sub_32
6284	},	6284	},
6285	{ // CPU16Regs_and_GPRMM16MovePPairSecond	6285	{ // CPU16Regs_and_GPRMM16MovePPairSecond
6286	0, // sub_32	6286	0, // sub_32
6287	0, // sub_64	6287	0, // sub_64
6288	0, // sub_dsp16_19	6288	0, // sub_dsp16_19
6289	0, // sub_dsp20	6289	0, // sub_dsp20
6290	0, // sub_dsp21	6290	0, // sub_dsp21
6291	0, // sub_dsp22	6291	0, // sub_dsp22
6292	0, // sub_dsp23	6292	0, // sub_dsp23
6293	0, // sub_hi	6293	0, // sub_hi
6294	0, // sub_lo	6294	0, // sub_lo
6295	0, // sub_hi_then_sub_32	6295	0, // sub_hi_then_sub_32
6296	0, // sub_32_sub_hi_then_sub_32	6296	0, // sub_32_sub_hi_then_sub_32
6297	},	6297	},
6298	{ // GPRMM16MovePPairFirst	6298	{ // GPRMM16MovePPairFirst
6299	0, // sub_32	6299	0, // sub_32
6300	0, // sub_64	6300	0, // sub_64
6301	0, // sub_dsp16_19	6301	0, // sub_dsp16_19
6302	0, // sub_dsp20	6302	0, // sub_dsp20
6303	0, // sub_dsp21	6303	0, // sub_dsp21
6304	0, // sub_dsp22	6304	0, // sub_dsp22
6305	0, // sub_dsp23	6305	0, // sub_dsp23
6306	0, // sub_hi	6306	0, // sub_hi
6307	0, // sub_lo	6307	0, // sub_lo
6308	0, // sub_hi_then_sub_32	6308	0, // sub_hi_then_sub_32
6309	0, // sub_32_sub_hi_then_sub_32	6309	0, // sub_32_sub_hi_then_sub_32
6310	},	6310	},
6311	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	6311	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6312	0, // sub_32	6312	0, // sub_32
6313	0, // sub_64	6313	0, // sub_64
6314	0, // sub_dsp16_19	6314	0, // sub_dsp16_19
6315	0, // sub_dsp20	6315	0, // sub_dsp20
6316	0, // sub_dsp21	6316	0, // sub_dsp21
6317	0, // sub_dsp22	6317	0, // sub_dsp22
6318	0, // sub_dsp23	6318	0, // sub_dsp23
6319	0, // sub_hi	6319	0, // sub_hi
6320	0, // sub_lo	6320	0, // sub_lo
6321	0, // sub_hi_then_sub_32	6321	0, // sub_hi_then_sub_32
6322	0, // sub_32_sub_hi_then_sub_32	6322	0, // sub_32_sub_hi_then_sub_32
6323	},	6323	},
6324	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	6324	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6325	0, // sub_32	6325	0, // sub_32
6326	0, // sub_64	6326	0, // sub_64
6327	0, // sub_dsp16_19	6327	0, // sub_dsp16_19
6328	0, // sub_dsp20	6328	0, // sub_dsp20
6329	0, // sub_dsp21	6329	0, // sub_dsp21
6330	0, // sub_dsp22	6330	0, // sub_dsp22
6331	0, // sub_dsp23	6331	0, // sub_dsp23
6332	0, // sub_hi	6332	0, // sub_hi
6333	0, // sub_lo	6333	0, // sub_lo
6334	0, // sub_hi_then_sub_32	6334	0, // sub_hi_then_sub_32
6335	0, // sub_32_sub_hi_then_sub_32	6335	0, // sub_32_sub_hi_then_sub_32
6336	},	6336	},
6337	{ // CPURAReg	6337	{ // CPURAReg
6338	0, // sub_32	6338	0, // sub_32
6339	0, // sub_64	6339	0, // sub_64
6340	0, // sub_dsp16_19	6340	0, // sub_dsp16_19
6341	0, // sub_dsp20	6341	0, // sub_dsp20
6342	0, // sub_dsp21	6342	0, // sub_dsp21
6343	0, // sub_dsp22	6343	0, // sub_dsp22
6344	0, // sub_dsp23	6344	0, // sub_dsp23
6345	0, // sub_hi	6345	0, // sub_hi
6346	0, // sub_lo	6346	0, // sub_lo
6347	0, // sub_hi_then_sub_32	6347	0, // sub_hi_then_sub_32
6348	0, // sub_32_sub_hi_then_sub_32	6348	0, // sub_32_sub_hi_then_sub_32
6349	},	6349	},
6350	{ // CPUSPReg	6350	{ // CPUSPReg
6351	0, // sub_32	6351	0, // sub_32
6352	0, // sub_64	6352	0, // sub_64
6353	0, // sub_dsp16_19	6353	0, // sub_dsp16_19
6354	0, // sub_dsp20	6354	0, // sub_dsp20
6355	0, // sub_dsp21	6355	0, // sub_dsp21
6356	0, // sub_dsp22	6356	0, // sub_dsp22
6357	0, // sub_dsp23	6357	0, // sub_dsp23
6358	0, // sub_hi	6358	0, // sub_hi
6359	0, // sub_lo	6359	0, // sub_lo
6360	0, // sub_hi_then_sub_32	6360	0, // sub_hi_then_sub_32
6361	0, // sub_32_sub_hi_then_sub_32	6361	0, // sub_32_sub_hi_then_sub_32
6362	},	6362	},
6363	{ // DSPCC	6363	{ // DSPCC
6364	0, // sub_32	6364	0, // sub_32
6365	0, // sub_64	6365	0, // sub_64
6366	0, // sub_dsp16_19	6366	0, // sub_dsp16_19
6367	0, // sub_dsp20	6367	0, // sub_dsp20
6368	0, // sub_dsp21	6368	0, // sub_dsp21
6369	0, // sub_dsp22	6369	0, // sub_dsp22
6370	0, // sub_dsp23	6370	0, // sub_dsp23
6371	0, // sub_hi	6371	0, // sub_hi
6372	0, // sub_lo	6372	0, // sub_lo
6373	0, // sub_hi_then_sub_32	6373	0, // sub_hi_then_sub_32
6374	0, // sub_32_sub_hi_then_sub_32	6374	0, // sub_32_sub_hi_then_sub_32
6375	},	6375	},
6376	{ // GP32	6376	{ // GP32
6377	0, // sub_32	6377	0, // sub_32
6378	0, // sub_64	6378	0, // sub_64
6379	0, // sub_dsp16_19	6379	0, // sub_dsp16_19
6380	0, // sub_dsp20	6380	0, // sub_dsp20
6381	0, // sub_dsp21	6381	0, // sub_dsp21
6382	0, // sub_dsp22	6382	0, // sub_dsp22
6383	0, // sub_dsp23	6383	0, // sub_dsp23
6384	0, // sub_hi	6384	0, // sub_hi
6385	0, // sub_lo	6385	0, // sub_lo
6386	0, // sub_hi_then_sub_32	6386	0, // sub_hi_then_sub_32
6387	0, // sub_32_sub_hi_then_sub_32	6387	0, // sub_32_sub_hi_then_sub_32
6388	},	6388	},
6389	{ // GPR32ZERO	6389	{ // GPR32ZERO
6390	0, // sub_32	6390	0, // sub_32
6391	0, // sub_64	6391	0, // sub_64
6392	0, // sub_dsp16_19	6392	0, // sub_dsp16_19
6393	0, // sub_dsp20	6393	0, // sub_dsp20
6394	0, // sub_dsp21	6394	0, // sub_dsp21
6395	0, // sub_dsp22	6395	0, // sub_dsp22
6396	0, // sub_dsp23	6396	0, // sub_dsp23
6397	0, // sub_hi	6397	0, // sub_hi
6398	0, // sub_lo	6398	0, // sub_lo
6399	0, // sub_hi_then_sub_32	6399	0, // sub_hi_then_sub_32
6400	0, // sub_32_sub_hi_then_sub_32	6400	0, // sub_32_sub_hi_then_sub_32
6401	},	6401	},
6402	{ // HI32	6402	{ // HI32
6403	0, // sub_32	6403	0, // sub_32
6404	0, // sub_64	6404	0, // sub_64
6405	0, // sub_dsp16_19	6405	0, // sub_dsp16_19
6406	0, // sub_dsp20	6406	0, // sub_dsp20
6407	0, // sub_dsp21	6407	0, // sub_dsp21
6408	0, // sub_dsp22	6408	0, // sub_dsp22
6409	0, // sub_dsp23	6409	0, // sub_dsp23
6410	0, // sub_hi	6410	0, // sub_hi
6411	0, // sub_lo	6411	0, // sub_lo
6412	0, // sub_hi_then_sub_32	6412	0, // sub_hi_then_sub_32
6413	0, // sub_32_sub_hi_then_sub_32	6413	0, // sub_32_sub_hi_then_sub_32
6414	},	6414	},
6415	{ // LO32	6415	{ // LO32
6416	0, // sub_32	6416	0, // sub_32
6417	0, // sub_64	6417	0, // sub_64
6418	0, // sub_dsp16_19	6418	0, // sub_dsp16_19
6419	0, // sub_dsp20	6419	0, // sub_dsp20
6420	0, // sub_dsp21	6420	0, // sub_dsp21
6421	0, // sub_dsp22	6421	0, // sub_dsp22
6422	0, // sub_dsp23	6422	0, // sub_dsp23
6423	0, // sub_hi	6423	0, // sub_hi
6424	0, // sub_lo	6424	0, // sub_lo
6425	0, // sub_hi_then_sub_32	6425	0, // sub_hi_then_sub_32
6426	0, // sub_32_sub_hi_then_sub_32	6426	0, // sub_32_sub_hi_then_sub_32
6427	},	6427	},
6428	{ // SP32	6428	{ // SP32
6429	0, // sub_32	6429	0, // sub_32
6430	0, // sub_64	6430	0, // sub_64
6431	0, // sub_dsp16_19	6431	0, // sub_dsp16_19
6432	0, // sub_dsp20	6432	0, // sub_dsp20
6433	0, // sub_dsp21	6433	0, // sub_dsp21
6434	0, // sub_dsp22	6434	0, // sub_dsp22
6435	0, // sub_dsp23	6435	0, // sub_dsp23
6436	0, // sub_hi	6436	0, // sub_hi
6437	0, // sub_lo	6437	0, // sub_lo
6438	0, // sub_hi_then_sub_32	6438	0, // sub_hi_then_sub_32
6439	0, // sub_32_sub_hi_then_sub_32	6439	0, // sub_32_sub_hi_then_sub_32
6440	},	6440	},
6441	{ // FGR64	6441	{ // FGR64
6442	0, // sub_32	6442	0, // sub_32
6443	0, // sub_64	6443	0, // sub_64
6444	0, // sub_dsp16_19	6444	0, // sub_dsp16_19
6445	0, // sub_dsp20	6445	0, // sub_dsp20
6446	0, // sub_dsp21	6446	0, // sub_dsp21
6447	0, // sub_dsp22	6447	0, // sub_dsp22
6448	0, // sub_dsp23	6448	0, // sub_dsp23
6449	38, // sub_hi -> FGR64	6449	38, // sub_hi -> FGR64
6450	38, // sub_lo -> FGR64	6450	38, // sub_lo -> FGR64
6451	0, // sub_hi_then_sub_32	6451	0, // sub_hi_then_sub_32
6452	0, // sub_32_sub_hi_then_sub_32	6452	0, // sub_32_sub_hi_then_sub_32
6453	},	6453	},
6454	{ // GPR64	6454	{ // GPR64
6455	39, // sub_32 -> GPR64	6455	39, // sub_32 -> GPR64
6456	0, // sub_64	6456	0, // sub_64
6457	0, // sub_dsp16_19	6457	0, // sub_dsp16_19
6458	0, // sub_dsp20	6458	0, // sub_dsp20
6459	0, // sub_dsp21	6459	0, // sub_dsp21
6460	0, // sub_dsp22	6460	0, // sub_dsp22
6461	0, // sub_dsp23	6461	0, // sub_dsp23
6462	0, // sub_hi	6462	0, // sub_hi
6463	0, // sub_lo	6463	0, // sub_lo
6464	0, // sub_hi_then_sub_32	6464	0, // sub_hi_then_sub_32
6465	0, // sub_32_sub_hi_then_sub_32	6465	0, // sub_32_sub_hi_then_sub_32
6466	},	6466	},
6467	{ // GPR64_with_sub_32_in_GPR32NONZERO	6467	{ // GPR64_with_sub_32_in_GPR32NONZERO
6468	40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO	6468	40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
6469	0, // sub_64	6469	0, // sub_64
6470	0, // sub_dsp16_19	6470	0, // sub_dsp16_19
6471	0, // sub_dsp20	6471	0, // sub_dsp20
6472	0, // sub_dsp21	6472	0, // sub_dsp21
6473	0, // sub_dsp22	6473	0, // sub_dsp22
6474	0, // sub_dsp23	6474	0, // sub_dsp23
6475	0, // sub_hi	6475	0, // sub_hi
6476	0, // sub_lo	6476	0, // sub_lo
6477	0, // sub_hi_then_sub_32	6477	0, // sub_hi_then_sub_32
6478	0, // sub_32_sub_hi_then_sub_32	6478	0, // sub_32_sub_hi_then_sub_32
6479	},	6479	},
6480	{ // AFGR64	6480	{ // AFGR64
6481	0, // sub_32	6481	0, // sub_32
6482	0, // sub_64	6482	0, // sub_64
6483	0, // sub_dsp16_19	6483	0, // sub_dsp16_19
6484	0, // sub_dsp20	6484	0, // sub_dsp20
6485	0, // sub_dsp21	6485	0, // sub_dsp21
6486	0, // sub_dsp22	6486	0, // sub_dsp22
6487	0, // sub_dsp23	6487	0, // sub_dsp23
6488	41, // sub_hi -> AFGR64	6488	41, // sub_hi -> AFGR64
6489	41, // sub_lo -> AFGR64	6489	41, // sub_lo -> AFGR64
6490	0, // sub_hi_then_sub_32	6490	0, // sub_hi_then_sub_32
6491	0, // sub_32_sub_hi_then_sub_32	6491	0, // sub_32_sub_hi_then_sub_32
6492	},	6492	},
6493	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	6493	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
6494	42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP	6494	42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
6495	0, // sub_64	6495	0, // sub_64
6496	0, // sub_dsp16_19	6496	0, // sub_dsp16_19
6497	0, // sub_dsp20	6497	0, // sub_dsp20
6498	0, // sub_dsp21	6498	0, // sub_dsp21
6499	0, // sub_dsp22	6499	0, // sub_dsp22
6500	0, // sub_dsp23	6500	0, // sub_dsp23
6501	0, // sub_hi	6501	0, // sub_hi
6502	0, // sub_lo	6502	0, // sub_lo
6503	0, // sub_hi_then_sub_32	6503	0, // sub_hi_then_sub_32
6504	0, // sub_32_sub_hi_then_sub_32	6504	0, // sub_32_sub_hi_then_sub_32
6505	},	6505	},
6506	{ // GPR64_with_sub_32_in_CPU16Regs	6506	{ // GPR64_with_sub_32_in_CPU16Regs
6507	43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs	6507	43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
6508	0, // sub_64	6508	0, // sub_64
6509	0, // sub_dsp16_19	6509	0, // sub_dsp16_19
6510	0, // sub_dsp20	6510	0, // sub_dsp20
6511	0, // sub_dsp21	6511	0, // sub_dsp21
6512	0, // sub_dsp22	6512	0, // sub_dsp22
6513	0, // sub_dsp23	6513	0, // sub_dsp23
6514	0, // sub_hi	6514	0, // sub_hi
6515	0, // sub_lo	6515	0, // sub_lo
6516	0, // sub_hi_then_sub_32	6516	0, // sub_hi_then_sub_32
6517	0, // sub_32_sub_hi_then_sub_32	6517	0, // sub_32_sub_hi_then_sub_32
6518	},	6518	},
6519	{ // GPR64_with_sub_32_in_GPRMM16MoveP	6519	{ // GPR64_with_sub_32_in_GPRMM16MoveP
6520	44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP	6520	44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
6521	0, // sub_64	6521	0, // sub_64
6522	0, // sub_dsp16_19	6522	0, // sub_dsp16_19
6523	0, // sub_dsp20	6523	0, // sub_dsp20
6524	0, // sub_dsp21	6524	0, // sub_dsp21
6525	0, // sub_dsp22	6525	0, // sub_dsp22
6526	0, // sub_dsp23	6526	0, // sub_dsp23
6527	0, // sub_hi	6527	0, // sub_hi
6528	0, // sub_lo	6528	0, // sub_lo
6529	0, // sub_hi_then_sub_32	6529	0, // sub_hi_then_sub_32
6530	0, // sub_32_sub_hi_then_sub_32	6530	0, // sub_32_sub_hi_then_sub_32
6531	},	6531	},
6532	{ // GPR64_with_sub_32_in_GPRMM16Zero	6532	{ // GPR64_with_sub_32_in_GPRMM16Zero
6533	45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero	6533	45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
6534	0, // sub_64	6534	0, // sub_64
6535	0, // sub_dsp16_19	6535	0, // sub_dsp16_19
6536	0, // sub_dsp20	6536	0, // sub_dsp20
6537	0, // sub_dsp21	6537	0, // sub_dsp21
6538	0, // sub_dsp22	6538	0, // sub_dsp22
6539	0, // sub_dsp23	6539	0, // sub_dsp23
6540	0, // sub_hi	6540	0, // sub_hi
6541	0, // sub_lo	6541	0, // sub_lo
6542	0, // sub_hi_then_sub_32	6542	0, // sub_hi_then_sub_32
6543	0, // sub_32_sub_hi_then_sub_32	6543	0, // sub_32_sub_hi_then_sub_32
6544	},	6544	},
6545	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	6545	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6546	46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	6546	46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
6547	0, // sub_64	6547	0, // sub_64
6548	0, // sub_dsp16_19	6548	0, // sub_dsp16_19
6549	0, // sub_dsp20	6549	0, // sub_dsp20
6550	0, // sub_dsp21	6550	0, // sub_dsp21
6551	0, // sub_dsp22	6551	0, // sub_dsp22
6552	0, // sub_dsp23	6552	0, // sub_dsp23
6553	0, // sub_hi	6553	0, // sub_hi
6554	0, // sub_lo	6554	0, // sub_lo
6555	0, // sub_hi_then_sub_32	6555	0, // sub_hi_then_sub_32
6556	0, // sub_32_sub_hi_then_sub_32	6556	0, // sub_32_sub_hi_then_sub_32
6557	},	6557	},
6558	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	6558	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6559	47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	6559	47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
6560	0, // sub_64	6560	0, // sub_64
6561	0, // sub_dsp16_19	6561	0, // sub_dsp16_19
6562	0, // sub_dsp20	6562	0, // sub_dsp20
6563	0, // sub_dsp21	6563	0, // sub_dsp21
6564	0, // sub_dsp22	6564	0, // sub_dsp22
6565	0, // sub_dsp23	6565	0, // sub_dsp23
6566	0, // sub_hi	6566	0, // sub_hi
6567	0, // sub_lo	6567	0, // sub_lo
6568	0, // sub_hi_then_sub_32	6568	0, // sub_hi_then_sub_32
6569	0, // sub_32_sub_hi_then_sub_32	6569	0, // sub_32_sub_hi_then_sub_32
6570	},	6570	},
6571	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	6571	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6572	48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond	6572	48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
6573	0, // sub_64	6573	0, // sub_64
6574	0, // sub_dsp16_19	6574	0, // sub_dsp16_19
6575	0, // sub_dsp20	6575	0, // sub_dsp20
6576	0, // sub_dsp21	6576	0, // sub_dsp21
6577	0, // sub_dsp22	6577	0, // sub_dsp22
6578	0, // sub_dsp23	6578	0, // sub_dsp23
6579	0, // sub_hi	6579	0, // sub_hi
6580	0, // sub_lo	6580	0, // sub_lo
6581	0, // sub_hi_then_sub_32	6581	0, // sub_hi_then_sub_32
6582	0, // sub_32_sub_hi_then_sub_32	6582	0, // sub_32_sub_hi_then_sub_32
6583	},	6583	},
6584	{ // ACC64DSP	6584	{ // ACC64DSP
6585	0, // sub_32	6585	0, // sub_32
6586	0, // sub_64	6586	0, // sub_64
6587	0, // sub_dsp16_19	6587	0, // sub_dsp16_19
6588	0, // sub_dsp20	6588	0, // sub_dsp20
6589	0, // sub_dsp21	6589	0, // sub_dsp21
6590	0, // sub_dsp22	6590	0, // sub_dsp22
6591	0, // sub_dsp23	6591	0, // sub_dsp23
6592	49, // sub_hi -> ACC64DSP	6592	49, // sub_hi -> ACC64DSP
6593	49, // sub_lo -> ACC64DSP	6593	49, // sub_lo -> ACC64DSP
6594	0, // sub_hi_then_sub_32	6594	0, // sub_hi_then_sub_32
6595	0, // sub_32_sub_hi_then_sub_32	6595	0, // sub_32_sub_hi_then_sub_32
6596	},	6596	},
6597	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	6597	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6598	50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	6598	50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
6599	0, // sub_64	6599	0, // sub_64
6600	0, // sub_dsp16_19	6600	0, // sub_dsp16_19
6601	0, // sub_dsp20	6601	0, // sub_dsp20
6602	0, // sub_dsp21	6602	0, // sub_dsp21
6603	0, // sub_dsp22	6603	0, // sub_dsp22
6604	0, // sub_dsp23	6604	0, // sub_dsp23
6605	0, // sub_hi	6605	0, // sub_hi
6606	0, // sub_lo	6606	0, // sub_lo
6607	0, // sub_hi_then_sub_32	6607	0, // sub_hi_then_sub_32
6608	0, // sub_32_sub_hi_then_sub_32	6608	0, // sub_32_sub_hi_then_sub_32
6609	},	6609	},
6610	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	6610	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6611	51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	6611	51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
6612	0, // sub_64	6612	0, // sub_64
6613	0, // sub_dsp16_19	6613	0, // sub_dsp16_19
6614	0, // sub_dsp20	6614	0, // sub_dsp20
6615	0, // sub_dsp21	6615	0, // sub_dsp21
6616	0, // sub_dsp22	6616	0, // sub_dsp22
6617	0, // sub_dsp23	6617	0, // sub_dsp23
6618	0, // sub_hi	6618	0, // sub_hi
6619	0, // sub_lo	6619	0, // sub_lo
6620	0, // sub_hi_then_sub_32	6620	0, // sub_hi_then_sub_32
6621	0, // sub_32_sub_hi_then_sub_32	6621	0, // sub_32_sub_hi_then_sub_32
6622	},	6622	},
6623	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	6623	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6624	52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	6624	52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
6625	0, // sub_64	6625	0, // sub_64
6626	0, // sub_dsp16_19	6626	0, // sub_dsp16_19
6627	0, // sub_dsp20	6627	0, // sub_dsp20
6628	0, // sub_dsp21	6628	0, // sub_dsp21
6629	0, // sub_dsp22	6629	0, // sub_dsp22
6630	0, // sub_dsp23	6630	0, // sub_dsp23
6631	0, // sub_hi	6631	0, // sub_hi
6632	0, // sub_lo	6632	0, // sub_lo
6633	0, // sub_hi_then_sub_32	6633	0, // sub_hi_then_sub_32
6634	0, // sub_32_sub_hi_then_sub_32	6634	0, // sub_32_sub_hi_then_sub_32
6635	},	6635	},
6636	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	6636	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6637	53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst	6637	53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
6638	0, // sub_64	6638	0, // sub_64
6639	0, // sub_dsp16_19	6639	0, // sub_dsp16_19
6640	0, // sub_dsp20	6640	0, // sub_dsp20
6641	0, // sub_dsp21	6641	0, // sub_dsp21
6642	0, // sub_dsp22	6642	0, // sub_dsp22
6643	0, // sub_dsp23	6643	0, // sub_dsp23
6644	0, // sub_hi	6644	0, // sub_hi
6645	0, // sub_lo	6645	0, // sub_lo
6646	0, // sub_hi_then_sub_32	6646	0, // sub_hi_then_sub_32
6647	0, // sub_32_sub_hi_then_sub_32	6647	0, // sub_32_sub_hi_then_sub_32
6648	},	6648	},
6649	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	6649	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6650	54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	6650	54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
6651	0, // sub_64	6651	0, // sub_64
6652	0, // sub_dsp16_19	6652	0, // sub_dsp16_19
6653	0, // sub_dsp20	6653	0, // sub_dsp20
6654	0, // sub_dsp21	6654	0, // sub_dsp21
6655	0, // sub_dsp22	6655	0, // sub_dsp22
6656	0, // sub_dsp23	6656	0, // sub_dsp23
6657	0, // sub_hi	6657	0, // sub_hi
6658	0, // sub_lo	6658	0, // sub_lo
6659	0, // sub_hi_then_sub_32	6659	0, // sub_hi_then_sub_32
6660	0, // sub_32_sub_hi_then_sub_32	6660	0, // sub_32_sub_hi_then_sub_32
6661	},	6661	},
6662	{ // OCTEON_MPL	6662	{ // OCTEON_MPL
6663	0, // sub_32	6663	0, // sub_32
6664	0, // sub_64	6664	0, // sub_64
6665	0, // sub_dsp16_19	6665	0, // sub_dsp16_19
6666	0, // sub_dsp20	6666	0, // sub_dsp20
6667	0, // sub_dsp21	6667	0, // sub_dsp21
6668	0, // sub_dsp22	6668	0, // sub_dsp22
6669	0, // sub_dsp23	6669	0, // sub_dsp23
6670	0, // sub_hi	6670	0, // sub_hi
6671	0, // sub_lo	6671	0, // sub_lo
6672	0, // sub_hi_then_sub_32	6672	0, // sub_hi_then_sub_32
6673	0, // sub_32_sub_hi_then_sub_32	6673	0, // sub_32_sub_hi_then_sub_32
6674	},	6674	},
6675	{ // OCTEON_P	6675	{ // OCTEON_P
6676	0, // sub_32	6676	0, // sub_32
6677	0, // sub_64	6677	0, // sub_64
6678	0, // sub_dsp16_19	6678	0, // sub_dsp16_19
6679	0, // sub_dsp20	6679	0, // sub_dsp20
6680	0, // sub_dsp21	6680	0, // sub_dsp21
6681	0, // sub_dsp22	6681	0, // sub_dsp22
6682	0, // sub_dsp23	6682	0, // sub_dsp23
6683	0, // sub_hi	6683	0, // sub_hi
6684	0, // sub_lo	6684	0, // sub_lo
6685	0, // sub_hi_then_sub_32	6685	0, // sub_hi_then_sub_32
6686	0, // sub_32_sub_hi_then_sub_32	6686	0, // sub_32_sub_hi_then_sub_32
6687	},	6687	},
6688	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	6688	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6689	57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	6689	57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
6690	0, // sub_64	6690	0, // sub_64
6691	0, // sub_dsp16_19	6691	0, // sub_dsp16_19
6692	0, // sub_dsp20	6692	0, // sub_dsp20
6693	0, // sub_dsp21	6693	0, // sub_dsp21
6694	0, // sub_dsp22	6694	0, // sub_dsp22
6695	0, // sub_dsp23	6695	0, // sub_dsp23
6696	0, // sub_hi	6696	0, // sub_hi
6697	0, // sub_lo	6697	0, // sub_lo
6698	0, // sub_hi_then_sub_32	6698	0, // sub_hi_then_sub_32
6699	0, // sub_32_sub_hi_then_sub_32	6699	0, // sub_32_sub_hi_then_sub_32
6700	},	6700	},
6701	{ // ACC64	6701	{ // ACC64
6702	0, // sub_32	6702	0, // sub_32
6703	0, // sub_64	6703	0, // sub_64
6704	0, // sub_dsp16_19	6704	0, // sub_dsp16_19
6705	0, // sub_dsp20	6705	0, // sub_dsp20
6706	0, // sub_dsp21	6706	0, // sub_dsp21
6707	0, // sub_dsp22	6707	0, // sub_dsp22
6708	0, // sub_dsp23	6708	0, // sub_dsp23
6709	58, // sub_hi -> ACC64	6709	58, // sub_hi -> ACC64
6710	58, // sub_lo -> ACC64	6710	58, // sub_lo -> ACC64
6711	0, // sub_hi_then_sub_32	6711	0, // sub_hi_then_sub_32
6712	0, // sub_32_sub_hi_then_sub_32	6712	0, // sub_32_sub_hi_then_sub_32
6713	},	6713	},
6714	{ // GP64	6714	{ // GP64
6715	59, // sub_32 -> GP64	6715	59, // sub_32 -> GP64
6716	0, // sub_64	6716	0, // sub_64
6717	0, // sub_dsp16_19	6717	0, // sub_dsp16_19
6718	0, // sub_dsp20	6718	0, // sub_dsp20
6719	0, // sub_dsp21	6719	0, // sub_dsp21
6720	0, // sub_dsp22	6720	0, // sub_dsp22
6721	0, // sub_dsp23	6721	0, // sub_dsp23
6722	0, // sub_hi	6722	0, // sub_hi
6723	0, // sub_lo	6723	0, // sub_lo
6724	0, // sub_hi_then_sub_32	6724	0, // sub_hi_then_sub_32
6725	0, // sub_32_sub_hi_then_sub_32	6725	0, // sub_32_sub_hi_then_sub_32
6726	},	6726	},
6727	{ // GPR64_with_sub_32_in_CPURAReg	6727	{ // GPR64_with_sub_32_in_CPURAReg
6728	60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg	6728	60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
6729	0, // sub_64	6729	0, // sub_64
6730	0, // sub_dsp16_19	6730	0, // sub_dsp16_19
6731	0, // sub_dsp20	6731	0, // sub_dsp20
6732	0, // sub_dsp21	6732	0, // sub_dsp21
6733	0, // sub_dsp22	6733	0, // sub_dsp22
6734	0, // sub_dsp23	6734	0, // sub_dsp23
6735	0, // sub_hi	6735	0, // sub_hi
6736	0, // sub_lo	6736	0, // sub_lo
6737	0, // sub_hi_then_sub_32	6737	0, // sub_hi_then_sub_32
6738	0, // sub_32_sub_hi_then_sub_32	6738	0, // sub_32_sub_hi_then_sub_32
6739	},	6739	},
6740	{ // GPR64_with_sub_32_in_GPR32ZERO	6740	{ // GPR64_with_sub_32_in_GPR32ZERO
6741	61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO	6741	61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
6742	0, // sub_64	6742	0, // sub_64
6743	0, // sub_dsp16_19	6743	0, // sub_dsp16_19
6744	0, // sub_dsp20	6744	0, // sub_dsp20
6745	0, // sub_dsp21	6745	0, // sub_dsp21
6746	0, // sub_dsp22	6746	0, // sub_dsp22
6747	0, // sub_dsp23	6747	0, // sub_dsp23
6748	0, // sub_hi	6748	0, // sub_hi
6749	0, // sub_lo	6749	0, // sub_lo
6750	0, // sub_hi_then_sub_32	6750	0, // sub_hi_then_sub_32
6751	0, // sub_32_sub_hi_then_sub_32	6751	0, // sub_32_sub_hi_then_sub_32
6752	},	6752	},
6753	{ // HI64	6753	{ // HI64
6754	62, // sub_32 -> HI64	6754	62, // sub_32 -> HI64
6755	0, // sub_64	6755	0, // sub_64
6756	0, // sub_dsp16_19	6756	0, // sub_dsp16_19
6757	0, // sub_dsp20	6757	0, // sub_dsp20
6758	0, // sub_dsp21	6758	0, // sub_dsp21
6759	0, // sub_dsp22	6759	0, // sub_dsp22
6760	0, // sub_dsp23	6760	0, // sub_dsp23
6761	0, // sub_hi	6761	0, // sub_hi
6762	0, // sub_lo	6762	0, // sub_lo
6763	0, // sub_hi_then_sub_32	6763	0, // sub_hi_then_sub_32
6764	0, // sub_32_sub_hi_then_sub_32	6764	0, // sub_32_sub_hi_then_sub_32
6765	},	6765	},
6766	{ // LO64	6766	{ // LO64
6767	63, // sub_32 -> LO64	6767	63, // sub_32 -> LO64
6768	0, // sub_64	6768	0, // sub_64
6769	0, // sub_dsp16_19	6769	0, // sub_dsp16_19
6770	0, // sub_dsp20	6770	0, // sub_dsp20
6771	0, // sub_dsp21	6771	0, // sub_dsp21
6772	0, // sub_dsp22	6772	0, // sub_dsp22
6773	0, // sub_dsp23	6773	0, // sub_dsp23
6774	0, // sub_hi	6774	0, // sub_hi
6775	0, // sub_lo	6775	0, // sub_lo
6776	0, // sub_hi_then_sub_32	6776	0, // sub_hi_then_sub_32
6777	0, // sub_32_sub_hi_then_sub_32	6777	0, // sub_32_sub_hi_then_sub_32
6778	},	6778	},
6779	{ // SP64	6779	{ // SP64
6780	64, // sub_32 -> SP64	6780	64, // sub_32 -> SP64
6781	0, // sub_64	6781	0, // sub_64
6782	0, // sub_dsp16_19	6782	0, // sub_dsp16_19
6783	0, // sub_dsp20	6783	0, // sub_dsp20
6784	0, // sub_dsp21	6784	0, // sub_dsp21
6785	0, // sub_dsp22	6785	0, // sub_dsp22
6786	0, // sub_dsp23	6786	0, // sub_dsp23
6787	0, // sub_hi	6787	0, // sub_hi
6788	0, // sub_lo	6788	0, // sub_lo
6789	0, // sub_hi_then_sub_32	6789	0, // sub_hi_then_sub_32
6790	0, // sub_32_sub_hi_then_sub_32	6790	0, // sub_32_sub_hi_then_sub_32
6791	},	6791	},
6792	{ // MSA128B	6792	{ // MSA128B
6793	0, // sub_32	6793	0, // sub_32
6794	65, // sub_64 -> MSA128B	6794	65, // sub_64 -> MSA128B
6795	0, // sub_dsp16_19	6795	0, // sub_dsp16_19
6796	0, // sub_dsp20	6796	0, // sub_dsp20
6797	0, // sub_dsp21	6797	0, // sub_dsp21
6798	0, // sub_dsp22	6798	0, // sub_dsp22
6799	0, // sub_dsp23	6799	0, // sub_dsp23
6800	65, // sub_hi -> MSA128B	6800	65, // sub_hi -> MSA128B
6801	65, // sub_lo -> MSA128B	6801	65, // sub_lo -> MSA128B
6802	0, // sub_hi_then_sub_32	6802	0, // sub_hi_then_sub_32
6803	0, // sub_32_sub_hi_then_sub_32	6803	0, // sub_32_sub_hi_then_sub_32
6804	},	6804	},
6805	{ // MSA128D	6805	{ // MSA128D
6806	0, // sub_32	6806	0, // sub_32
6807	66, // sub_64 -> MSA128D	6807	66, // sub_64 -> MSA128D
6808	0, // sub_dsp16_19	6808	0, // sub_dsp16_19
6809	0, // sub_dsp20	6809	0, // sub_dsp20
6810	0, // sub_dsp21	6810	0, // sub_dsp21
6811	0, // sub_dsp22	6811	0, // sub_dsp22
6812	0, // sub_dsp23	6812	0, // sub_dsp23
6813	66, // sub_hi -> MSA128D	6813	66, // sub_hi -> MSA128D
6814	66, // sub_lo -> MSA128D	6814	66, // sub_lo -> MSA128D
6815	0, // sub_hi_then_sub_32	6815	0, // sub_hi_then_sub_32
6816	0, // sub_32_sub_hi_then_sub_32	6816	0, // sub_32_sub_hi_then_sub_32
6817	},	6817	},
6818	{ // MSA128H	6818	{ // MSA128H
6819	0, // sub_32	6819	0, // sub_32
6820	67, // sub_64 -> MSA128H	6820	67, // sub_64 -> MSA128H
6821	0, // sub_dsp16_19	6821	0, // sub_dsp16_19
6822	0, // sub_dsp20	6822	0, // sub_dsp20
6823	0, // sub_dsp21	6823	0, // sub_dsp21
6824	0, // sub_dsp22	6824	0, // sub_dsp22
6825	0, // sub_dsp23	6825	0, // sub_dsp23
6826	67, // sub_hi -> MSA128H	6826	67, // sub_hi -> MSA128H
6827	67, // sub_lo -> MSA128H	6827	67, // sub_lo -> MSA128H
6828	0, // sub_hi_then_sub_32	6828	0, // sub_hi_then_sub_32
6829	0, // sub_32_sub_hi_then_sub_32	6829	0, // sub_32_sub_hi_then_sub_32
6830	},	6830	},
6831	{ // MSA128W	6831	{ // MSA128W
6832	0, // sub_32	6832	0, // sub_32
6833	68, // sub_64 -> MSA128W	6833	68, // sub_64 -> MSA128W
6834	0, // sub_dsp16_19	6834	0, // sub_dsp16_19
6835	0, // sub_dsp20	6835	0, // sub_dsp20
6836	0, // sub_dsp21	6836	0, // sub_dsp21
6837	0, // sub_dsp22	6837	0, // sub_dsp22
6838	0, // sub_dsp23	6838	0, // sub_dsp23
6839	68, // sub_hi -> MSA128W	6839	68, // sub_hi -> MSA128W
6840	68, // sub_lo -> MSA128W	6840	68, // sub_lo -> MSA128W
6841	0, // sub_hi_then_sub_32	6841	0, // sub_hi_then_sub_32
6842	0, // sub_32_sub_hi_then_sub_32	6842	0, // sub_32_sub_hi_then_sub_32
6843	},	6843	},
6844	{ // MSA128WEvens	6844	{ // MSA128WEvens
6845	0, // sub_32	6845	0, // sub_32
6846	69, // sub_64 -> MSA128WEvens	6846	69, // sub_64 -> MSA128WEvens
6847	0, // sub_dsp16_19	6847	0, // sub_dsp16_19
6848	0, // sub_dsp20	6848	0, // sub_dsp20
6849	0, // sub_dsp21	6849	0, // sub_dsp21
6850	0, // sub_dsp22	6850	0, // sub_dsp22
6851	0, // sub_dsp23	6851	0, // sub_dsp23
6852	69, // sub_hi -> MSA128WEvens	6852	69, // sub_hi -> MSA128WEvens
6853	69, // sub_lo -> MSA128WEvens	6853	69, // sub_lo -> MSA128WEvens
6854	0, // sub_hi_then_sub_32	6854	0, // sub_hi_then_sub_32
6855	0, // sub_32_sub_hi_then_sub_32	6855	0, // sub_32_sub_hi_then_sub_32
6856	},	6856	},
6857	{ // ACC128	6857	{ // ACC128
6858	70, // sub_32 -> ACC128	6858	70, // sub_32 -> ACC128
6859	0, // sub_64	6859	0, // sub_64
6860	0, // sub_dsp16_19	6860	0, // sub_dsp16_19
6861	0, // sub_dsp20	6861	0, // sub_dsp20
6862	0, // sub_dsp21	6862	0, // sub_dsp21
6863	0, // sub_dsp22	6863	0, // sub_dsp22
6864	0, // sub_dsp23	6864	0, // sub_dsp23
6865	70, // sub_hi -> ACC128	6865	70, // sub_hi -> ACC128
6866	70, // sub_lo -> ACC128	6866	70, // sub_lo -> ACC128
6867	70, // sub_hi_then_sub_32 -> ACC128	6867	70, // sub_hi_then_sub_32 -> ACC128
6868	70, // sub_32_sub_hi_then_sub_32 -> ACC128	6868	70, // sub_32_sub_hi_then_sub_32 -> ACC128
6869	},	6869	},
6870	};	6870	};
6871	assert(RC && "Missing regclass");	6871	assert(RC && "Missing regclass");
6872	if (!Idx) return RC;	6872	if (!Idx) return RC;
6873	--Idx;	6873	--Idx;
6874	assert(Idx < 11 && "Bad subreg");	6874	assert(Idx < 11 && "Bad subreg");
6875	unsigned TV = Table[RC->getID()][Idx];	6875	unsigned TV = Table[RC->getID()][Idx];
6876	return TV ? getRegClass(TV - 1) : nullptr;	6876	return TV ? getRegClass(TV - 1) : nullptr;
6877	}	6877	}
6878		6878
6879	const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {	6879	const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {
6880	static const uint8_t Table[70][11] = {	6880	static const uint8_t Table[70][11] = {
6881	{ // MSA128F16	6881	{ // MSA128F16
6882	0, // MSA128F16:sub_32	6882	0, // MSA128F16:sub_32
6883	38, // MSA128F16:sub_64 -> FGR64	6883	38, // MSA128F16:sub_64 -> FGR64
6884	0, // MSA128F16:sub_dsp16_19	6884	0, // MSA128F16:sub_dsp16_19
6885	0, // MSA128F16:sub_dsp20	6885	0, // MSA128F16:sub_dsp20
6886	0, // MSA128F16:sub_dsp21	6886	0, // MSA128F16:sub_dsp21
6887	0, // MSA128F16:sub_dsp22	6887	0, // MSA128F16:sub_dsp22
6888	0, // MSA128F16:sub_dsp23	6888	0, // MSA128F16:sub_dsp23
6889	0, // MSA128F16:sub_hi	6889	0, // MSA128F16:sub_hi
6890	7, // MSA128F16:sub_lo -> FGR32	6890	7, // MSA128F16:sub_lo -> FGR32
6891	0, // MSA128F16:sub_hi_then_sub_32	6891	0, // MSA128F16:sub_hi_then_sub_32
6892	0, // MSA128F16:sub_32_sub_hi_then_sub_32	6892	0, // MSA128F16:sub_32_sub_hi_then_sub_32
6893	},	6893	},
6894	{ // CCR	6894	{ // CCR
6895	0, // CCR:sub_32	6895	0, // CCR:sub_32
6896	0, // CCR:sub_64	6896	0, // CCR:sub_64
6897	0, // CCR:sub_dsp16_19	6897	0, // CCR:sub_dsp16_19
6898	0, // CCR:sub_dsp20	6898	0, // CCR:sub_dsp20
6899	0, // CCR:sub_dsp21	6899	0, // CCR:sub_dsp21
6900	0, // CCR:sub_dsp22	6900	0, // CCR:sub_dsp22
6901	0, // CCR:sub_dsp23	6901	0, // CCR:sub_dsp23
6902	0, // CCR:sub_hi	6902	0, // CCR:sub_hi
6903	0, // CCR:sub_lo	6903	0, // CCR:sub_lo
6904	0, // CCR:sub_hi_then_sub_32	6904	0, // CCR:sub_hi_then_sub_32
6905	0, // CCR:sub_32_sub_hi_then_sub_32	6905	0, // CCR:sub_32_sub_hi_then_sub_32
6906	},	6906	},
6907	{ // COP0	6907	{ // COP0
6908	0, // COP0:sub_32	6908	0, // COP0:sub_32
6909	0, // COP0:sub_64	6909	0, // COP0:sub_64
6910	0, // COP0:sub_dsp16_19	6910	0, // COP0:sub_dsp16_19
6911	0, // COP0:sub_dsp20	6911	0, // COP0:sub_dsp20
6912	0, // COP0:sub_dsp21	6912	0, // COP0:sub_dsp21
6913	0, // COP0:sub_dsp22	6913	0, // COP0:sub_dsp22
6914	0, // COP0:sub_dsp23	6914	0, // COP0:sub_dsp23
6915	0, // COP0:sub_hi	6915	0, // COP0:sub_hi
6916	0, // COP0:sub_lo	6916	0, // COP0:sub_lo
6917	0, // COP0:sub_hi_then_sub_32	6917	0, // COP0:sub_hi_then_sub_32
6918	0, // COP0:sub_32_sub_hi_then_sub_32	6918	0, // COP0:sub_32_sub_hi_then_sub_32
6919	},	6919	},
6920	{ // COP2	6920	{ // COP2
6921	0, // COP2:sub_32	6921	0, // COP2:sub_32
6922	0, // COP2:sub_64	6922	0, // COP2:sub_64
6923	0, // COP2:sub_dsp16_19	6923	0, // COP2:sub_dsp16_19
6924	0, // COP2:sub_dsp20	6924	0, // COP2:sub_dsp20
6925	0, // COP2:sub_dsp21	6925	0, // COP2:sub_dsp21
6926	0, // COP2:sub_dsp22	6926	0, // COP2:sub_dsp22
6927	0, // COP2:sub_dsp23	6927	0, // COP2:sub_dsp23
6928	0, // COP2:sub_hi	6928	0, // COP2:sub_hi
6929	0, // COP2:sub_lo	6929	0, // COP2:sub_lo
6930	0, // COP2:sub_hi_then_sub_32	6930	0, // COP2:sub_hi_then_sub_32
6931	0, // COP2:sub_32_sub_hi_then_sub_32	6931	0, // COP2:sub_32_sub_hi_then_sub_32
6932	},	6932	},
6933	{ // COP3	6933	{ // COP3
6934	0, // COP3:sub_32	6934	0, // COP3:sub_32
6935	0, // COP3:sub_64	6935	0, // COP3:sub_64
6936	0, // COP3:sub_dsp16_19	6936	0, // COP3:sub_dsp16_19
6937	0, // COP3:sub_dsp20	6937	0, // COP3:sub_dsp20
6938	0, // COP3:sub_dsp21	6938	0, // COP3:sub_dsp21
6939	0, // COP3:sub_dsp22	6939	0, // COP3:sub_dsp22
6940	0, // COP3:sub_dsp23	6940	0, // COP3:sub_dsp23
6941	0, // COP3:sub_hi	6941	0, // COP3:sub_hi
6942	0, // COP3:sub_lo	6942	0, // COP3:sub_lo
6943	0, // COP3:sub_hi_then_sub_32	6943	0, // COP3:sub_hi_then_sub_32
6944	0, // COP3:sub_32_sub_hi_then_sub_32	6944	0, // COP3:sub_32_sub_hi_then_sub_32
6945	},	6945	},
6946	{ // DSPR	6946	{ // DSPR
6947	0, // DSPR:sub_32	6947	0, // DSPR:sub_32
6948	0, // DSPR:sub_64	6948	0, // DSPR:sub_64
6949	0, // DSPR:sub_dsp16_19	6949	0, // DSPR:sub_dsp16_19
6950	0, // DSPR:sub_dsp20	6950	0, // DSPR:sub_dsp20
6951	0, // DSPR:sub_dsp21	6951	0, // DSPR:sub_dsp21
6952	0, // DSPR:sub_dsp22	6952	0, // DSPR:sub_dsp22
6953	0, // DSPR:sub_dsp23	6953	0, // DSPR:sub_dsp23
6954	0, // DSPR:sub_hi	6954	0, // DSPR:sub_hi
6955	0, // DSPR:sub_lo	6955	0, // DSPR:sub_lo
6956	0, // DSPR:sub_hi_then_sub_32	6956	0, // DSPR:sub_hi_then_sub_32
6957	0, // DSPR:sub_32_sub_hi_then_sub_32	6957	0, // DSPR:sub_32_sub_hi_then_sub_32
6958	},	6958	},
6959	{ // FGR32	6959	{ // FGR32
6960	0, // FGR32:sub_32	6960	0, // FGR32:sub_32
6961	0, // FGR32:sub_64	6961	0, // FGR32:sub_64
6962	0, // FGR32:sub_dsp16_19	6962	0, // FGR32:sub_dsp16_19
6963	0, // FGR32:sub_dsp20	6963	0, // FGR32:sub_dsp20
6964	0, // FGR32:sub_dsp21	6964	0, // FGR32:sub_dsp21
6965	0, // FGR32:sub_dsp22	6965	0, // FGR32:sub_dsp22
6966	0, // FGR32:sub_dsp23	6966	0, // FGR32:sub_dsp23
6967	0, // FGR32:sub_hi	6967	0, // FGR32:sub_hi
6968	0, // FGR32:sub_lo	6968	0, // FGR32:sub_lo
6969	0, // FGR32:sub_hi_then_sub_32	6969	0, // FGR32:sub_hi_then_sub_32
6970	0, // FGR32:sub_32_sub_hi_then_sub_32	6970	0, // FGR32:sub_32_sub_hi_then_sub_32
6971	},	6971	},
6972	{ // FGRCC	6972	{ // FGRCC
6973	0, // FGRCC:sub_32	6973	0, // FGRCC:sub_32
6974	0, // FGRCC:sub_64	6974	0, // FGRCC:sub_64
6975	0, // FGRCC:sub_dsp16_19	6975	0, // FGRCC:sub_dsp16_19
6976	0, // FGRCC:sub_dsp20	6976	0, // FGRCC:sub_dsp20
6977	0, // FGRCC:sub_dsp21	6977	0, // FGRCC:sub_dsp21
6978	0, // FGRCC:sub_dsp22	6978	0, // FGRCC:sub_dsp22
6979	0, // FGRCC:sub_dsp23	6979	0, // FGRCC:sub_dsp23
6980	0, // FGRCC:sub_hi	6980	0, // FGRCC:sub_hi
6981	0, // FGRCC:sub_lo	6981	0, // FGRCC:sub_lo
6982	0, // FGRCC:sub_hi_then_sub_32	6982	0, // FGRCC:sub_hi_then_sub_32
6983	0, // FGRCC:sub_32_sub_hi_then_sub_32	6983	0, // FGRCC:sub_32_sub_hi_then_sub_32
6984	},	6984	},
6985	{ // GPR32	6985	{ // GPR32
6986	0, // GPR32:sub_32	6986	0, // GPR32:sub_32
6987	0, // GPR32:sub_64	6987	0, // GPR32:sub_64
6988	0, // GPR32:sub_dsp16_19	6988	0, // GPR32:sub_dsp16_19
6989	0, // GPR32:sub_dsp20	6989	0, // GPR32:sub_dsp20
6990	0, // GPR32:sub_dsp21	6990	0, // GPR32:sub_dsp21
6991	0, // GPR32:sub_dsp22	6991	0, // GPR32:sub_dsp22
6992	0, // GPR32:sub_dsp23	6992	0, // GPR32:sub_dsp23
6993	0, // GPR32:sub_hi	6993	0, // GPR32:sub_hi
6994	0, // GPR32:sub_lo	6994	0, // GPR32:sub_lo
6995	0, // GPR32:sub_hi_then_sub_32	6995	0, // GPR32:sub_hi_then_sub_32
6996	0, // GPR32:sub_32_sub_hi_then_sub_32	6996	0, // GPR32:sub_32_sub_hi_then_sub_32
6997	},	6997	},
6998	{ // HWRegs	6998	{ // HWRegs
6999	0, // HWRegs:sub_32	6999	0, // HWRegs:sub_32
7000	0, // HWRegs:sub_64	7000	0, // HWRegs:sub_64
7001	0, // HWRegs:sub_dsp16_19	7001	0, // HWRegs:sub_dsp16_19
7002	0, // HWRegs:sub_dsp20	7002	0, // HWRegs:sub_dsp20
7003	0, // HWRegs:sub_dsp21	7003	0, // HWRegs:sub_dsp21
7004	0, // HWRegs:sub_dsp22	7004	0, // HWRegs:sub_dsp22
7005	0, // HWRegs:sub_dsp23	7005	0, // HWRegs:sub_dsp23
7006	0, // HWRegs:sub_hi	7006	0, // HWRegs:sub_hi
7007	0, // HWRegs:sub_lo	7007	0, // HWRegs:sub_lo
7008	0, // HWRegs:sub_hi_then_sub_32	7008	0, // HWRegs:sub_hi_then_sub_32
7009	0, // HWRegs:sub_32_sub_hi_then_sub_32	7009	0, // HWRegs:sub_32_sub_hi_then_sub_32
7010	},	7010	},
7011	{ // MSACtrl	7011	{ // MSACtrl
7012	0, // MSACtrl:sub_32	7012	0, // MSACtrl:sub_32
7013	0, // MSACtrl:sub_64	7013	0, // MSACtrl:sub_64
7014	0, // MSACtrl:sub_dsp16_19	7014	0, // MSACtrl:sub_dsp16_19
7015	0, // MSACtrl:sub_dsp20	7015	0, // MSACtrl:sub_dsp20
7016	0, // MSACtrl:sub_dsp21	7016	0, // MSACtrl:sub_dsp21
7017	0, // MSACtrl:sub_dsp22	7017	0, // MSACtrl:sub_dsp22
7018	0, // MSACtrl:sub_dsp23	7018	0, // MSACtrl:sub_dsp23
7019	0, // MSACtrl:sub_hi	7019	0, // MSACtrl:sub_hi
7020	0, // MSACtrl:sub_lo	7020	0, // MSACtrl:sub_lo
7021	0, // MSACtrl:sub_hi_then_sub_32	7021	0, // MSACtrl:sub_hi_then_sub_32
7022	0, // MSACtrl:sub_32_sub_hi_then_sub_32	7022	0, // MSACtrl:sub_32_sub_hi_then_sub_32
7023	},	7023	},
7024	{ // GPR32NONZERO	7024	{ // GPR32NONZERO
7025	0, // GPR32NONZERO:sub_32	7025	0, // GPR32NONZERO:sub_32
7026	0, // GPR32NONZERO:sub_64	7026	0, // GPR32NONZERO:sub_64
7027	0, // GPR32NONZERO:sub_dsp16_19	7027	0, // GPR32NONZERO:sub_dsp16_19
7028	0, // GPR32NONZERO:sub_dsp20	7028	0, // GPR32NONZERO:sub_dsp20
7029	0, // GPR32NONZERO:sub_dsp21	7029	0, // GPR32NONZERO:sub_dsp21
7030	0, // GPR32NONZERO:sub_dsp22	7030	0, // GPR32NONZERO:sub_dsp22
7031	0, // GPR32NONZERO:sub_dsp23	7031	0, // GPR32NONZERO:sub_dsp23
7032	0, // GPR32NONZERO:sub_hi	7032	0, // GPR32NONZERO:sub_hi
7033	0, // GPR32NONZERO:sub_lo	7033	0, // GPR32NONZERO:sub_lo
7034	0, // GPR32NONZERO:sub_hi_then_sub_32	7034	0, // GPR32NONZERO:sub_hi_then_sub_32
7035	0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32	7035	0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32
7036	},	7036	},
7037	{ // CPU16RegsPlusSP	7037	{ // CPU16RegsPlusSP
7038	0, // CPU16RegsPlusSP:sub_32	7038	0, // CPU16RegsPlusSP:sub_32
7039	0, // CPU16RegsPlusSP:sub_64	7039	0, // CPU16RegsPlusSP:sub_64
7040	0, // CPU16RegsPlusSP:sub_dsp16_19	7040	0, // CPU16RegsPlusSP:sub_dsp16_19
7041	0, // CPU16RegsPlusSP:sub_dsp20	7041	0, // CPU16RegsPlusSP:sub_dsp20
7042	0, // CPU16RegsPlusSP:sub_dsp21	7042	0, // CPU16RegsPlusSP:sub_dsp21
7043	0, // CPU16RegsPlusSP:sub_dsp22	7043	0, // CPU16RegsPlusSP:sub_dsp22
7044	0, // CPU16RegsPlusSP:sub_dsp23	7044	0, // CPU16RegsPlusSP:sub_dsp23
7045	0, // CPU16RegsPlusSP:sub_hi	7045	0, // CPU16RegsPlusSP:sub_hi
7046	0, // CPU16RegsPlusSP:sub_lo	7046	0, // CPU16RegsPlusSP:sub_lo
7047	0, // CPU16RegsPlusSP:sub_hi_then_sub_32	7047	0, // CPU16RegsPlusSP:sub_hi_then_sub_32
7048	0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	7048	0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7049	},	7049	},
7050	{ // CPU16Regs	7050	{ // CPU16Regs
7051	0, // CPU16Regs:sub_32	7051	0, // CPU16Regs:sub_32
7052	0, // CPU16Regs:sub_64	7052	0, // CPU16Regs:sub_64
7053	0, // CPU16Regs:sub_dsp16_19	7053	0, // CPU16Regs:sub_dsp16_19
7054	0, // CPU16Regs:sub_dsp20	7054	0, // CPU16Regs:sub_dsp20
7055	0, // CPU16Regs:sub_dsp21	7055	0, // CPU16Regs:sub_dsp21
7056	0, // CPU16Regs:sub_dsp22	7056	0, // CPU16Regs:sub_dsp22
7057	0, // CPU16Regs:sub_dsp23	7057	0, // CPU16Regs:sub_dsp23
7058	0, // CPU16Regs:sub_hi	7058	0, // CPU16Regs:sub_hi
7059	0, // CPU16Regs:sub_lo	7059	0, // CPU16Regs:sub_lo
7060	0, // CPU16Regs:sub_hi_then_sub_32	7060	0, // CPU16Regs:sub_hi_then_sub_32
7061	0, // CPU16Regs:sub_32_sub_hi_then_sub_32	7061	0, // CPU16Regs:sub_32_sub_hi_then_sub_32
7062	},	7062	},
7063	{ // FCC	7063	{ // FCC
7064	0, // FCC:sub_32	7064	0, // FCC:sub_32
7065	0, // FCC:sub_64	7065	0, // FCC:sub_64
7066	0, // FCC:sub_dsp16_19	7066	0, // FCC:sub_dsp16_19
7067	0, // FCC:sub_dsp20	7067	0, // FCC:sub_dsp20
7068	0, // FCC:sub_dsp21	7068	0, // FCC:sub_dsp21
7069	0, // FCC:sub_dsp22	7069	0, // FCC:sub_dsp22
7070	0, // FCC:sub_dsp23	7070	0, // FCC:sub_dsp23
7071	0, // FCC:sub_hi	7071	0, // FCC:sub_hi
7072	0, // FCC:sub_lo	7072	0, // FCC:sub_lo
7073	0, // FCC:sub_hi_then_sub_32	7073	0, // FCC:sub_hi_then_sub_32
7074	0, // FCC:sub_32_sub_hi_then_sub_32	7074	0, // FCC:sub_32_sub_hi_then_sub_32
7075	},	7075	},
7076	{ // GPRMM16	7076	{ // GPRMM16
7077	0, // GPRMM16:sub_32	7077	0, // GPRMM16:sub_32
7078	0, // GPRMM16:sub_64	7078	0, // GPRMM16:sub_64
7079	0, // GPRMM16:sub_dsp16_19	7079	0, // GPRMM16:sub_dsp16_19
7080	0, // GPRMM16:sub_dsp20	7080	0, // GPRMM16:sub_dsp20
7081	0, // GPRMM16:sub_dsp21	7081	0, // GPRMM16:sub_dsp21
7082	0, // GPRMM16:sub_dsp22	7082	0, // GPRMM16:sub_dsp22
7083	0, // GPRMM16:sub_dsp23	7083	0, // GPRMM16:sub_dsp23
7084	0, // GPRMM16:sub_hi	7084	0, // GPRMM16:sub_hi
7085	0, // GPRMM16:sub_lo	7085	0, // GPRMM16:sub_lo
7086	0, // GPRMM16:sub_hi_then_sub_32	7086	0, // GPRMM16:sub_hi_then_sub_32
7087	0, // GPRMM16:sub_32_sub_hi_then_sub_32	7087	0, // GPRMM16:sub_32_sub_hi_then_sub_32
7088	},	7088	},
7089	{ // GPRMM16MoveP	7089	{ // GPRMM16MoveP
7090	0, // GPRMM16MoveP:sub_32	7090	0, // GPRMM16MoveP:sub_32
7091	0, // GPRMM16MoveP:sub_64	7091	0, // GPRMM16MoveP:sub_64
7092	0, // GPRMM16MoveP:sub_dsp16_19	7092	0, // GPRMM16MoveP:sub_dsp16_19
7093	0, // GPRMM16MoveP:sub_dsp20	7093	0, // GPRMM16MoveP:sub_dsp20
7094	0, // GPRMM16MoveP:sub_dsp21	7094	0, // GPRMM16MoveP:sub_dsp21
7095	0, // GPRMM16MoveP:sub_dsp22	7095	0, // GPRMM16MoveP:sub_dsp22
7096	0, // GPRMM16MoveP:sub_dsp23	7096	0, // GPRMM16MoveP:sub_dsp23
7097	0, // GPRMM16MoveP:sub_hi	7097	0, // GPRMM16MoveP:sub_hi
7098	0, // GPRMM16MoveP:sub_lo	7098	0, // GPRMM16MoveP:sub_lo
7099	0, // GPRMM16MoveP:sub_hi_then_sub_32	7099	0, // GPRMM16MoveP:sub_hi_then_sub_32
7100	0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7100	0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7101	},	7101	},
7102	{ // GPRMM16Zero	7102	{ // GPRMM16Zero
7103	0, // GPRMM16Zero:sub_32	7103	0, // GPRMM16Zero:sub_32
7104	0, // GPRMM16Zero:sub_64	7104	0, // GPRMM16Zero:sub_64
7105	0, // GPRMM16Zero:sub_dsp16_19	7105	0, // GPRMM16Zero:sub_dsp16_19
7106	0, // GPRMM16Zero:sub_dsp20	7106	0, // GPRMM16Zero:sub_dsp20
7107	0, // GPRMM16Zero:sub_dsp21	7107	0, // GPRMM16Zero:sub_dsp21
7108	0, // GPRMM16Zero:sub_dsp22	7108	0, // GPRMM16Zero:sub_dsp22
7109	0, // GPRMM16Zero:sub_dsp23	7109	0, // GPRMM16Zero:sub_dsp23
7110	0, // GPRMM16Zero:sub_hi	7110	0, // GPRMM16Zero:sub_hi
7111	0, // GPRMM16Zero:sub_lo	7111	0, // GPRMM16Zero:sub_lo
7112	0, // GPRMM16Zero:sub_hi_then_sub_32	7112	0, // GPRMM16Zero:sub_hi_then_sub_32
7113	0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32	7113	0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32
7114	},	7114	},
7115	{ // CPU16Regs_and_GPRMM16Zero	7115	{ // CPU16Regs_and_GPRMM16Zero
7116	0, // CPU16Regs_and_GPRMM16Zero:sub_32	7116	0, // CPU16Regs_and_GPRMM16Zero:sub_32
7117	0, // CPU16Regs_and_GPRMM16Zero:sub_64	7117	0, // CPU16Regs_and_GPRMM16Zero:sub_64
7118	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	7118	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7119	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20	7119	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20
7120	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21	7120	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21
7121	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22	7121	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22
7122	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23	7122	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23
7123	0, // CPU16Regs_and_GPRMM16Zero:sub_hi	7123	0, // CPU16Regs_and_GPRMM16Zero:sub_hi
7124	0, // CPU16Regs_and_GPRMM16Zero:sub_lo	7124	0, // CPU16Regs_and_GPRMM16Zero:sub_lo
7125	0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	7125	0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7126	0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7126	0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7127	},	7127	},
7128	{ // GPR32NONZERO_and_GPRMM16MoveP	7128	{ // GPR32NONZERO_and_GPRMM16MoveP
7129	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32	7129	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32
7130	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64	7130	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64
7131	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	7131	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7132	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	7132	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7133	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	7133	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7134	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	7134	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7135	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	7135	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7136	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi	7136	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7137	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo	7137	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7138	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	7138	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7139	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7139	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7140	},	7140	},
7141	{ // GPRMM16MovePPairSecond	7141	{ // GPRMM16MovePPairSecond
7142	0, // GPRMM16MovePPairSecond:sub_32	7142	0, // GPRMM16MovePPairSecond:sub_32
7143	0, // GPRMM16MovePPairSecond:sub_64	7143	0, // GPRMM16MovePPairSecond:sub_64
7144	0, // GPRMM16MovePPairSecond:sub_dsp16_19	7144	0, // GPRMM16MovePPairSecond:sub_dsp16_19
7145	0, // GPRMM16MovePPairSecond:sub_dsp20	7145	0, // GPRMM16MovePPairSecond:sub_dsp20
7146	0, // GPRMM16MovePPairSecond:sub_dsp21	7146	0, // GPRMM16MovePPairSecond:sub_dsp21
7147	0, // GPRMM16MovePPairSecond:sub_dsp22	7147	0, // GPRMM16MovePPairSecond:sub_dsp22
7148	0, // GPRMM16MovePPairSecond:sub_dsp23	7148	0, // GPRMM16MovePPairSecond:sub_dsp23
7149	0, // GPRMM16MovePPairSecond:sub_hi	7149	0, // GPRMM16MovePPairSecond:sub_hi
7150	0, // GPRMM16MovePPairSecond:sub_lo	7150	0, // GPRMM16MovePPairSecond:sub_lo
7151	0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32	7151	0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32
7152	0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7152	0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7153	},	7153	},
7154	{ // CPU16Regs_and_GPRMM16MoveP	7154	{ // CPU16Regs_and_GPRMM16MoveP
7155	0, // CPU16Regs_and_GPRMM16MoveP:sub_32	7155	0, // CPU16Regs_and_GPRMM16MoveP:sub_32
7156	0, // CPU16Regs_and_GPRMM16MoveP:sub_64	7156	0, // CPU16Regs_and_GPRMM16MoveP:sub_64
7157	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	7157	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7158	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20	7158	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7159	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21	7159	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7160	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22	7160	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7161	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23	7161	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7162	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi	7162	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi
7163	0, // CPU16Regs_and_GPRMM16MoveP:sub_lo	7163	0, // CPU16Regs_and_GPRMM16MoveP:sub_lo
7164	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	7164	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7165	0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7165	0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7166	},	7166	},
7167	{ // GPRMM16MoveP_and_GPRMM16Zero	7167	{ // GPRMM16MoveP_and_GPRMM16Zero
7168	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32	7168	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32
7169	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64	7169	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64
7170	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	7170	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7171	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	7171	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7172	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	7172	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7173	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	7173	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7174	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	7174	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7175	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi	7175	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7176	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo	7176	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7177	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	7177	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7178	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7178	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7179	},	7179	},
7180	{ // HI32DSP	7180	{ // HI32DSP
7181	0, // HI32DSP:sub_32	7181	0, // HI32DSP:sub_32
7182	0, // HI32DSP:sub_64	7182	0, // HI32DSP:sub_64
7183	0, // HI32DSP:sub_dsp16_19	7183	0, // HI32DSP:sub_dsp16_19
7184	0, // HI32DSP:sub_dsp20	7184	0, // HI32DSP:sub_dsp20
7185	0, // HI32DSP:sub_dsp21	7185	0, // HI32DSP:sub_dsp21
7186	0, // HI32DSP:sub_dsp22	7186	0, // HI32DSP:sub_dsp22
7187	0, // HI32DSP:sub_dsp23	7187	0, // HI32DSP:sub_dsp23
7188	0, // HI32DSP:sub_hi	7188	0, // HI32DSP:sub_hi
7189	0, // HI32DSP:sub_lo	7189	0, // HI32DSP:sub_lo
7190	0, // HI32DSP:sub_hi_then_sub_32	7190	0, // HI32DSP:sub_hi_then_sub_32
7191	0, // HI32DSP:sub_32_sub_hi_then_sub_32	7191	0, // HI32DSP:sub_32_sub_hi_then_sub_32
7192	},	7192	},
7193	{ // LO32DSP	7193	{ // LO32DSP
7194	0, // LO32DSP:sub_32	7194	0, // LO32DSP:sub_32
7195	0, // LO32DSP:sub_64	7195	0, // LO32DSP:sub_64
7196	0, // LO32DSP:sub_dsp16_19	7196	0, // LO32DSP:sub_dsp16_19
7197	0, // LO32DSP:sub_dsp20	7197	0, // LO32DSP:sub_dsp20
7198	0, // LO32DSP:sub_dsp21	7198	0, // LO32DSP:sub_dsp21
7199	0, // LO32DSP:sub_dsp22	7199	0, // LO32DSP:sub_dsp22
7200	0, // LO32DSP:sub_dsp23	7200	0, // LO32DSP:sub_dsp23
7201	0, // LO32DSP:sub_hi	7201	0, // LO32DSP:sub_hi
7202	0, // LO32DSP:sub_lo	7202	0, // LO32DSP:sub_lo
7203	0, // LO32DSP:sub_hi_then_sub_32	7203	0, // LO32DSP:sub_hi_then_sub_32
7204	0, // LO32DSP:sub_32_sub_hi_then_sub_32	7204	0, // LO32DSP:sub_32_sub_hi_then_sub_32
7205	},	7205	},
7206	{ // CPU16Regs_and_GPRMM16MovePPairSecond	7206	{ // CPU16Regs_and_GPRMM16MovePPairSecond
7207	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32	7207	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
7208	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	7208	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7209	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	7209	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7210	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	7210	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7211	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	7211	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7212	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	7212	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7213	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	7213	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7214	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	7214	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7215	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	7215	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7216	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	7216	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7217	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7217	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7218	},	7218	},
7219	{ // GPRMM16MovePPairFirst	7219	{ // GPRMM16MovePPairFirst
7220	0, // GPRMM16MovePPairFirst:sub_32	7220	0, // GPRMM16MovePPairFirst:sub_32
7221	0, // GPRMM16MovePPairFirst:sub_64	7221	0, // GPRMM16MovePPairFirst:sub_64
7222	0, // GPRMM16MovePPairFirst:sub_dsp16_19	7222	0, // GPRMM16MovePPairFirst:sub_dsp16_19
7223	0, // GPRMM16MovePPairFirst:sub_dsp20	7223	0, // GPRMM16MovePPairFirst:sub_dsp20
7224	0, // GPRMM16MovePPairFirst:sub_dsp21	7224	0, // GPRMM16MovePPairFirst:sub_dsp21
7225	0, // GPRMM16MovePPairFirst:sub_dsp22	7225	0, // GPRMM16MovePPairFirst:sub_dsp22
7226	0, // GPRMM16MovePPairFirst:sub_dsp23	7226	0, // GPRMM16MovePPairFirst:sub_dsp23
7227	0, // GPRMM16MovePPairFirst:sub_hi	7227	0, // GPRMM16MovePPairFirst:sub_hi
7228	0, // GPRMM16MovePPairFirst:sub_lo	7228	0, // GPRMM16MovePPairFirst:sub_lo
7229	0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32	7229	0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32
7230	0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	7230	0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7231	},	7231	},
7232	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	7232	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7233	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32	7233	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
7234	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	7234	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7235	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	7235	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7236	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	7236	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7237	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	7237	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7238	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	7238	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7239	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	7239	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7240	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	7240	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7241	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	7241	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7242	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	7242	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7243	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7243	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7244	},	7244	},
7245	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	7245	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7246	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32	7246	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
7247	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	7247	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7248	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	7248	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7249	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	7249	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7250	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	7250	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7251	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	7251	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7252	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	7252	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7253	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	7253	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7254	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	7254	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7255	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	7255	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7256	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7256	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7257	},	7257	},
7258	{ // CPURAReg	7258	{ // CPURAReg
7259	0, // CPURAReg:sub_32	7259	0, // CPURAReg:sub_32
7260	0, // CPURAReg:sub_64	7260	0, // CPURAReg:sub_64
7261	0, // CPURAReg:sub_dsp16_19	7261	0, // CPURAReg:sub_dsp16_19
7262	0, // CPURAReg:sub_dsp20	7262	0, // CPURAReg:sub_dsp20
7263	0, // CPURAReg:sub_dsp21	7263	0, // CPURAReg:sub_dsp21
7264	0, // CPURAReg:sub_dsp22	7264	0, // CPURAReg:sub_dsp22
7265	0, // CPURAReg:sub_dsp23	7265	0, // CPURAReg:sub_dsp23
7266	0, // CPURAReg:sub_hi	7266	0, // CPURAReg:sub_hi
7267	0, // CPURAReg:sub_lo	7267	0, // CPURAReg:sub_lo
7268	0, // CPURAReg:sub_hi_then_sub_32	7268	0, // CPURAReg:sub_hi_then_sub_32
7269	0, // CPURAReg:sub_32_sub_hi_then_sub_32	7269	0, // CPURAReg:sub_32_sub_hi_then_sub_32
7270	},	7270	},
7271	{ // CPUSPReg	7271	{ // CPUSPReg
7272	0, // CPUSPReg:sub_32	7272	0, // CPUSPReg:sub_32
7273	0, // CPUSPReg:sub_64	7273	0, // CPUSPReg:sub_64
7274	0, // CPUSPReg:sub_dsp16_19	7274	0, // CPUSPReg:sub_dsp16_19
7275	0, // CPUSPReg:sub_dsp20	7275	0, // CPUSPReg:sub_dsp20
7276	0, // CPUSPReg:sub_dsp21	7276	0, // CPUSPReg:sub_dsp21
7277	0, // CPUSPReg:sub_dsp22	7277	0, // CPUSPReg:sub_dsp22
7278	0, // CPUSPReg:sub_dsp23	7278	0, // CPUSPReg:sub_dsp23
7279	0, // CPUSPReg:sub_hi	7279	0, // CPUSPReg:sub_hi
7280	0, // CPUSPReg:sub_lo	7280	0, // CPUSPReg:sub_lo
7281	0, // CPUSPReg:sub_hi_then_sub_32	7281	0, // CPUSPReg:sub_hi_then_sub_32
7282	0, // CPUSPReg:sub_32_sub_hi_then_sub_32	7282	0, // CPUSPReg:sub_32_sub_hi_then_sub_32
7283	},	7283	},
7284	{ // DSPCC	7284	{ // DSPCC
7285	0, // DSPCC:sub_32	7285	0, // DSPCC:sub_32
7286	0, // DSPCC:sub_64	7286	0, // DSPCC:sub_64
7287	0, // DSPCC:sub_dsp16_19	7287	0, // DSPCC:sub_dsp16_19
7288	0, // DSPCC:sub_dsp20	7288	0, // DSPCC:sub_dsp20
7289	0, // DSPCC:sub_dsp21	7289	0, // DSPCC:sub_dsp21
7290	0, // DSPCC:sub_dsp22	7290	0, // DSPCC:sub_dsp22
7291	0, // DSPCC:sub_dsp23	7291	0, // DSPCC:sub_dsp23
7292	0, // DSPCC:sub_hi	7292	0, // DSPCC:sub_hi
7293	0, // DSPCC:sub_lo	7293	0, // DSPCC:sub_lo
7294	0, // DSPCC:sub_hi_then_sub_32	7294	0, // DSPCC:sub_hi_then_sub_32
7295	0, // DSPCC:sub_32_sub_hi_then_sub_32	7295	0, // DSPCC:sub_32_sub_hi_then_sub_32
7296	},	7296	},
7297	{ // GP32	7297	{ // GP32
7298	0, // GP32:sub_32	7298	0, // GP32:sub_32
7299	0, // GP32:sub_64	7299	0, // GP32:sub_64
7300	0, // GP32:sub_dsp16_19	7300	0, // GP32:sub_dsp16_19
7301	0, // GP32:sub_dsp20	7301	0, // GP32:sub_dsp20
7302	0, // GP32:sub_dsp21	7302	0, // GP32:sub_dsp21
7303	0, // GP32:sub_dsp22	7303	0, // GP32:sub_dsp22
7304	0, // GP32:sub_dsp23	7304	0, // GP32:sub_dsp23
7305	0, // GP32:sub_hi	7305	0, // GP32:sub_hi
7306	0, // GP32:sub_lo	7306	0, // GP32:sub_lo
7307	0, // GP32:sub_hi_then_sub_32	7307	0, // GP32:sub_hi_then_sub_32
7308	0, // GP32:sub_32_sub_hi_then_sub_32	7308	0, // GP32:sub_32_sub_hi_then_sub_32
7309	},	7309	},
7310	{ // GPR32ZERO	7310	{ // GPR32ZERO
7311	0, // GPR32ZERO:sub_32	7311	0, // GPR32ZERO:sub_32
7312	0, // GPR32ZERO:sub_64	7312	0, // GPR32ZERO:sub_64
7313	0, // GPR32ZERO:sub_dsp16_19	7313	0, // GPR32ZERO:sub_dsp16_19
7314	0, // GPR32ZERO:sub_dsp20	7314	0, // GPR32ZERO:sub_dsp20
7315	0, // GPR32ZERO:sub_dsp21	7315	0, // GPR32ZERO:sub_dsp21
7316	0, // GPR32ZERO:sub_dsp22	7316	0, // GPR32ZERO:sub_dsp22
7317	0, // GPR32ZERO:sub_dsp23	7317	0, // GPR32ZERO:sub_dsp23
7318	0, // GPR32ZERO:sub_hi	7318	0, // GPR32ZERO:sub_hi
7319	0, // GPR32ZERO:sub_lo	7319	0, // GPR32ZERO:sub_lo
7320	0, // GPR32ZERO:sub_hi_then_sub_32	7320	0, // GPR32ZERO:sub_hi_then_sub_32
7321	0, // GPR32ZERO:sub_32_sub_hi_then_sub_32	7321	0, // GPR32ZERO:sub_32_sub_hi_then_sub_32
7322	},	7322	},
7323	{ // HI32	7323	{ // HI32
7324	0, // HI32:sub_32	7324	0, // HI32:sub_32
7325	0, // HI32:sub_64	7325	0, // HI32:sub_64
7326	0, // HI32:sub_dsp16_19	7326	0, // HI32:sub_dsp16_19
7327	0, // HI32:sub_dsp20	7327	0, // HI32:sub_dsp20
7328	0, // HI32:sub_dsp21	7328	0, // HI32:sub_dsp21
7329	0, // HI32:sub_dsp22	7329	0, // HI32:sub_dsp22
7330	0, // HI32:sub_dsp23	7330	0, // HI32:sub_dsp23
7331	0, // HI32:sub_hi	7331	0, // HI32:sub_hi
7332	0, // HI32:sub_lo	7332	0, // HI32:sub_lo
7333	0, // HI32:sub_hi_then_sub_32	7333	0, // HI32:sub_hi_then_sub_32
7334	0, // HI32:sub_32_sub_hi_then_sub_32	7334	0, // HI32:sub_32_sub_hi_then_sub_32
7335	},	7335	},
7336	{ // LO32	7336	{ // LO32
7337	0, // LO32:sub_32	7337	0, // LO32:sub_32
7338	0, // LO32:sub_64	7338	0, // LO32:sub_64
7339	0, // LO32:sub_dsp16_19	7339	0, // LO32:sub_dsp16_19
7340	0, // LO32:sub_dsp20	7340	0, // LO32:sub_dsp20
7341	0, // LO32:sub_dsp21	7341	0, // LO32:sub_dsp21
7342	0, // LO32:sub_dsp22	7342	0, // LO32:sub_dsp22
7343	0, // LO32:sub_dsp23	7343	0, // LO32:sub_dsp23
7344	0, // LO32:sub_hi	7344	0, // LO32:sub_hi
7345	0, // LO32:sub_lo	7345	0, // LO32:sub_lo
7346	0, // LO32:sub_hi_then_sub_32	7346	0, // LO32:sub_hi_then_sub_32
7347	0, // LO32:sub_32_sub_hi_then_sub_32	7347	0, // LO32:sub_32_sub_hi_then_sub_32
7348	},	7348	},
7349	{ // SP32	7349	{ // SP32
7350	0, // SP32:sub_32	7350	0, // SP32:sub_32
7351	0, // SP32:sub_64	7351	0, // SP32:sub_64
7352	0, // SP32:sub_dsp16_19	7352	0, // SP32:sub_dsp16_19
7353	0, // SP32:sub_dsp20	7353	0, // SP32:sub_dsp20
7354	0, // SP32:sub_dsp21	7354	0, // SP32:sub_dsp21
7355	0, // SP32:sub_dsp22	7355	0, // SP32:sub_dsp22
7356	0, // SP32:sub_dsp23	7356	0, // SP32:sub_dsp23
7357	0, // SP32:sub_hi	7357	0, // SP32:sub_hi
7358	0, // SP32:sub_lo	7358	0, // SP32:sub_lo
7359	0, // SP32:sub_hi_then_sub_32	7359	0, // SP32:sub_hi_then_sub_32
7360	0, // SP32:sub_32_sub_hi_then_sub_32	7360	0, // SP32:sub_32_sub_hi_then_sub_32
7361	},	7361	},
7362	{ // FGR64	7362	{ // FGR64
7363	0, // FGR64:sub_32	7363	0, // FGR64:sub_32
7364	0, // FGR64:sub_64	7364	0, // FGR64:sub_64
7365	0, // FGR64:sub_dsp16_19	7365	0, // FGR64:sub_dsp16_19
7366	0, // FGR64:sub_dsp20	7366	0, // FGR64:sub_dsp20
7367	0, // FGR64:sub_dsp21	7367	0, // FGR64:sub_dsp21
7368	0, // FGR64:sub_dsp22	7368	0, // FGR64:sub_dsp22
7369	0, // FGR64:sub_dsp23	7369	0, // FGR64:sub_dsp23
7370	0, // FGR64:sub_hi	7370	0, // FGR64:sub_hi
7371	7, // FGR64:sub_lo -> FGR32	7371	7, // FGR64:sub_lo -> FGR32
7372	0, // FGR64:sub_hi_then_sub_32	7372	0, // FGR64:sub_hi_then_sub_32
7373	0, // FGR64:sub_32_sub_hi_then_sub_32	7373	0, // FGR64:sub_32_sub_hi_then_sub_32
7374	},	7374	},
7375	{ // GPR64	7375	{ // GPR64
7376	9, // GPR64:sub_32 -> GPR32	7376	9, // GPR64:sub_32 -> GPR32
7377	0, // GPR64:sub_64	7377	0, // GPR64:sub_64
7378	0, // GPR64:sub_dsp16_19	7378	0, // GPR64:sub_dsp16_19
7379	0, // GPR64:sub_dsp20	7379	0, // GPR64:sub_dsp20
7380	0, // GPR64:sub_dsp21	7380	0, // GPR64:sub_dsp21
7381	0, // GPR64:sub_dsp22	7381	0, // GPR64:sub_dsp22
7382	0, // GPR64:sub_dsp23	7382	0, // GPR64:sub_dsp23
7383	0, // GPR64:sub_hi	7383	0, // GPR64:sub_hi
7384	0, // GPR64:sub_lo	7384	0, // GPR64:sub_lo
7385	0, // GPR64:sub_hi_then_sub_32	7385	0, // GPR64:sub_hi_then_sub_32
7386	0, // GPR64:sub_32_sub_hi_then_sub_32	7386	0, // GPR64:sub_32_sub_hi_then_sub_32
7387	},	7387	},
7388	{ // GPR64_with_sub_32_in_GPR32NONZERO	7388	{ // GPR64_with_sub_32_in_GPR32NONZERO
7389	12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO	7389	12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
7390	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64	7390	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
7391	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19	7391	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
7392	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20	7392	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
7393	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21	7393	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
7394	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22	7394	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
7395	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23	7395	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
7396	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi	7396	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
7397	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo	7397	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
7398	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32	7398	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
7399	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32	7399	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
7400	},	7400	},
7401	{ // AFGR64	7401	{ // AFGR64
7402	0, // AFGR64:sub_32	7402	0, // AFGR64:sub_32
7403	0, // AFGR64:sub_64	7403	0, // AFGR64:sub_64
7404	0, // AFGR64:sub_dsp16_19	7404	0, // AFGR64:sub_dsp16_19
7405	0, // AFGR64:sub_dsp20	7405	0, // AFGR64:sub_dsp20
7406	0, // AFGR64:sub_dsp21	7406	0, // AFGR64:sub_dsp21
7407	0, // AFGR64:sub_dsp22	7407	0, // AFGR64:sub_dsp22
7408	0, // AFGR64:sub_dsp23	7408	0, // AFGR64:sub_dsp23
7409	8, // AFGR64:sub_hi -> FGRCC	7409	8, // AFGR64:sub_hi -> FGRCC
7410	8, // AFGR64:sub_lo -> FGRCC	7410	8, // AFGR64:sub_lo -> FGRCC
7411	0, // AFGR64:sub_hi_then_sub_32	7411	0, // AFGR64:sub_hi_then_sub_32
7412	0, // AFGR64:sub_32_sub_hi_then_sub_32	7412	0, // AFGR64:sub_32_sub_hi_then_sub_32
7413	},	7413	},
7414	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	7414	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP
7415	13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP	7415	13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
7416	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64	7416	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
7417	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19	7417	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
7418	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20	7418	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
7419	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21	7419	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
7420	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22	7420	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
7421	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23	7421	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
7422	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi	7422	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
7423	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo	7423	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
7424	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32	7424	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
7425	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	7425	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
7426	},	7426	},
7427	{ // GPR64_with_sub_32_in_CPU16Regs	7427	{ // GPR64_with_sub_32_in_CPU16Regs
7428	14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs	7428	14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
7429	0, // GPR64_with_sub_32_in_CPU16Regs:sub_64	7429	0, // GPR64_with_sub_32_in_CPU16Regs:sub_64
7430	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19	7430	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
7431	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20	7431	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
7432	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21	7432	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
7433	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22	7433	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
7434	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23	7434	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
7435	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi	7435	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi
7436	0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo	7436	0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo
7437	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32	7437	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
7438	0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32	7438	0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
7439	},	7439	},
7440	{ // GPR64_with_sub_32_in_GPRMM16MoveP	7440	{ // GPR64_with_sub_32_in_GPRMM16MoveP
7441	17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP	7441	17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
7442	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64	7442	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
7443	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19	7443	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
7444	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20	7444	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
7445	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21	7445	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
7446	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22	7446	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
7447	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23	7447	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
7448	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi	7448	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
7449	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo	7449	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
7450	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32	7450	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
7451	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7451	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7452	},	7452	},
7453	{ // GPR64_with_sub_32_in_GPRMM16Zero	7453	{ // GPR64_with_sub_32_in_GPRMM16Zero
7454	18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero	7454	18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
7455	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64	7455	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
7456	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19	7456	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
7457	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20	7457	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
7458	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21	7458	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
7459	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22	7459	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
7460	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23	7460	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
7461	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi	7461	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
7462	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo	7462	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
7463	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32	7463	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
7464	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7464	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7465	},	7465	},
7466	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	7466	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7467	19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero	7467	19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
7468	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64	7468	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
7469	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	7469	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7470	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20	7470	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7471	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21	7471	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7472	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22	7472	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7473	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23	7473	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7474	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi	7474	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
7475	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo	7475	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
7476	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	7476	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7477	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7477	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7478	},	7478	},
7479	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	7479	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7480	20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP	7480	20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
7481	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64	7481	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
7482	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	7482	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
7483	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	7483	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
7484	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	7484	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
7485	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	7485	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
7486	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	7486	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
7487	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi	7487	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
7488	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo	7488	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
7489	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	7489	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
7490	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7490	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7491	},	7491	},
7492	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	7492	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7493	21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond	7493	21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
7494	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64	7494	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
7495	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19	7495	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
7496	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20	7496	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
7497	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21	7497	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
7498	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22	7498	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
7499	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23	7499	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
7500	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi	7500	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
7501	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo	7501	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
7502	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32	7502	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7503	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7503	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7504	},	7504	},
7505	{ // ACC64DSP	7505	{ // ACC64DSP
7506	0, // ACC64DSP:sub_32	7506	0, // ACC64DSP:sub_32
7507	0, // ACC64DSP:sub_64	7507	0, // ACC64DSP:sub_64
7508	0, // ACC64DSP:sub_dsp16_19	7508	0, // ACC64DSP:sub_dsp16_19
7509	0, // ACC64DSP:sub_dsp20	7509	0, // ACC64DSP:sub_dsp20
7510	0, // ACC64DSP:sub_dsp21	7510	0, // ACC64DSP:sub_dsp21
7511	0, // ACC64DSP:sub_dsp22	7511	0, // ACC64DSP:sub_dsp22
7512	0, // ACC64DSP:sub_dsp23	7512	0, // ACC64DSP:sub_dsp23
7513	24, // ACC64DSP:sub_hi -> HI32DSP	7513	24, // ACC64DSP:sub_hi -> HI32DSP
7514	25, // ACC64DSP:sub_lo -> LO32DSP	7514	25, // ACC64DSP:sub_lo -> LO32DSP
7515	0, // ACC64DSP:sub_hi_then_sub_32	7515	0, // ACC64DSP:sub_hi_then_sub_32
7516	0, // ACC64DSP:sub_32_sub_hi_then_sub_32	7516	0, // ACC64DSP:sub_32_sub_hi_then_sub_32
7517	},	7517	},
7518	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	7518	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7519	22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP	7519	22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
7520	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64	7520	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
7521	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	7521	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
7522	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20	7522	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
7523	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21	7523	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
7524	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22	7524	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
7525	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23	7525	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
7526	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi	7526	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
7527	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo	7527	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
7528	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	7528	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
7529	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	7529	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
7530	},	7530	},
7531	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	7531	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7532	23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero	7532	23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
7533	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64	7533	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
7534	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	7534	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
7535	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	7535	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
7536	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	7536	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
7537	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	7537	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
7538	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	7538	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
7539	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi	7539	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
7540	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo	7540	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
7541	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	7541	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
7542	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7542	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7543	},	7543	},
7544	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	7544	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7545	26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond	7545	26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
7546	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	7546	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
7547	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	7547	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
7548	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	7548	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
7549	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	7549	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
7550	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	7550	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
7551	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	7551	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
7552	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	7552	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
7553	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	7553	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
7554	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	7554	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7555	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7555	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7556	},	7556	},
7557	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	7557	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7558	27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst	7558	27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
7559	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64	7559	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
7560	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19	7560	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
7561	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20	7561	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
7562	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21	7562	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
7563	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22	7563	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
7564	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23	7564	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
7565	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi	7565	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
7566	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo	7566	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
7567	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32	7567	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
7568	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	7568	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
7569	},	7569	},
7570	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	7570	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7571	28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	7571	28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7572	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	7572	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
7573	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	7573	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
7574	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	7574	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
7575	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	7575	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
7576	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	7576	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
7577	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	7577	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
7578	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	7578	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
7579	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	7579	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
7580	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	7580	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
7581	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	7581	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
7582	},	7582	},
7583	{ // OCTEON_MPL	7583	{ // OCTEON_MPL
7584	0, // OCTEON_MPL:sub_32	7584	0, // OCTEON_MPL:sub_32
7585	0, // OCTEON_MPL:sub_64	7585	0, // OCTEON_MPL:sub_64
7586	0, // OCTEON_MPL:sub_dsp16_19	7586	0, // OCTEON_MPL:sub_dsp16_19
7587	0, // OCTEON_MPL:sub_dsp20	7587	0, // OCTEON_MPL:sub_dsp20
7588	0, // OCTEON_MPL:sub_dsp21	7588	0, // OCTEON_MPL:sub_dsp21
7589	0, // OCTEON_MPL:sub_dsp22	7589	0, // OCTEON_MPL:sub_dsp22
7590	0, // OCTEON_MPL:sub_dsp23	7590	0, // OCTEON_MPL:sub_dsp23
7591	0, // OCTEON_MPL:sub_hi	7591	0, // OCTEON_MPL:sub_hi
7592	0, // OCTEON_MPL:sub_lo	7592	0, // OCTEON_MPL:sub_lo
7593	0, // OCTEON_MPL:sub_hi_then_sub_32	7593	0, // OCTEON_MPL:sub_hi_then_sub_32
7594	0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32	7594	0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32
7595	},	7595	},
7596	{ // OCTEON_P	7596	{ // OCTEON_P
7597	0, // OCTEON_P:sub_32	7597	0, // OCTEON_P:sub_32
7598	0, // OCTEON_P:sub_64	7598	0, // OCTEON_P:sub_64
7599	0, // OCTEON_P:sub_dsp16_19	7599	0, // OCTEON_P:sub_dsp16_19
7600	0, // OCTEON_P:sub_dsp20	7600	0, // OCTEON_P:sub_dsp20
7601	0, // OCTEON_P:sub_dsp21	7601	0, // OCTEON_P:sub_dsp21
7602	0, // OCTEON_P:sub_dsp22	7602	0, // OCTEON_P:sub_dsp22
7603	0, // OCTEON_P:sub_dsp23	7603	0, // OCTEON_P:sub_dsp23
7604	0, // OCTEON_P:sub_hi	7604	0, // OCTEON_P:sub_hi
7605	0, // OCTEON_P:sub_lo	7605	0, // OCTEON_P:sub_lo
7606	0, // OCTEON_P:sub_hi_then_sub_32	7606	0, // OCTEON_P:sub_hi_then_sub_32
7607	0, // OCTEON_P:sub_32_sub_hi_then_sub_32	7607	0, // OCTEON_P:sub_32_sub_hi_then_sub_32
7608	},	7608	},
7609	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	7609	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7610	29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	7610	29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7611	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	7611	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
7612	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	7612	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
7613	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	7613	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
7614	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	7614	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
7615	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	7615	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
7616	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	7616	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
7617	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	7617	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
7618	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	7618	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
7619	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	7619	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
7620	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	7620	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
7621	},	7621	},
7622	{ // ACC64	7622	{ // ACC64
7623	0, // ACC64:sub_32	7623	0, // ACC64:sub_32
7624	0, // ACC64:sub_64	7624	0, // ACC64:sub_64
7625	0, // ACC64:sub_dsp16_19	7625	0, // ACC64:sub_dsp16_19
7626	0, // ACC64:sub_dsp20	7626	0, // ACC64:sub_dsp20
7627	0, // ACC64:sub_dsp21	7627	0, // ACC64:sub_dsp21
7628	0, // ACC64:sub_dsp22	7628	0, // ACC64:sub_dsp22
7629	0, // ACC64:sub_dsp23	7629	0, // ACC64:sub_dsp23
7630	35, // ACC64:sub_hi -> HI32	7630	35, // ACC64:sub_hi -> HI32
7631	36, // ACC64:sub_lo -> LO32	7631	36, // ACC64:sub_lo -> LO32
7632	0, // ACC64:sub_hi_then_sub_32	7632	0, // ACC64:sub_hi_then_sub_32
7633	0, // ACC64:sub_32_sub_hi_then_sub_32	7633	0, // ACC64:sub_32_sub_hi_then_sub_32
7634	},	7634	},
7635	{ // GP64	7635	{ // GP64
7636	33, // GP64:sub_32 -> GP32	7636	33, // GP64:sub_32 -> GP32
7637	0, // GP64:sub_64	7637	0, // GP64:sub_64
7638	0, // GP64:sub_dsp16_19	7638	0, // GP64:sub_dsp16_19
7639	0, // GP64:sub_dsp20	7639	0, // GP64:sub_dsp20
7640	0, // GP64:sub_dsp21	7640	0, // GP64:sub_dsp21
7641	0, // GP64:sub_dsp22	7641	0, // GP64:sub_dsp22
7642	0, // GP64:sub_dsp23	7642	0, // GP64:sub_dsp23
7643	0, // GP64:sub_hi	7643	0, // GP64:sub_hi
7644	0, // GP64:sub_lo	7644	0, // GP64:sub_lo
7645	0, // GP64:sub_hi_then_sub_32	7645	0, // GP64:sub_hi_then_sub_32
7646	0, // GP64:sub_32_sub_hi_then_sub_32	7646	0, // GP64:sub_32_sub_hi_then_sub_32
7647	},	7647	},
7648	{ // GPR64_with_sub_32_in_CPURAReg	7648	{ // GPR64_with_sub_32_in_CPURAReg
7649	30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg	7649	30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
7650	0, // GPR64_with_sub_32_in_CPURAReg:sub_64	7650	0, // GPR64_with_sub_32_in_CPURAReg:sub_64
7651	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19	7651	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
7652	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20	7652	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
7653	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21	7653	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
7654	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22	7654	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
7655	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23	7655	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
7656	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi	7656	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi
7657	0, // GPR64_with_sub_32_in_CPURAReg:sub_lo	7657	0, // GPR64_with_sub_32_in_CPURAReg:sub_lo
7658	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32	7658	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
7659	0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32	7659	0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
7660	},	7660	},
7661	{ // GPR64_with_sub_32_in_GPR32ZERO	7661	{ // GPR64_with_sub_32_in_GPR32ZERO
7662	34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO	7662	34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
7663	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64	7663	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64
7664	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19	7664	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
7665	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20	7665	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
7666	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21	7666	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
7667	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22	7667	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
7668	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23	7668	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
7669	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi	7669	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
7670	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo	7670	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
7671	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32	7671	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
7672	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32	7672	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
7673	},	7673	},
7674	{ // HI64	7674	{ // HI64
7675	35, // HI64:sub_32 -> HI32	7675	35, // HI64:sub_32 -> HI32
7676	0, // HI64:sub_64	7676	0, // HI64:sub_64
7677	0, // HI64:sub_dsp16_19	7677	0, // HI64:sub_dsp16_19
7678	0, // HI64:sub_dsp20	7678	0, // HI64:sub_dsp20
7679	0, // HI64:sub_dsp21	7679	0, // HI64:sub_dsp21
7680	0, // HI64:sub_dsp22	7680	0, // HI64:sub_dsp22
7681	0, // HI64:sub_dsp23	7681	0, // HI64:sub_dsp23
7682	0, // HI64:sub_hi	7682	0, // HI64:sub_hi
7683	0, // HI64:sub_lo	7683	0, // HI64:sub_lo
7684	0, // HI64:sub_hi_then_sub_32	7684	0, // HI64:sub_hi_then_sub_32
7685	0, // HI64:sub_32_sub_hi_then_sub_32	7685	0, // HI64:sub_32_sub_hi_then_sub_32
7686	},	7686	},
7687	{ // LO64	7687	{ // LO64
7688	36, // LO64:sub_32 -> LO32	7688	36, // LO64:sub_32 -> LO32
7689	0, // LO64:sub_64	7689	0, // LO64:sub_64
7690	0, // LO64:sub_dsp16_19	7690	0, // LO64:sub_dsp16_19
7691	0, // LO64:sub_dsp20	7691	0, // LO64:sub_dsp20
7692	0, // LO64:sub_dsp21	7692	0, // LO64:sub_dsp21
7693	0, // LO64:sub_dsp22	7693	0, // LO64:sub_dsp22
7694	0, // LO64:sub_dsp23	7694	0, // LO64:sub_dsp23
7695	0, // LO64:sub_hi	7695	0, // LO64:sub_hi
7696	0, // LO64:sub_lo	7696	0, // LO64:sub_lo
7697	0, // LO64:sub_hi_then_sub_32	7697	0, // LO64:sub_hi_then_sub_32
7698	0, // LO64:sub_32_sub_hi_then_sub_32	7698	0, // LO64:sub_32_sub_hi_then_sub_32
7699	},	7699	},
7700	{ // SP64	7700	{ // SP64
7701	31, // SP64:sub_32 -> CPUSPReg	7701	31, // SP64:sub_32 -> CPUSPReg
7702	0, // SP64:sub_64	7702	0, // SP64:sub_64
7703	0, // SP64:sub_dsp16_19	7703	0, // SP64:sub_dsp16_19
7704	0, // SP64:sub_dsp20	7704	0, // SP64:sub_dsp20
7705	0, // SP64:sub_dsp21	7705	0, // SP64:sub_dsp21
7706	0, // SP64:sub_dsp22	7706	0, // SP64:sub_dsp22
7707	0, // SP64:sub_dsp23	7707	0, // SP64:sub_dsp23
7708	0, // SP64:sub_hi	7708	0, // SP64:sub_hi
7709	0, // SP64:sub_lo	7709	0, // SP64:sub_lo
7710	0, // SP64:sub_hi_then_sub_32	7710	0, // SP64:sub_hi_then_sub_32
7711	0, // SP64:sub_32_sub_hi_then_sub_32	7711	0, // SP64:sub_32_sub_hi_then_sub_32
7712	},	7712	},
7713	{ // MSA128B	7713	{ // MSA128B
7714	0, // MSA128B:sub_32	7714	0, // MSA128B:sub_32
7715	38, // MSA128B:sub_64 -> FGR64	7715	38, // MSA128B:sub_64 -> FGR64
7716	0, // MSA128B:sub_dsp16_19	7716	0, // MSA128B:sub_dsp16_19
7717	0, // MSA128B:sub_dsp20	7717	0, // MSA128B:sub_dsp20
7718	0, // MSA128B:sub_dsp21	7718	0, // MSA128B:sub_dsp21
7719	0, // MSA128B:sub_dsp22	7719	0, // MSA128B:sub_dsp22
7720	0, // MSA128B:sub_dsp23	7720	0, // MSA128B:sub_dsp23
7721	0, // MSA128B:sub_hi	7721	0, // MSA128B:sub_hi
7722	7, // MSA128B:sub_lo -> FGR32	7722	7, // MSA128B:sub_lo -> FGR32
7723	0, // MSA128B:sub_hi_then_sub_32	7723	0, // MSA128B:sub_hi_then_sub_32
7724	0, // MSA128B:sub_32_sub_hi_then_sub_32	7724	0, // MSA128B:sub_32_sub_hi_then_sub_32
7725	},	7725	},
7726	{ // MSA128D	7726	{ // MSA128D
7727	0, // MSA128D:sub_32	7727	0, // MSA128D:sub_32
7728	38, // MSA128D:sub_64 -> FGR64	7728	38, // MSA128D:sub_64 -> FGR64
7729	0, // MSA128D:sub_dsp16_19	7729	0, // MSA128D:sub_dsp16_19
7730	0, // MSA128D:sub_dsp20	7730	0, // MSA128D:sub_dsp20
7731	0, // MSA128D:sub_dsp21	7731	0, // MSA128D:sub_dsp21
7732	0, // MSA128D:sub_dsp22	7732	0, // MSA128D:sub_dsp22
7733	0, // MSA128D:sub_dsp23	7733	0, // MSA128D:sub_dsp23
7734	0, // MSA128D:sub_hi	7734	0, // MSA128D:sub_hi
7735	7, // MSA128D:sub_lo -> FGR32	7735	7, // MSA128D:sub_lo -> FGR32
7736	0, // MSA128D:sub_hi_then_sub_32	7736	0, // MSA128D:sub_hi_then_sub_32
7737	0, // MSA128D:sub_32_sub_hi_then_sub_32	7737	0, // MSA128D:sub_32_sub_hi_then_sub_32
7738	},	7738	},
7739	{ // MSA128H	7739	{ // MSA128H
7740	0, // MSA128H:sub_32	7740	0, // MSA128H:sub_32
7741	38, // MSA128H:sub_64 -> FGR64	7741	38, // MSA128H:sub_64 -> FGR64
7742	0, // MSA128H:sub_dsp16_19	7742	0, // MSA128H:sub_dsp16_19
7743	0, // MSA128H:sub_dsp20	7743	0, // MSA128H:sub_dsp20
7744	0, // MSA128H:sub_dsp21	7744	0, // MSA128H:sub_dsp21
7745	0, // MSA128H:sub_dsp22	7745	0, // MSA128H:sub_dsp22
7746	0, // MSA128H:sub_dsp23	7746	0, // MSA128H:sub_dsp23
7747	0, // MSA128H:sub_hi	7747	0, // MSA128H:sub_hi
7748	7, // MSA128H:sub_lo -> FGR32	7748	7, // MSA128H:sub_lo -> FGR32
7749	0, // MSA128H:sub_hi_then_sub_32	7749	0, // MSA128H:sub_hi_then_sub_32
7750	0, // MSA128H:sub_32_sub_hi_then_sub_32	7750	0, // MSA128H:sub_32_sub_hi_then_sub_32
7751	},	7751	},
7752	{ // MSA128W	7752	{ // MSA128W
7753	0, // MSA128W:sub_32	7753	0, // MSA128W:sub_32
7754	38, // MSA128W:sub_64 -> FGR64	7754	38, // MSA128W:sub_64 -> FGR64
7755	0, // MSA128W:sub_dsp16_19	7755	0, // MSA128W:sub_dsp16_19
7756	0, // MSA128W:sub_dsp20	7756	0, // MSA128W:sub_dsp20
7757	0, // MSA128W:sub_dsp21	7757	0, // MSA128W:sub_dsp21
7758	0, // MSA128W:sub_dsp22	7758	0, // MSA128W:sub_dsp22
7759	0, // MSA128W:sub_dsp23	7759	0, // MSA128W:sub_dsp23
7760	0, // MSA128W:sub_hi	7760	0, // MSA128W:sub_hi
7761	7, // MSA128W:sub_lo -> FGR32	7761	7, // MSA128W:sub_lo -> FGR32
7762	0, // MSA128W:sub_hi_then_sub_32	7762	0, // MSA128W:sub_hi_then_sub_32
7763	0, // MSA128W:sub_32_sub_hi_then_sub_32	7763	0, // MSA128W:sub_32_sub_hi_then_sub_32
7764	},	7764	},
7765	{ // MSA128WEvens	7765	{ // MSA128WEvens
7766	0, // MSA128WEvens:sub_32	7766	0, // MSA128WEvens:sub_32
7767	38, // MSA128WEvens:sub_64 -> FGR64	7767	38, // MSA128WEvens:sub_64 -> FGR64
7768	0, // MSA128WEvens:sub_dsp16_19	7768	0, // MSA128WEvens:sub_dsp16_19
7769	0, // MSA128WEvens:sub_dsp20	7769	0, // MSA128WEvens:sub_dsp20
7770	0, // MSA128WEvens:sub_dsp21	7770	0, // MSA128WEvens:sub_dsp21
7771	0, // MSA128WEvens:sub_dsp22	7771	0, // MSA128WEvens:sub_dsp22
7772	0, // MSA128WEvens:sub_dsp23	7772	0, // MSA128WEvens:sub_dsp23
7773	0, // MSA128WEvens:sub_hi	7773	0, // MSA128WEvens:sub_hi
7774	8, // MSA128WEvens:sub_lo -> FGRCC	7774	8, // MSA128WEvens:sub_lo -> FGRCC
7775	0, // MSA128WEvens:sub_hi_then_sub_32	7775	0, // MSA128WEvens:sub_hi_then_sub_32
7776	0, // MSA128WEvens:sub_32_sub_hi_then_sub_32	7776	0, // MSA128WEvens:sub_32_sub_hi_then_sub_32
7777	},	7777	},
7778	{ // ACC128	7778	{ // ACC128
7779	36, // ACC128:sub_32 -> LO32	7779	36, // ACC128:sub_32 -> LO32
7780	0, // ACC128:sub_64	7780	0, // ACC128:sub_64
7781	0, // ACC128:sub_dsp16_19	7781	0, // ACC128:sub_dsp16_19
7782	0, // ACC128:sub_dsp20	7782	0, // ACC128:sub_dsp20
7783	0, // ACC128:sub_dsp21	7783	0, // ACC128:sub_dsp21
7784	0, // ACC128:sub_dsp22	7784	0, // ACC128:sub_dsp22
7785	0, // ACC128:sub_dsp23	7785	0, // ACC128:sub_dsp23
7786	62, // ACC128:sub_hi -> HI64	7786	62, // ACC128:sub_hi -> HI64
7787	63, // ACC128:sub_lo -> LO64	7787	63, // ACC128:sub_lo -> LO64
7788	35, // ACC128:sub_hi_then_sub_32 -> HI32	7788	35, // ACC128:sub_hi_then_sub_32 -> HI32
7789	58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64	7789	58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
7790	},	7790	},
7791	};	7791	};
7792	assert(RC && "Missing regclass");	7792	assert(RC && "Missing regclass");
7793	if (!Idx) return RC;	7793	if (!Idx) return RC;
7794	--Idx;	7794	--Idx;
7795	assert(Idx < 11 && "Bad subreg");	7795	assert(Idx < 11 && "Bad subreg");
7796	unsigned TV = Table[RC->getID()][Idx];	7796	unsigned TV = Table[RC->getID()][Idx];
7797	return TV ? getRegClass(TV - 1) : nullptr;	7797	return TV ? getRegClass(TV - 1) : nullptr;
7798	}	7798	}
7799		7799
7800	/// Get the weight in units of pressure for this register class.	7800	/// Get the weight in units of pressure for this register class.
7801	const RegClassWeight &MipsGenRegisterInfo::	7801	const RegClassWeight &MipsGenRegisterInfo::
7802	getRegClassWeight(const TargetRegisterClass *RC) const {	7802	getRegClassWeight(const TargetRegisterClass *RC) const {
7803	static const RegClassWeight RCWeightTable[] = {	7803	static const RegClassWeight RCWeightTable[] = {
7804	{2, 64}, // MSA128F16	7804	{2, 64}, // MSA128F16
7805	{0, 0}, // CCR	7805	{0, 0}, // CCR
7806	{0, 0}, // COP0	7806	{0, 0}, // COP0
7807	{0, 0}, // COP2	7807	{0, 0}, // COP2
7808	{0, 0}, // COP3	7808	{0, 0}, // COP3
7809	{1, 32}, // DSPR	7809	{1, 32}, // DSPR
7810	{1, 32}, // FGR32	7810	{1, 32}, // FGR32
7811	{1, 32}, // FGRCC	7811	{1, 32}, // FGRCC
7812	{1, 32}, // GPR32	7812	{1, 32}, // GPR32
7813	{0, 0}, // HWRegs	7813	{0, 0}, // HWRegs
7814	{0, 0}, // MSACtrl	7814	{0, 0}, // MSACtrl
7815	{1, 31}, // GPR32NONZERO	7815	{1, 31}, // GPR32NONZERO
7816	{1, 9}, // CPU16RegsPlusSP	7816	{1, 9}, // CPU16RegsPlusSP
7817	{1, 8}, // CPU16Regs	7817	{1, 8}, // CPU16Regs
7818	{0, 0}, // FCC	7818	{0, 0}, // FCC
7819	{1, 8}, // GPRMM16	7819	{1, 8}, // GPRMM16
7820	{1, 8}, // GPRMM16MoveP	7820	{1, 8}, // GPRMM16MoveP
7821	{1, 8}, // GPRMM16Zero	7821	{1, 8}, // GPRMM16Zero
7822	{1, 7}, // CPU16Regs_and_GPRMM16Zero	7822	{1, 7}, // CPU16Regs_and_GPRMM16Zero
7823	{1, 7}, // GPR32NONZERO_and_GPRMM16MoveP	7823	{1, 7}, // GPR32NONZERO_and_GPRMM16MoveP
7824	{1, 5}, // GPRMM16MovePPairSecond	7824	{1, 5}, // GPRMM16MovePPairSecond
7825	{1, 4}, // CPU16Regs_and_GPRMM16MoveP	7825	{1, 4}, // CPU16Regs_and_GPRMM16MoveP
7826	{1, 4}, // GPRMM16MoveP_and_GPRMM16Zero	7826	{1, 4}, // GPRMM16MoveP_and_GPRMM16Zero
7827	{1, 4}, // HI32DSP	7827	{1, 4}, // HI32DSP
7828	{1, 4}, // LO32DSP	7828	{1, 4}, // LO32DSP
7829	{1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond	7829	{1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond
7830	{1, 3}, // GPRMM16MovePPairFirst	7830	{1, 3}, // GPRMM16MovePPairFirst
7831	{1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	7831	{1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7832	{1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	7832	{1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7833	{1, 1}, // CPURAReg	7833	{1, 1}, // CPURAReg
7834	{1, 1}, // CPUSPReg	7834	{1, 1}, // CPUSPReg
7835	{1, 1}, // DSPCC	7835	{1, 1}, // DSPCC
7836	{1, 1}, // GP32	7836	{1, 1}, // GP32
7837	{1, 1}, // GPR32ZERO	7837	{1, 1}, // GPR32ZERO
7838	{1, 1}, // HI32	7838	{1, 1}, // HI32
7839	{1, 1}, // LO32	7839	{1, 1}, // LO32
7840	{1, 1}, // SP32	7840	{1, 1}, // SP32
7841	{2, 64}, // FGR64	7841	{2, 64}, // FGR64
7842	{1, 32}, // GPR64	7842	{1, 32}, // GPR64
7843	{1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO	7843	{1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO
7844	{2, 32}, // AFGR64	7844	{2, 32}, // AFGR64
7845	{1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP	7845	{1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
7846	{1, 8}, // GPR64_with_sub_32_in_CPU16Regs	7846	{1, 8}, // GPR64_with_sub_32_in_CPU16Regs
7847	{1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP	7847	{1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
7848	{1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero	7848	{1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero
7849	{1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	7849	{1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
7850	{1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	7850	{1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
7851	{1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	7851	{1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
7852	{2, 8}, // ACC64DSP	7852	{2, 8}, // ACC64DSP
7853	{1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	7853	{1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
7854	{1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	7854	{1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
7855	{1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	7855	{1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
7856	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	7856	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
7857	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	7857	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
7858	{0, 0}, // OCTEON_MPL	7858	{0, 0}, // OCTEON_MPL
7859	{0, 0}, // OCTEON_P	7859	{0, 0}, // OCTEON_P
7860	{1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	7860	{1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
7861	{2, 2}, // ACC64	7861	{2, 2}, // ACC64
7862	{1, 1}, // GP64	7862	{1, 1}, // GP64
7863	{1, 1}, // GPR64_with_sub_32_in_CPURAReg	7863	{1, 1}, // GPR64_with_sub_32_in_CPURAReg
7864	{1, 1}, // GPR64_with_sub_32_in_GPR32ZERO	7864	{1, 1}, // GPR64_with_sub_32_in_GPR32ZERO
7865	{1, 1}, // HI64	7865	{1, 1}, // HI64
7866	{1, 1}, // LO64	7866	{1, 1}, // LO64
7867	{1, 1}, // SP64	7867	{1, 1}, // SP64
7868	{2, 64}, // MSA128B	7868	{2, 64}, // MSA128B
7869	{2, 64}, // MSA128D	7869	{2, 64}, // MSA128D
7870	{2, 64}, // MSA128H	7870	{2, 64}, // MSA128H
7871	{2, 64}, // MSA128W	7871	{2, 64}, // MSA128W
7872	{2, 32}, // MSA128WEvens	7872	{2, 32}, // MSA128WEvens
7873	{2, 2}, // ACC128	7873	{2, 2}, // ACC128
7874	};	7874	};
7875	return RCWeightTable[RC->getID()];	7875	return RCWeightTable[RC->getID()];
7876	}	7876	}
7877		7877
7878	/// Get the weight in units of pressure for this register unit.	7878	/// Get the weight in units of pressure for this register unit.
7879	unsigned MipsGenRegisterInfo::	7879	unsigned MipsGenRegisterInfo::
7880	getRegUnitWeight(unsigned RegUnit) const {	7880	getRegUnitWeight(unsigned RegUnit) const {
7881	assert(RegUnit < 321 && "invalid register unit");	7881	assert(RegUnit < 321 && "invalid register unit");
7882	// All register units have unit weight.	7882	// All register units have unit weight.
7883	return 1;	7883	return 1;
7884	}	7884	}
7885		7885
7886		7886
7887	// Get the number of dimensions of register pressure.	7887	// Get the number of dimensions of register pressure.
7888	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {	7888	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
7889	return 20;	7889	return 20;
7890	}	7890	}
7891		7891
7892	// Get the name of this register unit pressure set.	7892	// Get the name of this register unit pressure set.
7893	const char *MipsGenRegisterInfo::	7893	const char *MipsGenRegisterInfo::
7894	getRegPressureSetName(unsigned Idx) const {	7894	getRegPressureSetName(unsigned Idx) const {
7895	static const char *PressureNameTable[] = {	7895	static const char *PressureNameTable[] = {
7896	"DSPCC",	7896	"DSPCC",
7897	"GPR32ZERO",	7897	"GPR32ZERO",
7898	"GPR64_with_sub_32_in_CPURAReg",	7898	"GPR64_with_sub_32_in_CPURAReg",
7899	"HI32",	7899	"HI32",
7900	"GPRMM16MovePPairFirst",	7900	"GPRMM16MovePPairFirst",
7901	"CPU16Regs_and_GPRMM16MoveP",	7901	"CPU16Regs_and_GPRMM16MoveP",
7902	"HI32DSP",	7902	"HI32DSP",
7903	"LO32DSP",	7903	"LO32DSP",
7904	"GPRMM16MovePPairSecond",	7904	"GPRMM16MovePPairSecond",
7905	"GPRMM16MoveP",	7905	"GPRMM16MoveP",
7906	"ACC64DSP",	7906	"ACC64DSP",
7907	"CPU16Regs",	7907	"CPU16Regs",
7908	"GPRMM16Zero_with_GPRMM16MovePPairSecond",	7908	"GPRMM16Zero_with_GPRMM16MovePPairSecond",
7909	"CPU16Regs_with_GPRMM16MovePPairSecond",	7909	"CPU16Regs_with_GPRMM16MovePPairSecond",
7910	"CPU16Regs_with_GPRMM16MoveP",	7910	"CPU16Regs_with_GPRMM16MoveP",
7911	"DSPR",	7911	"DSPR",
7912	"FGR32",	7912	"FGR32",
7913	"MSA128WEvens",	7913	"MSA128WEvens",
7914	"FGR32_with_MSA128WEvens",	7914	"FGR32_with_MSA128WEvens",
7915	"MSA128F16",	7915	"MSA128F16",
7916	};	7916	};
7917	return PressureNameTable[Idx];	7917	return PressureNameTable[Idx];
7918	}	7918	}
7919		7919
7920	// Get the register unit pressure limit for this dimension.	7920	// Get the register unit pressure limit for this dimension.
7921	// This limit must be adjusted dynamically for reserved registers.	7921	// This limit must be adjusted dynamically for reserved registers.
7922	unsigned MipsGenRegisterInfo::	7922	unsigned MipsGenRegisterInfo::
7923	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {	7923	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
7924	static const uint8_t PressureLimitTable[] = {	7924	static const uint8_t PressureLimitTable[] = {
7925	1, // 0: DSPCC	7925	1, // 0: DSPCC
7926	1, // 1: GPR32ZERO	7926	1, // 1: GPR32ZERO
7927	1, // 2: GPR64_with_sub_32_in_CPURAReg	7927	1, // 2: GPR64_with_sub_32_in_CPURAReg
7928	2, // 3: HI32	7928	2, // 3: HI32
7929	3, // 4: GPRMM16MovePPairFirst	7929	3, // 4: GPRMM16MovePPairFirst
7930	5, // 5: CPU16Regs_and_GPRMM16MoveP	7930	5, // 5: CPU16Regs_and_GPRMM16MoveP
7931	5, // 6: HI32DSP	7931	5, // 6: HI32DSP
7932	5, // 7: LO32DSP	7932	5, // 7: LO32DSP
7933	6, // 8: GPRMM16MovePPairSecond	7933	6, // 8: GPRMM16MovePPairSecond
7934	8, // 9: GPRMM16MoveP	7934	8, // 9: GPRMM16MoveP
7935	8, // 10: ACC64DSP	7935	8, // 10: ACC64DSP
7936	10, // 11: CPU16Regs	7936	10, // 11: CPU16Regs
7937	10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond	7937	10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
7938	11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond	7938	11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond
7939	13, // 14: CPU16Regs_with_GPRMM16MoveP	7939	13, // 14: CPU16Regs_with_GPRMM16MoveP
7940	32, // 15: DSPR	7940	32, // 15: DSPR
7941	32, // 16: FGR32	7941	32, // 16: FGR32
7942	32, // 17: MSA128WEvens	7942	32, // 17: MSA128WEvens
7943	48, // 18: FGR32_with_MSA128WEvens	7943	48, // 18: FGR32_with_MSA128WEvens
7944	64, // 19: MSA128F16	7944	64, // 19: MSA128F16
7945	};	7945	};
7946	return PressureLimitTable[Idx];	7946	return PressureLimitTable[Idx];
7947	}	7947	}
7948		7948
7949	/// Table of pressure sets per register class or unit.	7949	/// Table of pressure sets per register class or unit.
7950	static const int RCSetsTable[] = {	7950	static const int RCSetsTable[] = {
7951	/* 0 */ 0, -1,	7951	/* 0 */ 0, -1,
7952	/* 2 */ 6, 10, -1,	7952	/* 2 */ 6, 10, -1,
7953	/* 5 */ 3, 6, 7, 10, -1,	7953	/* 5 */ 3, 6, 7, 10, -1,
7954	/* 10 */ 2, 15, -1,	7954	/* 10 */ 2, 15, -1,
7955	/* 13 */ 8, 12, 13, 15, -1,	7955	/* 13 */ 8, 12, 13, 15, -1,
7956	/* 18 */ 9, 14, 15, -1,	7956	/* 18 */ 9, 14, 15, -1,
7957	/* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,	7957	/* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
7958	/* 30 */ 5, 9, 11, 13, 14, 15, -1,	7958	/* 30 */ 5, 9, 11, 13, 14, 15, -1,
7959	/* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,	7959	/* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
7960	/* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,	7960	/* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
7961	/* 53 */ 16, 18, 19, -1,	7961	/* 53 */ 16, 18, 19, -1,
7962	/* 57 */ 16, 17, 18, 19, -1,	7962	/* 57 */ 16, 17, 18, 19, -1,
7963	};	7963	};
7964		7964
7965	/// Get the dimensions of register pressure impacted by this register class.	7965	/// Get the dimensions of register pressure impacted by this register class.
7966	/// Returns a -1 terminated array of pressure set IDs	7966	/// Returns a -1 terminated array of pressure set IDs
7967	const int *MipsGenRegisterInfo::	7967	const int *MipsGenRegisterInfo::
7968	getRegClassPressureSets(const TargetRegisterClass *RC) const {	7968	getRegClassPressureSets(const TargetRegisterClass *RC) const {
7969	static const uint8_t RCSetStartTable[] = {	7969	static const uint8_t RCSetStartTable[] = {
7970	55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};	7970	55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
7971	return &RCSetsTable[RCSetStartTable[RC->getID()]];	7971	return &RCSetsTable[RCSetStartTable[RC->getID()]];
7972	}	7972	}
7973		7973
7974	/// Get the dimensions of register pressure impacted by this register unit.	7974	/// Get the dimensions of register pressure impacted by this register unit.
7975	/// Returns a -1 terminated array of pressure set IDs	7975	/// Returns a -1 terminated array of pressure set IDs
7976	const int *MipsGenRegisterInfo::	7976	const int *MipsGenRegisterInfo::
7977	getRegUnitPressureSets(unsigned RegUnit) const {	7977	getRegUnitPressureSets(unsigned RegUnit) const {
7978	assert(RegUnit < 321 && "invalid register unit");	7978	assert(RegUnit < 321 && "invalid register unit");
7979	static const uint8_t RUSetStartTable[] = {	7979	static const uint8_t RUSetStartTable[] = {
7980	11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};	7980	11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
7981	return &RCSetsTable[RUSetStartTable[RegUnit]];	7981	return &RCSetsTable[RUSetStartTable[RegUnit]];
7982	}	7982	}
7983		7983
7984	extern const MCRegisterDesc MipsRegDesc[];	7984	extern const MCRegisterDesc MipsRegDesc[];
7985	extern const int16_t MipsRegDiffLists[];	7985	extern const int16_t MipsRegDiffLists[];
7986	extern const LaneBitmask MipsLaneMaskLists[];	7986	extern const LaneBitmask MipsLaneMaskLists[];
7987	extern const char MipsRegStrings[];	7987	extern const char MipsRegStrings[];
7988	extern const char MipsRegClassStrings[];	7988	extern const char MipsRegClassStrings[];
7989	extern const MCPhysReg MipsRegUnitRoots[][2];	7989	extern const MCPhysReg MipsRegUnitRoots[][2];
7990	extern const uint16_t MipsSubRegIdxLists[];	7990	extern const uint16_t MipsSubRegIdxLists[];
7991	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];	7991	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
7992	extern const uint16_t MipsRegEncodingTable[];	7992	extern const uint16_t MipsRegEncodingTable[];
7993	// Mips Dwarf<->LLVM register mappings.	7993	// Mips Dwarf<->LLVM register mappings.
7994	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];	7994	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
7995	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;	7995	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
7996		7996
7997	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];	7997	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
7998	extern const unsigned MipsEHFlavour0Dwarf2LSize;	7998	extern const unsigned MipsEHFlavour0Dwarf2LSize;
7999		7999
8000	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];	8000	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
8001	extern const unsigned MipsDwarfFlavour0L2DwarfSize;	8001	extern const unsigned MipsDwarfFlavour0L2DwarfSize;
8002		8002
8003	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];	8003	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
8004	extern const unsigned MipsEHFlavour0L2DwarfSize;	8004	extern const unsigned MipsEHFlavour0L2DwarfSize;
8005		8005
8006	MipsGenRegisterInfo::	8006	MipsGenRegisterInfo::
8007	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,	8007	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
8008	unsigned PC, unsigned HwMode)	8008	unsigned PC, unsigned HwMode)
8009	: TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,	8009	: TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
8010	SubRegIndexNameTable, SubRegIndexLaneMaskTable,	8010	SubRegIndexNameTable, SubRegIndexLaneMaskTable,
8011	LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {	8011	LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {
8012	InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,	8012	InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
8013	MipsMCRegisterClasses, 70,	8013	MipsMCRegisterClasses, 70,
8014	MipsRegUnitRoots,	8014	MipsRegUnitRoots,
8015	321,	8015	321,
8016	MipsRegDiffLists,	8016	MipsRegDiffLists,
8017	MipsLaneMaskLists,	8017	MipsLaneMaskLists,
8018	MipsRegStrings,	8018	MipsRegStrings,
8019	MipsRegClassStrings,	8019	MipsRegClassStrings,
8020	MipsSubRegIdxLists,	8020	MipsSubRegIdxLists,
8021	12,	8021	12,
8022	MipsSubRegIdxRanges,	8022	MipsSubRegIdxRanges,
8023	MipsRegEncodingTable);	8023	MipsRegEncodingTable);
8024		8024
8025	switch (DwarfFlavour) {	8025	switch (DwarfFlavour) {
8026	default:	8026	default:
8027	llvm_unreachable("Unknown DWARF flavour");	8027	llvm_unreachable("Unknown DWARF flavour");
8028	case 0:	8028	case 0:
8029	mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	8029	mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
8030	break;	8030	break;
8031	}	8031	}
8032	switch (EHFlavour) {	8032	switch (EHFlavour) {
8033	default:	8033	default:
8034	llvm_unreachable("Unknown DWARF flavour");	8034	llvm_unreachable("Unknown DWARF flavour");
8035	case 0:	8035	case 0:
8036	mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	8036	mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
8037	break;	8037	break;
8038	}	8038	}
8039	switch (DwarfFlavour) {	8039	switch (DwarfFlavour) {
8040	default:	8040	default:
8041	llvm_unreachable("Unknown DWARF flavour");	8041	llvm_unreachable("Unknown DWARF flavour");
8042	case 0:	8042	case 0:
8043	mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	8043	mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
8044	break;	8044	break;
8045	}	8045	}
8046	switch (EHFlavour) {	8046	switch (EHFlavour) {
8047	default:	8047	default:
8048	llvm_unreachable("Unknown DWARF flavour");	8048	llvm_unreachable("Unknown DWARF flavour");
8049	case 0:	8049	case 0:
8050	mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	8050	mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
8051	break;	8051	break;
8052	}	8052	}
8053	}	8053	}
8054		8054
8055	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };	8055	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
8056	static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	8056	static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8057	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };	8057	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
8058	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	8058	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
8059	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };	8059	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
8060	static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };	8060	static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
8061	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };	8061	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
8062	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };	8062	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
8063	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };	8063	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
8064	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };	8064	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
8065	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	8065	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8066	static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };	8066	static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
8067	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	8067	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
8068	static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };	8068	static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
8069	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	8069	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8070	static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	8070	static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8071	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	8071	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8072	static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };	8072	static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
8073	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	8073	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8074	static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	8074	static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8075	static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	8075	static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
8076	static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	8076	static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
8077		8077
8078		8078
8079	ArrayRef MipsGenRegisterInfo::getRegMasks() const {	8079	ArrayRef MipsGenRegisterInfo::getRegMasks() const {
8080	static const uint32_t *const Masks[] = {	8080	static const uint32_t *const Masks[] = {
8081	CSR_Interrupt_32_RegMask,	8081	CSR_Interrupt_32_RegMask,
8082	CSR_Interrupt_32R6_RegMask,	8082	CSR_Interrupt_32R6_RegMask,
8083	CSR_Interrupt_64_RegMask,	8083	CSR_Interrupt_64_RegMask,
8084	CSR_Interrupt_64R6_RegMask,	8084	CSR_Interrupt_64R6_RegMask,
8085	CSR_Mips16RetHelper_RegMask,	8085	CSR_Mips16RetHelper_RegMask,
8086	CSR_N32_RegMask,	8086	CSR_N32_RegMask,
8087	CSR_N64_RegMask,	8087	CSR_N64_RegMask,
8088	CSR_O32_RegMask,	8088	CSR_O32_RegMask,
8089	CSR_O32_FP64_RegMask,	8089	CSR_O32_FP64_RegMask,
8090	CSR_O32_FPXX_RegMask,	8090	CSR_O32_FPXX_RegMask,
8091	CSR_SingleFloatOnly_RegMask,	8091	CSR_SingleFloatOnly_RegMask,
8092	};	8092	};
8093	return ArrayRef(Masks);	8093	return ArrayRef(Masks);
8094	}	8094	}
8095		8095
8096	bool MipsGenRegisterInfo::	8096	bool MipsGenRegisterInfo::
8097	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {	8097	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8098	return	8098	return
8099	false;	8099	false;
8100	}	8100	}
8101		8101
8102	bool MipsGenRegisterInfo::	8102	bool MipsGenRegisterInfo::
8103	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {	8103	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8104	return	8104	return
8105	false;	8105	false;
8106	}	8106	}
8107		8107
8108	bool MipsGenRegisterInfo::	8108	bool MipsGenRegisterInfo::
8109	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {	8109	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
8110	return	8110	return
8111	false;	8111	false;
8112	}	8112	}
8113		8113
8114	bool MipsGenRegisterInfo::	8114	bool MipsGenRegisterInfo::
8115	isConstantPhysReg(MCRegister PhysReg) const {	8115	isConstantPhysReg(MCRegister PhysReg) const {
8116	return	8116	return
8117	PhysReg == Mips::ZERO \|\|	8117	PhysReg == Mips::ZERO \|\|
8118	PhysReg == Mips::ZERO_64 \|\|	8118	PhysReg == Mips::ZERO_64 \|\|
8119	false;	8119	false;
8120	}	8120	}
8121		8121
8122	ArrayRef MipsGenRegisterInfo::getRegMaskNames() const {	8122	ArrayRef MipsGenRegisterInfo::getRegMaskNames() const {
8123	static const char *Names[] = {	8123	static const char *Names[] = {
8124	"CSR_Interrupt_32",	8124	"CSR_Interrupt_32",
8125	"CSR_Interrupt_32R6",	8125	"CSR_Interrupt_32R6",
8126	"CSR_Interrupt_64",	8126	"CSR_Interrupt_64",
8127	"CSR_Interrupt_64R6",	8127	"CSR_Interrupt_64R6",
8128	"CSR_Mips16RetHelper",	8128	"CSR_Mips16RetHelper",
8129	"CSR_N32",	8129	"CSR_N32",
8130	"CSR_N64",	8130	"CSR_N64",
8131	"CSR_O32",	8131	"CSR_O32",
8132	"CSR_O32_FP64",	8132	"CSR_O32_FP64",
8133	"CSR_O32_FPXX",	8133	"CSR_O32_FPXX",
8134	"CSR_SingleFloatOnly",	8134	"CSR_SingleFloatOnly",
8135	};	8135	};
8136	return ArrayRef(Names);	8136	return ArrayRef(Names);
8137	}	8137	}
8138		8138
8139	const MipsFrameLowering *	8139	const MipsFrameLowering *
8140	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {	8140	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
8141	return static_cast(	8141	return static_cast(
8142	MF.getSubtarget().getFrameLowering());	8142	MF.getSubtarget().getFrameLowering());
8143	}	8143	}
8144		8144
8145	} // end namespace llvm	8145	} // end namespace llvm
8146		8146
8147	#endif // GET_REGINFO_TARGET_DESC	8147	#endif // GET_REGINFO_TARGET_DESC
8148		8148
8149		8149

Side By Side Comparison

Line Number	../DebugInfoTest/example_mips_dbg.ll	Hit count	Line Number	../DebugInfoTest/example_mips.ll	Hit count
1	/===- TableGen'erated file -------------------------------------- C++ --===\	---	1	/===- TableGen'erated file -------------------------------------- C++ --===\	---
2	\|* *\|	---	2	\|* *\|	---
3	\|* Target Register Enum Values *\|	---	3	\|* Target Register Enum Values *\|	---
4	\|* *\|	---	4	\|* *\|	---
5	\|* Automatically generated file, do not edit! *\|	---	5	\|* Automatically generated file, do not edit! *\|	---
6	\|* *\|	---	6	\|* *\|	---
7	\===----------------------------------------------------------------------===/	---	7	\===----------------------------------------------------------------------===/	---
8		---	8		---
9		---	9		---
10	#ifdef GET_REGINFO_ENUM	---	10	#ifdef GET_REGINFO_ENUM	---
11	#undef GET_REGINFO_ENUM	---	11	#undef GET_REGINFO_ENUM	---
12		---	12		---
13	namespace llvm {	---	13	namespace llvm {	---
14		---	14		---
15	class MCRegisterClass;	---	15	class MCRegisterClass;	---
16	extern const MCRegisterClass MipsMCRegisterClasses[];	---	16	extern const MCRegisterClass MipsMCRegisterClasses[];	---
17		---	17		---
18	namespace Mips {	---	18	namespace Mips {	---
19	enum {	---	19	enum {	---
20	NoRegister,	---	20	NoRegister,	---
21	AT = 1,	---	21	AT = 1,	---
22	DSPCCond = 2,	---	22	DSPCCond = 2,	---
23	DSPCarry = 3,	---	23	DSPCarry = 3,	---
24	DSPEFI = 4,	---	24	DSPEFI = 4,	---
25	DSPOutFlag = 5,	---	25	DSPOutFlag = 5,	---
26	DSPPos = 6,	---	26	DSPPos = 6,	---
27	DSPSCount = 7,	---	27	DSPSCount = 7,	---
28	FP = 8,	---	28	FP = 8,	---
29	GP = 9,	---	29	GP = 9,	---
30	MSAAccess = 10,	---	30	MSAAccess = 10,	---
31	MSACSR = 11,	---	31	MSACSR = 11,	---
32	MSAIR = 12,	---	32	MSAIR = 12,	---
33	MSAMap = 13,	---	33	MSAMap = 13,	---
34	MSAModify = 14,	---	34	MSAModify = 14,	---
35	MSARequest = 15,	---	35	MSARequest = 15,	---
36	MSASave = 16,	---	36	MSASave = 16,	---
37	MSAUnmap = 17,	---	37	MSAUnmap = 17,	---
38	PC = 18,	---	38	PC = 18,	---
39	RA = 19,	---	39	RA = 19,	---
40	SP = 20,	---	40	SP = 20,	---
41	ZERO = 21,	---	41	ZERO = 21,	---
42	A0 = 22,	---	42	A0 = 22,	---
43	A1 = 23,	---	43	A1 = 23,	---
44	A2 = 24,	---	44	A2 = 24,	---
45	A3 = 25,	---	45	A3 = 25,	---
46	AC0 = 26,	---	46	AC0 = 26,	---
47	AC1 = 27,	---	47	AC1 = 27,	---
48	AC2 = 28,	---	48	AC2 = 28,	---
49	AC3 = 29,	---	49	AC3 = 29,	---
50	AT_64 = 30,	---	50	AT_64 = 30,	---
51	COP00 = 31,	---	51	COP00 = 31,	---
52	COP01 = 32,	---	52	COP01 = 32,	---
53	COP02 = 33,	---	53	COP02 = 33,	---
54	COP03 = 34,	---	54	COP03 = 34,	---
55	COP04 = 35,	---	55	COP04 = 35,	---
56	COP05 = 36,	---	56	COP05 = 36,	---
57	COP06 = 37,	---	57	COP06 = 37,	---
58	COP07 = 38,	---	58	COP07 = 38,	---
59	COP08 = 39,	---	59	COP08 = 39,	---
60	COP09 = 40,	---	60	COP09 = 40,	---
61	COP20 = 41,	---	61	COP20 = 41,	---
62	COP21 = 42,	---	62	COP21 = 42,	---
63	COP22 = 43,	---	63	COP22 = 43,	---
64	COP23 = 44,	---	64	COP23 = 44,	---
65	COP24 = 45,	---	65	COP24 = 45,	---
66	COP25 = 46,	---	66	COP25 = 46,	---
67	COP26 = 47,	---	67	COP26 = 47,	---
68	COP27 = 48,	---	68	COP27 = 48,	---
69	COP28 = 49,	---	69	COP28 = 49,	---
70	COP29 = 50,	---	70	COP29 = 50,	---
71	COP30 = 51,	---	71	COP30 = 51,	---
72	COP31 = 52,	---	72	COP31 = 52,	---
73	COP32 = 53,	---	73	COP32 = 53,	---
74	COP33 = 54,	---	74	COP33 = 54,	---
75	COP34 = 55,	---	75	COP34 = 55,	---
76	COP35 = 56,	---	76	COP35 = 56,	---
77	COP36 = 57,	---	77	COP36 = 57,	---
78	COP37 = 58,	---	78	COP37 = 58,	---
79	COP38 = 59,	---	79	COP38 = 59,	---
80	COP39 = 60,	---	80	COP39 = 60,	---
81	COP010 = 61,	---	81	COP010 = 61,	---
82	COP011 = 62,	---	82	COP011 = 62,	---
83	COP012 = 63,	---	83	COP012 = 63,	---
84	COP013 = 64,	---	84	COP013 = 64,	---
85	COP014 = 65,	---	85	COP014 = 65,	---
86	COP015 = 66,	---	86	COP015 = 66,	---
87	COP016 = 67,	---	87	COP016 = 67,	---
88	COP017 = 68,	---	88	COP017 = 68,	---
89	COP018 = 69,	---	89	COP018 = 69,	---
90	COP019 = 70,	---	90	COP019 = 70,	---
91	COP020 = 71,	---	91	COP020 = 71,	---
92	COP021 = 72,	---	92	COP021 = 72,	---
93	COP022 = 73,	---	93	COP022 = 73,	---
94	COP023 = 74,	---	94	COP023 = 74,	---
95	COP024 = 75,	---	95	COP024 = 75,	---
96	COP025 = 76,	---	96	COP025 = 76,	---
97	COP026 = 77,	---	97	COP026 = 77,	---
98	COP027 = 78,	---	98	COP027 = 78,	---
99	COP028 = 79,	---	99	COP028 = 79,	---
100	COP029 = 80,	---	100	COP029 = 80,	---
101	COP030 = 81,	---	101	COP030 = 81,	---
102	COP031 = 82,	---	102	COP031 = 82,	---
103	COP210 = 83,	---	103	COP210 = 83,	---
104	COP211 = 84,	---	104	COP211 = 84,	---
105	COP212 = 85,	---	105	COP212 = 85,	---
106	COP213 = 86,	---	106	COP213 = 86,	---
107	COP214 = 87,	---	107	COP214 = 87,	---
108	COP215 = 88,	---	108	COP215 = 88,	---
109	COP216 = 89,	---	109	COP216 = 89,	---
110	COP217 = 90,	---	110	COP217 = 90,	---
111	COP218 = 91,	---	111	COP218 = 91,	---
112	COP219 = 92,	---	112	COP219 = 92,	---
113	COP220 = 93,	---	113	COP220 = 93,	---
114	COP221 = 94,	---	114	COP221 = 94,	---
115	COP222 = 95,	---	115	COP222 = 95,	---
116	COP223 = 96,	---	116	COP223 = 96,	---
117	COP224 = 97,	---	117	COP224 = 97,	---
118	COP225 = 98,	---	118	COP225 = 98,	---
119	COP226 = 99,	---	119	COP226 = 99,	---
120	COP227 = 100,	---	120	COP227 = 100,	---
121	COP228 = 101,	---	121	COP228 = 101,	---
122	COP229 = 102,	---	122	COP229 = 102,	---
123	COP230 = 103,	---	123	COP230 = 103,	---
124	COP231 = 104,	---	124	COP231 = 104,	---
125	COP310 = 105,	---	125	COP310 = 105,	---
126	COP311 = 106,	---	126	COP311 = 106,	---
127	COP312 = 107,	---	127	COP312 = 107,	---
128	COP313 = 108,	---	128	COP313 = 108,	---
129	COP314 = 109,	---	129	COP314 = 109,	---
130	COP315 = 110,	---	130	COP315 = 110,	---
131	COP316 = 111,	---	131	COP316 = 111,	---
132	COP317 = 112,	---	132	COP317 = 112,	---
133	COP318 = 113,	---	133	COP318 = 113,	---
134	COP319 = 114,	---	134	COP319 = 114,	---
135	COP320 = 115,	---	135	COP320 = 115,	---
136	COP321 = 116,	---	136	COP321 = 116,	---
137	COP322 = 117,	---	137	COP322 = 117,	---
138	COP323 = 118,	---	138	COP323 = 118,	---
139	COP324 = 119,	---	139	COP324 = 119,	---
140	COP325 = 120,	---	140	COP325 = 120,	---
141	COP326 = 121,	---	141	COP326 = 121,	---
142	COP327 = 122,	---	142	COP327 = 122,	---
143	COP328 = 123,	---	143	COP328 = 123,	---
144	COP329 = 124,	---	144	COP329 = 124,	---
145	COP330 = 125,	---	145	COP330 = 125,	---
146	COP331 = 126,	---	146	COP331 = 126,	---
147	D0 = 127,	---	147	D0 = 127,	---
148	D1 = 128,	---	148	D1 = 128,	---
149	D2 = 129,	---	149	D2 = 129,	---
150	D3 = 130,	---	150	D3 = 130,	---
151	D4 = 131,	---	151	D4 = 131,	---
152	D5 = 132,	---	152	D5 = 132,	---
153	D6 = 133,	---	153	D6 = 133,	---
154	D7 = 134,	---	154	D7 = 134,	---
155	D8 = 135,	---	155	D8 = 135,	---
156	D9 = 136,	---	156	D9 = 136,	---
157	D10 = 137,	---	157	D10 = 137,	---
158	D11 = 138,	---	158	D11 = 138,	---
159	D12 = 139,	---	159	D12 = 139,	---
160	D13 = 140,	---	160	D13 = 140,	---
161	D14 = 141,	---	161	D14 = 141,	---
162	D15 = 142,	---	162	D15 = 142,	---
163	DSPOutFlag20 = 143,	---	163	DSPOutFlag20 = 143,	---
164	DSPOutFlag21 = 144,	---	164	DSPOutFlag21 = 144,	---
165	DSPOutFlag22 = 145,	---	165	DSPOutFlag22 = 145,	---
166	DSPOutFlag23 = 146,	---	166	DSPOutFlag23 = 146,	---
167	F0 = 147,	---	167	F0 = 147,	---
168	F1 = 148,	---	168	F1 = 148,	---
169	F2 = 149,	---	169	F2 = 149,	---
170	F3 = 150,	---	170	F3 = 150,	---
171	F4 = 151,	---	171	F4 = 151,	---
172	F5 = 152,	---	172	F5 = 152,	---
173	F6 = 153,	---	173	F6 = 153,	---
174	F7 = 154,	---	174	F7 = 154,	---
175	F8 = 155,	---	175	F8 = 155,	---
176	F9 = 156,	---	176	F9 = 156,	---
177	F10 = 157,	---	177	F10 = 157,	---
178	F11 = 158,	---	178	F11 = 158,	---
179	F12 = 159,	---	179	F12 = 159,	---
180	F13 = 160,	---	180	F13 = 160,	---
181	F14 = 161,	---	181	F14 = 161,	---
182	F15 = 162,	---	182	F15 = 162,	---
183	F16 = 163,	---	183	F16 = 163,	---
184	F17 = 164,	---	184	F17 = 164,	---
185	F18 = 165,	---	185	F18 = 165,	---
186	F19 = 166,	---	186	F19 = 166,	---
187	F20 = 167,	---	187	F20 = 167,	---
188	F21 = 168,	---	188	F21 = 168,	---
189	F22 = 169,	---	189	F22 = 169,	---
190	F23 = 170,	---	190	F23 = 170,	---
191	F24 = 171,	---	191	F24 = 171,	---
192	F25 = 172,	---	192	F25 = 172,	---
193	F26 = 173,	---	193	F26 = 173,	---
194	F27 = 174,	---	194	F27 = 174,	---
195	F28 = 175,	---	195	F28 = 175,	---
196	F29 = 176,	---	196	F29 = 176,	---
197	F30 = 177,	---	197	F30 = 177,	---
198	F31 = 178,	---	198	F31 = 178,	---
199	FCC0 = 179,	---	199	FCC0 = 179,	---
200	FCC1 = 180,	---	200	FCC1 = 180,	---
201	FCC2 = 181,	---	201	FCC2 = 181,	---
202	FCC3 = 182,	---	202	FCC3 = 182,	---
203	FCC4 = 183,	---	203	FCC4 = 183,	---
204	FCC5 = 184,	---	204	FCC5 = 184,	---
205	FCC6 = 185,	---	205	FCC6 = 185,	---
206	FCC7 = 186,	---	206	FCC7 = 186,	---
207	FCR0 = 187,	---	207	FCR0 = 187,	---
208	FCR1 = 188,	---	208	FCR1 = 188,	---
209	FCR2 = 189,	---	209	FCR2 = 189,	---
210	FCR3 = 190,	---	210	FCR3 = 190,	---
211	FCR4 = 191,	---	211	FCR4 = 191,	---
212	FCR5 = 192,	---	212	FCR5 = 192,	---
213	FCR6 = 193,	---	213	FCR6 = 193,	---
214	FCR7 = 194,	---	214	FCR7 = 194,	---
215	FCR8 = 195,	---	215	FCR8 = 195,	---
216	FCR9 = 196,	---	216	FCR9 = 196,	---
217	FCR10 = 197,	---	217	FCR10 = 197,	---
218	FCR11 = 198,	---	218	FCR11 = 198,	---
219	FCR12 = 199,	---	219	FCR12 = 199,	---
220	FCR13 = 200,	---	220	FCR13 = 200,	---
221	FCR14 = 201,	---	221	FCR14 = 201,	---
222	FCR15 = 202,	---	222	FCR15 = 202,	---
223	FCR16 = 203,	---	223	FCR16 = 203,	---
224	FCR17 = 204,	---	224	FCR17 = 204,	---
225	FCR18 = 205,	---	225	FCR18 = 205,	---
226	FCR19 = 206,	---	226	FCR19 = 206,	---
227	FCR20 = 207,	---	227	FCR20 = 207,	---
228	FCR21 = 208,	---	228	FCR21 = 208,	---
229	FCR22 = 209,	---	229	FCR22 = 209,	---
230	FCR23 = 210,	---	230	FCR23 = 210,	---
231	FCR24 = 211,	---	231	FCR24 = 211,	---
232	FCR25 = 212,	---	232	FCR25 = 212,	---
233	FCR26 = 213,	---	233	FCR26 = 213,	---
234	FCR27 = 214,	---	234	FCR27 = 214,	---
235	FCR28 = 215,	---	235	FCR28 = 215,	---
236	FCR29 = 216,	---	236	FCR29 = 216,	---
237	FCR30 = 217,	---	237	FCR30 = 217,	---
238	FCR31 = 218,	---	238	FCR31 = 218,	---
239	FP_64 = 219,	---	239	FP_64 = 219,	---
240	F_HI0 = 220,	---	240	F_HI0 = 220,	---
241	F_HI1 = 221,	---	241	F_HI1 = 221,	---
242	F_HI2 = 222,	---	242	F_HI2 = 222,	---
243	F_HI3 = 223,	---	243	F_HI3 = 223,	---
244	F_HI4 = 224,	---	244	F_HI4 = 224,	---
245	F_HI5 = 225,	---	245	F_HI5 = 225,	---
246	F_HI6 = 226,	---	246	F_HI6 = 226,	---
247	F_HI7 = 227,	---	247	F_HI7 = 227,	---
248	F_HI8 = 228,	---	248	F_HI8 = 228,	---
249	F_HI9 = 229,	---	249	F_HI9 = 229,	---
250	F_HI10 = 230,	---	250	F_HI10 = 230,	---
251	F_HI11 = 231,	---	251	F_HI11 = 231,	---
252	F_HI12 = 232,	---	252	F_HI12 = 232,	---
253	F_HI13 = 233,	---	253	F_HI13 = 233,	---
254	F_HI14 = 234,	---	254	F_HI14 = 234,	---
255	F_HI15 = 235,	---	255	F_HI15 = 235,	---
256	F_HI16 = 236,	---	256	F_HI16 = 236,	---
257	F_HI17 = 237,	---	257	F_HI17 = 237,	---
258	F_HI18 = 238,	---	258	F_HI18 = 238,	---
259	F_HI19 = 239,	---	259	F_HI19 = 239,	---
260	F_HI20 = 240,	---	260	F_HI20 = 240,	---
261	F_HI21 = 241,	---	261	F_HI21 = 241,	---
262	F_HI22 = 242,	---	262	F_HI22 = 242,	---
263	F_HI23 = 243,	---	263	F_HI23 = 243,	---
264	F_HI24 = 244,	---	264	F_HI24 = 244,	---
265	F_HI25 = 245,	---	265	F_HI25 = 245,	---
266	F_HI26 = 246,	---	266	F_HI26 = 246,	---
267	F_HI27 = 247,	---	267	F_HI27 = 247,	---
268	F_HI28 = 248,	---	268	F_HI28 = 248,	---
269	F_HI29 = 249,	---	269	F_HI29 = 249,	---
270	F_HI30 = 250,	---	270	F_HI30 = 250,	---
271	F_HI31 = 251,	---	271	F_HI31 = 251,	---
272	GP_64 = 252,	---	272	GP_64 = 252,	---
273	HI0 = 253,	---	273	HI0 = 253,	---
274	HI1 = 254,	---	274	HI1 = 254,	---
275	HI2 = 255,	---	275	HI2 = 255,	---
276	HI3 = 256,	---	276	HI3 = 256,	---
277	HWR0 = 257,	---	277	HWR0 = 257,	---
278	HWR1 = 258,	---	278	HWR1 = 258,	---
279	HWR2 = 259,	---	279	HWR2 = 259,	---
280	HWR3 = 260,	---	280	HWR3 = 260,	---
281	HWR4 = 261,	---	281	HWR4 = 261,	---
282	HWR5 = 262,	---	282	HWR5 = 262,	---
283	HWR6 = 263,	---	283	HWR6 = 263,	---
284	HWR7 = 264,	---	284	HWR7 = 264,	---
285	HWR8 = 265,	---	285	HWR8 = 265,	---
286	HWR9 = 266,	---	286	HWR9 = 266,	---
287	HWR10 = 267,	---	287	HWR10 = 267,	---
288	HWR11 = 268,	---	288	HWR11 = 268,	---
289	HWR12 = 269,	---	289	HWR12 = 269,	---
290	HWR13 = 270,	---	290	HWR13 = 270,	---
291	HWR14 = 271,	---	291	HWR14 = 271,	---
292	HWR15 = 272,	---	292	HWR15 = 272,	---
293	HWR16 = 273,	---	293	HWR16 = 273,	---
294	HWR17 = 274,	---	294	HWR17 = 274,	---
295	HWR18 = 275,	---	295	HWR18 = 275,	---
296	HWR19 = 276,	---	296	HWR19 = 276,	---
297	HWR20 = 277,	---	297	HWR20 = 277,	---
298	HWR21 = 278,	---	298	HWR21 = 278,	---
299	HWR22 = 279,	---	299	HWR22 = 279,	---
300	HWR23 = 280,	---	300	HWR23 = 280,	---
301	HWR24 = 281,	---	301	HWR24 = 281,	---
302	HWR25 = 282,	---	302	HWR25 = 282,	---
303	HWR26 = 283,	---	303	HWR26 = 283,	---
304	HWR27 = 284,	---	304	HWR27 = 284,	---
305	HWR28 = 285,	---	305	HWR28 = 285,	---
306	HWR29 = 286,	---	306	HWR29 = 286,	---
307	HWR30 = 287,	---	307	HWR30 = 287,	---
308	HWR31 = 288,	---	308	HWR31 = 288,	---
309	K0 = 289,	---	309	K0 = 289,	---
310	K1 = 290,	---	310	K1 = 290,	---
311	LO0 = 291,	---	311	LO0 = 291,	---
312	LO1 = 292,	---	312	LO1 = 292,	---
313	LO2 = 293,	---	313	LO2 = 293,	---
314	LO3 = 294,	---	314	LO3 = 294,	---
315	MPL0 = 295,	---	315	MPL0 = 295,	---
316	MPL1 = 296,	---	316	MPL1 = 296,	---
317	MPL2 = 297,	---	317	MPL2 = 297,	---
318	MSA8 = 298,	---	318	MSA8 = 298,	---
319	MSA9 = 299,	---	319	MSA9 = 299,	---
320	MSA10 = 300,	---	320	MSA10 = 300,	---
321	MSA11 = 301,	---	321	MSA11 = 301,	---
322	MSA12 = 302,	---	322	MSA12 = 302,	---
323	MSA13 = 303,	---	323	MSA13 = 303,	---
324	MSA14 = 304,	---	324	MSA14 = 304,	---
325	MSA15 = 305,	---	325	MSA15 = 305,	---
326	MSA16 = 306,	---	326	MSA16 = 306,	---
327	MSA17 = 307,	---	327	MSA17 = 307,	---
328	MSA18 = 308,	---	328	MSA18 = 308,	---
329	MSA19 = 309,	---	329	MSA19 = 309,	---
330	MSA20 = 310,	---	330	MSA20 = 310,	---
331	MSA21 = 311,	---	331	MSA21 = 311,	---
332	MSA22 = 312,	---	332	MSA22 = 312,	---
333	MSA23 = 313,	---	333	MSA23 = 313,	---
334	MSA24 = 314,	---	334	MSA24 = 314,	---
335	MSA25 = 315,	---	335	MSA25 = 315,	---
336	MSA26 = 316,	---	336	MSA26 = 316,	---
337	MSA27 = 317,	---	337	MSA27 = 317,	---
338	MSA28 = 318,	---	338	MSA28 = 318,	---
339	MSA29 = 319,	---	339	MSA29 = 319,	---
340	MSA30 = 320,	---	340	MSA30 = 320,	---
341	MSA31 = 321,	---	341	MSA31 = 321,	---
342	P0 = 322,	---	342	P0 = 322,	---
343	P1 = 323,	---	343	P1 = 323,	---
344	P2 = 324,	---	344	P2 = 324,	---
345	RA_64 = 325,	---	345	RA_64 = 325,	---
346	S0 = 326,	---	346	S0 = 326,	---
347	S1 = 327,	---	347	S1 = 327,	---
348	S2 = 328,	---	348	S2 = 328,	---
349	S3 = 329,	---	349	S3 = 329,	---
350	S4 = 330,	---	350	S4 = 330,	---
351	S5 = 331,	---	351	S5 = 331,	---
352	S6 = 332,	---	352	S6 = 332,	---
353	S7 = 333,	---	353	S7 = 333,	---
354	SP_64 = 334,	---	354	SP_64 = 334,	---
355	T0 = 335,	---	355	T0 = 335,	---
356	T1 = 336,	---	356	T1 = 336,	---
357	T2 = 337,	---	357	T2 = 337,	---
358	T3 = 338,	---	358	T3 = 338,	---
359	T4 = 339,	---	359	T4 = 339,	---
360	T5 = 340,	---	360	T5 = 340,	---
361	T6 = 341,	---	361	T6 = 341,	---
362	T7 = 342,	---	362	T7 = 342,	---
363	T8 = 343,	---	363	T8 = 343,	---
364	T9 = 344,	---	364	T9 = 344,	---
365	V0 = 345,	---	365	V0 = 345,	---
366	V1 = 346,	---	366	V1 = 346,	---
367	W0 = 347,	---	367	W0 = 347,	---
368	W1 = 348,	---	368	W1 = 348,	---
369	W2 = 349,	---	369	W2 = 349,	---
370	W3 = 350,	---	370	W3 = 350,	---
371	W4 = 351,	---	371	W4 = 351,	---
372	W5 = 352,	---	372	W5 = 352,	---
373	W6 = 353,	---	373	W6 = 353,	---
374	W7 = 354,	---	374	W7 = 354,	---
375	W8 = 355,	---	375	W8 = 355,	---
376	W9 = 356,	---	376	W9 = 356,	---
377	W10 = 357,	---	377	W10 = 357,	---
378	W11 = 358,	---	378	W11 = 358,	---
379	W12 = 359,	---	379	W12 = 359,	---
380	W13 = 360,	---	380	W13 = 360,	---
381	W14 = 361,	---	381	W14 = 361,	---
382	W15 = 362,	---	382	W15 = 362,	---
383	W16 = 363,	---	383	W16 = 363,	---
384	W17 = 364,	---	384	W17 = 364,	---
385	W18 = 365,	---	385	W18 = 365,	---
386	W19 = 366,	---	386	W19 = 366,	---
387	W20 = 367,	---	387	W20 = 367,	---
388	W21 = 368,	---	388	W21 = 368,	---
389	W22 = 369,	---	389	W22 = 369,	---
390	W23 = 370,	---	390	W23 = 370,	---
391	W24 = 371,	---	391	W24 = 371,	---
392	W25 = 372,	---	392	W25 = 372,	---
393	W26 = 373,	---	393	W26 = 373,	---
394	W27 = 374,	---	394	W27 = 374,	---
395	W28 = 375,	---	395	W28 = 375,	---
396	W29 = 376,	---	396	W29 = 376,	---
397	W30 = 377,	---	397	W30 = 377,	---
398	W31 = 378,	---	398	W31 = 378,	---
399	ZERO_64 = 379,	---	399	ZERO_64 = 379,	---
400	A0_64 = 380,	---	400	A0_64 = 380,	---
401	A1_64 = 381,	---	401	A1_64 = 381,	---
402	A2_64 = 382,	---	402	A2_64 = 382,	---
403	A3_64 = 383,	---	403	A3_64 = 383,	---
404	AC0_64 = 384,	---	404	AC0_64 = 384,	---
405	D0_64 = 385,	---	405	D0_64 = 385,	---
406	D1_64 = 386,	---	406	D1_64 = 386,	---
407	D2_64 = 387,	---	407	D2_64 = 387,	---
408	D3_64 = 388,	---	408	D3_64 = 388,	---
409	D4_64 = 389,	---	409	D4_64 = 389,	---
410	D5_64 = 390,	---	410	D5_64 = 390,	---
411	D6_64 = 391,	---	411	D6_64 = 391,	---
412	D7_64 = 392,	---	412	D7_64 = 392,	---
413	D8_64 = 393,	---	413	D8_64 = 393,	---
414	D9_64 = 394,	---	414	D9_64 = 394,	---
415	D10_64 = 395,	---	415	D10_64 = 395,	---
416	D11_64 = 396,	---	416	D11_64 = 396,	---
417	D12_64 = 397,	---	417	D12_64 = 397,	---
418	D13_64 = 398,	---	418	D13_64 = 398,	---
419	D14_64 = 399,	---	419	D14_64 = 399,	---
420	D15_64 = 400,	---	420	D15_64 = 400,	---
421	D16_64 = 401,	---	421	D16_64 = 401,	---
422	D17_64 = 402,	---	422	D17_64 = 402,	---
423	D18_64 = 403,	---	423	D18_64 = 403,	---
424	D19_64 = 404,	---	424	D19_64 = 404,	---
425	D20_64 = 405,	---	425	D20_64 = 405,	---
426	D21_64 = 406,	---	426	D21_64 = 406,	---
427	D22_64 = 407,	---	427	D22_64 = 407,	---
428	D23_64 = 408,	---	428	D23_64 = 408,	---
429	D24_64 = 409,	---	429	D24_64 = 409,	---
430	D25_64 = 410,	---	430	D25_64 = 410,	---
431	D26_64 = 411,	---	431	D26_64 = 411,	---
432	D27_64 = 412,	---	432	D27_64 = 412,	---
433	D28_64 = 413,	---	433	D28_64 = 413,	---
434	D29_64 = 414,	---	434	D29_64 = 414,	---
435	D30_64 = 415,	---	435	D30_64 = 415,	---
436	D31_64 = 416,	---	436	D31_64 = 416,	---
437	DSPOutFlag16_19 = 417,	---	437	DSPOutFlag16_19 = 417,	---
438	HI0_64 = 418,	---	438	HI0_64 = 418,	---
439	K0_64 = 419,	---	439	K0_64 = 419,	---
440	K1_64 = 420,	---	440	K1_64 = 420,	---
441	LO0_64 = 421,	---	441	LO0_64 = 421,	---
442	S0_64 = 422,	---	442	S0_64 = 422,	---
443	S1_64 = 423,	---	443	S1_64 = 423,	---
444	S2_64 = 424,	---	444	S2_64 = 424,	---
445	S3_64 = 425,	---	445	S3_64 = 425,	---
446	S4_64 = 426,	---	446	S4_64 = 426,	---
447	S5_64 = 427,	---	447	S5_64 = 427,	---
448	S6_64 = 428,	---	448	S6_64 = 428,	---
449	S7_64 = 429,	---	449	S7_64 = 429,	---
450	T0_64 = 430,	---	450	T0_64 = 430,	---
451	T1_64 = 431,	---	451	T1_64 = 431,	---
452	T2_64 = 432,	---	452	T2_64 = 432,	---
453	T3_64 = 433,	---	453	T3_64 = 433,	---
454	T4_64 = 434,	---	454	T4_64 = 434,	---
455	T5_64 = 435,	---	455	T5_64 = 435,	---
456	T6_64 = 436,	---	456	T6_64 = 436,	---
457	T7_64 = 437,	---	457	T7_64 = 437,	---
458	T8_64 = 438,	---	458	T8_64 = 438,	---
459	T9_64 = 439,	---	459	T9_64 = 439,	---
460	V0_64 = 440,	---	460	V0_64 = 440,	---
461	V1_64 = 441,	---	461	V1_64 = 441,	---
462	NUM_TARGET_REGS // 442	---	462	NUM_TARGET_REGS // 442	---
463	};	---	463	};	---
464	} // end namespace Mips	---	464	} // end namespace Mips	---
465		---	465		---
466	// Register classes	---	466	// Register classes	---
467		---	467		---
468	namespace Mips {	---	468	namespace Mips {	---
469	enum {	---	469	enum {	---
470	MSA128F16RegClassID = 0,	---	470	MSA128F16RegClassID = 0,	---
471	CCRRegClassID = 1,	---	471	CCRRegClassID = 1,	---
472	COP0RegClassID = 2,	---	472	COP0RegClassID = 2,	---
473	COP2RegClassID = 3,	---	473	COP2RegClassID = 3,	---
474	COP3RegClassID = 4,	---	474	COP3RegClassID = 4,	---
475	DSPRRegClassID = 5,	---	475	DSPRRegClassID = 5,	---
476	FGR32RegClassID = 6,	---	476	FGR32RegClassID = 6,	---
477	FGRCCRegClassID = 7,	---	477	FGRCCRegClassID = 7,	---
478	GPR32RegClassID = 8,	---	478	GPR32RegClassID = 8,	---
479	HWRegsRegClassID = 9,	---	479	HWRegsRegClassID = 9,	---
480	MSACtrlRegClassID = 10,	---	480	MSACtrlRegClassID = 10,	---
481	GPR32NONZERORegClassID = 11,	---	481	GPR32NONZERORegClassID = 11,	---
482	CPU16RegsPlusSPRegClassID = 12,	---	482	CPU16RegsPlusSPRegClassID = 12,	---
483	CPU16RegsRegClassID = 13,	---	483	CPU16RegsRegClassID = 13,	---
484	FCCRegClassID = 14,	---	484	FCCRegClassID = 14,	---
485	GPRMM16RegClassID = 15,	---	485	GPRMM16RegClassID = 15,	---
486	GPRMM16MovePRegClassID = 16,	---	486	GPRMM16MovePRegClassID = 16,	---
487	GPRMM16ZeroRegClassID = 17,	---	487	GPRMM16ZeroRegClassID = 17,	---
488	CPU16Regs_and_GPRMM16ZeroRegClassID = 18,	---	488	CPU16Regs_and_GPRMM16ZeroRegClassID = 18,	---
489	GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,	---	489	GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,	---
490	GPRMM16MovePPairSecondRegClassID = 20,	---	490	GPRMM16MovePPairSecondRegClassID = 20,	---
491	CPU16Regs_and_GPRMM16MovePRegClassID = 21,	---	491	CPU16Regs_and_GPRMM16MovePRegClassID = 21,	---
492	GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,	---	492	GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,	---
493	HI32DSPRegClassID = 23,	---	493	HI32DSPRegClassID = 23,	---
494	LO32DSPRegClassID = 24,	---	494	LO32DSPRegClassID = 24,	---
495	CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,	---	495	CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,	---
496	GPRMM16MovePPairFirstRegClassID = 26,	---	496	GPRMM16MovePPairFirstRegClassID = 26,	---
497	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,	---	497	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,	---
498	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,	---	498	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,	---
499	CPURARegRegClassID = 29,	---	499	CPURARegRegClassID = 29,	---
500	CPUSPRegRegClassID = 30,	---	500	CPUSPRegRegClassID = 30,	---
501	DSPCCRegClassID = 31,	---	501	DSPCCRegClassID = 31,	---
502	GP32RegClassID = 32,	---	502	GP32RegClassID = 32,	---
503	GPR32ZERORegClassID = 33,	---	503	GPR32ZERORegClassID = 33,	---
504	HI32RegClassID = 34,	---	504	HI32RegClassID = 34,	---
505	LO32RegClassID = 35,	---	505	LO32RegClassID = 35,	---
506	SP32RegClassID = 36,	---	506	SP32RegClassID = 36,	---
507	FGR64RegClassID = 37,	---	507	FGR64RegClassID = 37,	---
508	GPR64RegClassID = 38,	---	508	GPR64RegClassID = 38,	---
509	GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,	---	509	GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,	---
510	AFGR64RegClassID = 40,	---	510	AFGR64RegClassID = 40,	---
511	GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,	---	511	GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,	---
512	GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,	---	512	GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,	---
513	GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,	---	513	GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,	---
514	GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,	---	514	GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,	---
515	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,	---	515	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,	---
516	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,	---	516	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,	---
517	GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,	---	517	GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,	---
518	ACC64DSPRegClassID = 48,	---	518	ACC64DSPRegClassID = 48,	---
519	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,	---	519	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,	---
520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,	---	520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,	---
521	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,	---	521	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,	---
522	GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,	---	522	GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,	---
523	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,	---	523	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,	---
524	OCTEON_MPLRegClassID = 54,	---	524	OCTEON_MPLRegClassID = 54,	---
525	OCTEON_PRegClassID = 55,	---	525	OCTEON_PRegClassID = 55,	---
526	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,	---	526	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,	---
527	ACC64RegClassID = 57,	---	527	ACC64RegClassID = 57,	---
528	GP64RegClassID = 58,	---	528	GP64RegClassID = 58,	---
529	GPR64_with_sub_32_in_CPURARegRegClassID = 59,	---	529	GPR64_with_sub_32_in_CPURARegRegClassID = 59,	---
530	GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,	---	530	GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,	---
531	HI64RegClassID = 61,	---	531	HI64RegClassID = 61,	---
532	LO64RegClassID = 62,	---	532	LO64RegClassID = 62,	---
533	SP64RegClassID = 63,	---	533	SP64RegClassID = 63,	---
534	MSA128BRegClassID = 64,	---	534	MSA128BRegClassID = 64,	---
535	MSA128DRegClassID = 65,	---	535	MSA128DRegClassID = 65,	---
536	MSA128HRegClassID = 66,	---	536	MSA128HRegClassID = 66,	---
537	MSA128WRegClassID = 67,	---	537	MSA128WRegClassID = 67,	---
538	MSA128WEvensRegClassID = 68,	---	538	MSA128WEvensRegClassID = 68,	---
539	ACC128RegClassID = 69,	---	539	ACC128RegClassID = 69,	---
540		---	540		---
541	};	---	541	};	---
542	} // end namespace Mips	---	542	} // end namespace Mips	---
543		---	543		---
544		---	544		---
545	// Subregister indices	---	545	// Subregister indices	---
546		---	546		---
547	namespace Mips {	---	547	namespace Mips {	---
548	enum : uint16_t {	---	548	enum : uint16_t {	---
549	NoSubRegister,	---	549	NoSubRegister,	---
550	sub_32, // 1	---	550	sub_32, // 1	---
551	sub_64, // 2	---	551	sub_64, // 2	---
552	sub_dsp16_19, // 3	---	552	sub_dsp16_19, // 3	---
553	sub_dsp20, // 4	---	553	sub_dsp20, // 4	---
554	sub_dsp21, // 5	---	554	sub_dsp21, // 5	---
555	sub_dsp22, // 6	---	555	sub_dsp22, // 6	---
556	sub_dsp23, // 7	---	556	sub_dsp23, // 7	---
557	sub_hi, // 8	---	557	sub_hi, // 8	---
558	sub_lo, // 9	---	558	sub_lo, // 9	---
559	sub_hi_then_sub_32, // 10	---	559	sub_hi_then_sub_32, // 10	---
560	sub_32_sub_hi_then_sub_32, // 11	---	560	sub_32_sub_hi_then_sub_32, // 11	---
561	NUM_TARGET_SUBREGS	---	561	NUM_TARGET_SUBREGS	---
562	};	---	562	};	---
563	} // end namespace Mips	---	563	} // end namespace Mips	---
564		---	564		---
565	// Register pressure sets enum.	---	565	// Register pressure sets enum.	---
566	namespace Mips {	---	566	namespace Mips {	---
567	enum RegisterPressureSets {	---	567	enum RegisterPressureSets {	---
568	DSPCC = 0,	---	568	DSPCC = 0,	---
569	GPR32ZERO = 1,	---	569	GPR32ZERO = 1,	---
570	GPR64_with_sub_32_in_CPURAReg = 2,	---	570	GPR64_with_sub_32_in_CPURAReg = 2,	---
571	HI32 = 3,	---	571	HI32 = 3,	---
572	GPRMM16MovePPairFirst = 4,	---	572	GPRMM16MovePPairFirst = 4,	---
573	CPU16Regs_and_GPRMM16MoveP = 5,	---	573	CPU16Regs_and_GPRMM16MoveP = 5,	---
574	HI32DSP = 6,	---	574	HI32DSP = 6,	---
575	LO32DSP = 7,	---	575	LO32DSP = 7,	---
576	GPRMM16MovePPairSecond = 8,	---	576	GPRMM16MovePPairSecond = 8,	---
577	GPRMM16MoveP = 9,	---	577	GPRMM16MoveP = 9,	---
578	ACC64DSP = 10,	---	578	ACC64DSP = 10,	---
579	CPU16Regs = 11,	---	579	CPU16Regs = 11,	---
580	GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,	---	580	GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,	---
581	CPU16Regs_with_GPRMM16MovePPairSecond = 13,	---	581	CPU16Regs_with_GPRMM16MovePPairSecond = 13,	---
582	CPU16Regs_with_GPRMM16MoveP = 14,	---	582	CPU16Regs_with_GPRMM16MoveP = 14,	---
583	DSPR = 15,	---	583	DSPR = 15,	---
584	FGR32 = 16,	---	584	FGR32 = 16,	---
585	MSA128WEvens = 17,	---	585	MSA128WEvens = 17,	---
586	FGR32_with_MSA128WEvens = 18,	---	586	FGR32_with_MSA128WEvens = 18,	---
587	MSA128F16 = 19,	---	587	MSA128F16 = 19,	---
588	};	---	588	};	---
589	} // end namespace Mips	---	589	} // end namespace Mips	---
590		---	590		---
591	} // end namespace llvm	---	591	} // end namespace llvm	---
592		---	592		---
593	#endif // GET_REGINFO_ENUM	---	593	#endif // GET_REGINFO_ENUM	---
594		---	594		---
595	/===- TableGen'erated file -------------------------------------- C++ --===\	---	595	/===- TableGen'erated file -------------------------------------- C++ --===\	---
596	\|* *\|	---	596	\|* *\|	---
597	\|* MC Register Information *\|	---	597	\|* MC Register Information *\|	---
598	\|* *\|	---	598	\|* *\|	---
599	\|* Automatically generated file, do not edit! *\|	---	599	\|* Automatically generated file, do not edit! *\|	---
600	\|* *\|	---	600	\|* *\|	---
601	\===----------------------------------------------------------------------===/	---	601	\===----------------------------------------------------------------------===/	---
602		---	602		---
603		---	603		---
604	#ifdef GET_REGINFO_MC_DESC	---	604	#ifdef GET_REGINFO_MC_DESC	---
605	#undef GET_REGINFO_MC_DESC	---	605	#undef GET_REGINFO_MC_DESC	---
606		---	606		---
607	namespace llvm {	---	607	namespace llvm {	---
608		---	608		---
609	extern const int16_t MipsRegDiffLists[] = {	---	609	extern const int16_t MipsRegDiffLists[] = {	---
610	/* 0 */ -412, 0,	---	610	/* 0 */ -412, 0,	---
611	/* 2 */ -358, 0,	---	611	/* 2 */ -358, 0,	---
612	/* 4 */ -314, 0,	---	612	/* 4 */ -314, 0,	---
613	/* 6 */ -306, 0,	---	613	/* 6 */ -306, 0,	---
614	/* 8 */ -265, 0,	---	614	/* 8 */ -265, 0,	---
615	/* 10 */ -243, 0,	---	615	/* 10 */ -243, 0,	---
616	/* 12 */ 37, -130, 127, -165, -227, 0,	---	616	/* 12 */ 37, -130, 127, -165, -227, 0,	---
617	/* 18 */ -211, 0,	---	617	/* 18 */ -211, 0,	---
618	/* 20 */ -165, 0,	---	618	/* 20 */ -165, 0,	---
619	/* 22 */ -141, 0,	---	619	/* 22 */ -141, 0,	---
620	/* 24 */ -140, 0,	---	620	/* 24 */ -140, 0,	---
621	/* 26 */ -139, 0,	---	621	/* 26 */ -139, 0,	---
622	/* 28 */ -138, 0,	---	622	/* 28 */ -138, 0,	---
623	/* 30 */ -130, 0,	---	623	/* 30 */ -130, 0,	---
624	/* 32 */ -96, 0,	---	624	/* 32 */ -96, 0,	---
625	/* 34 */ -95, 0,	---	625	/* 34 */ -95, 0,	---
626	/* 36 */ 165, -38, 0,	---	626	/* 36 */ 165, -38, 0,	---
627	/* 39 */ -20, 258, -38, 0,	---	627	/* 39 */ -20, 258, -38, 0,	---
628	/* 43 */ -21, 259, -38, 0,	---	628	/* 43 */ -21, 259, -38, 0,	---
629	/* 47 */ -22, 260, -38, 0,	---	629	/* 47 */ -22, 260, -38, 0,	---
630	/* 51 */ -23, 261, -38, 0,	---	630	/* 51 */ -23, 261, -38, 0,	---
631	/* 55 */ -24, 262, -38, 0,	---	631	/* 55 */ -24, 262, -38, 0,	---
632	/* 59 */ -25, 263, -38, 0,	---	632	/* 59 */ -25, 263, -38, 0,	---
633	/* 63 */ -26, 264, -38, 0,	---	633	/* 63 */ -26, 264, -38, 0,	---
634	/* 67 */ -27, 265, -38, 0,	---	634	/* 67 */ -27, 265, -38, 0,	---
635	/* 71 */ -28, 266, -38, 0,	---	635	/* 71 */ -28, 266, -38, 0,	---
636	/* 75 */ -29, 267, -38, 0,	---	636	/* 75 */ -29, 267, -38, 0,	---
637	/* 79 */ -30, 268, -38, 0,	---	637	/* 79 */ -30, 268, -38, 0,	---
638	/* 83 */ -31, 269, -38, 0,	---	638	/* 83 */ -31, 269, -38, 0,	---
639	/* 87 */ -32, 270, -38, 0,	---	639	/* 87 */ -32, 270, -38, 0,	---
640	/* 91 */ -33, 271, -38, 0,	---	640	/* 91 */ -33, 271, -38, 0,	---
641	/* 95 */ -34, 272, -38, 0,	---	641	/* 95 */ -34, 272, -38, 0,	---
642	/* 99 */ -35, 273, -38, 0,	---	642	/* 99 */ -35, 273, -38, 0,	---
643	/* 103 */ -36, 274, -38, 0,	---	643	/* 103 */ -36, 274, -38, 0,	---
644	/* 107 */ -265, 395, -37, 0,	---	644	/* 107 */ -265, 395, -37, 0,	---
645	/* 111 */ -227, 392, -34, 0,	---	645	/* 111 */ -227, 392, -34, 0,	---
646	/* 115 */ -29, 0,	---	646	/* 115 */ -29, 0,	---
647	/* 117 */ 412, -274, 1, 1, 1, 0,	---	647	/* 117 */ 412, -274, 1, 1, 1, 0,	---
648	/* 123 */ 1, 1, 1, 1, 0,	---	648	/* 123 */ 1, 1, 1, 1, 0,	---
649	/* 128 */ 20, 1, 0,	---	649	/* 128 */ 20, 1, 0,	---
650	/* 131 */ 21, 1, 0,	---	650	/* 131 */ 21, 1, 0,	---
651	/* 134 */ 22, 1, 0,	---	651	/* 134 */ 22, 1, 0,	---
652	/* 137 */ 23, 1, 0,	---	652	/* 137 */ 23, 1, 0,	---
653	/* 140 */ 24, 1, 0,	---	653	/* 140 */ 24, 1, 0,	---
654	/* 143 */ 25, 1, 0,	---	654	/* 143 */ 25, 1, 0,	---
655	/* 146 */ 26, 1, 0,	---	655	/* 146 */ 26, 1, 0,	---
656	/* 149 */ 27, 1, 0,	---	656	/* 149 */ 27, 1, 0,	---
657	/* 152 */ 28, 1, 0,	---	657	/* 152 */ 28, 1, 0,	---
658	/* 155 */ 29, 1, 0,	---	658	/* 155 */ 29, 1, 0,	---
659	/* 158 */ 30, 1, 0,	---	659	/* 158 */ 30, 1, 0,	---
660	/* 161 */ 31, 1, 0,	---	660	/* 161 */ 31, 1, 0,	---
661	/* 164 */ 32, 1, 0,	---	661	/* 164 */ 32, 1, 0,	---
662	/* 167 */ 33, 1, 0,	---	662	/* 167 */ 33, 1, 0,	---
663	/* 170 */ 34, 1, 0,	---	663	/* 170 */ 34, 1, 0,	---
664	/* 173 */ 35, 1, 0,	---	664	/* 173 */ 35, 1, 0,	---
665	/* 176 */ 29, 0,	---	665	/* 176 */ 29, 0,	---
666	/* 178 */ 72, 0,	---	666	/* 178 */ 72, 0,	---
667	/* 180 */ 38, -238, 73, 0,	---	667	/* 180 */ 38, -238, 73, 0,	---
668	/* 184 */ 95, 0,	---	668	/* 184 */ 95, 0,	---
669	/* 186 */ 96, 0,	---	669	/* 186 */ 96, 0,	---
670	/* 188 */ 130, 0,	---	670	/* 188 */ 130, 0,	---
671	/* 190 */ 211, 0,	---	671	/* 190 */ 211, 0,	---
672	/* 192 */ 243, 0,	---	672	/* 192 */ 243, 0,	---
673	/* 194 */ 306, 0,	---	673	/* 194 */ 306, 0,	---
674	/* 196 */ 314, 0,	---	674	/* 196 */ 314, 0,	---
675	/* 198 */ 358, 0,	---	675	/* 198 */ 358, 0,	---
676	};	---	676	};	---
677		---	677		---
678	extern const LaneBitmask MipsLaneMaskLists[] = {	---	678	extern const LaneBitmask MipsLaneMaskLists[] = {	---
679	/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),	---	679	/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),	---
680	/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),	---	680	/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),	---
681	/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),	---	681	/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),	---
682	/* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),	---	682	/* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),	---
683	};	---	683	};	---
684		---	684		---
685	extern const uint16_t MipsSubRegIdxLists[] = {	---	685	extern const uint16_t MipsSubRegIdxLists[] = {	---
686	/* 0 */ 1, 0,	---	686	/* 0 */ 1, 0,	---
687	/* 2 */ 3, 4, 5, 6, 7, 0,	---	687	/* 2 */ 3, 4, 5, 6, 7, 0,	---
688	/* 8 */ 2, 9, 8, 0,	---	688	/* 8 */ 2, 9, 8, 0,	---
689	/* 12 */ 9, 1, 8, 10, 11, 0,	---	689	/* 12 */ 9, 1, 8, 10, 11, 0,	---
690	};	---	690	};	---
691		---	691		---
692	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {	---	692	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {	---
693	{ 65535, 65535 },	---	693	{ 65535, 65535 },	---
694	{ 0, 32 }, // sub_32	---	694	{ 0, 32 }, // sub_32	---
695	{ 0, 64 }, // sub_64	---	695	{ 0, 64 }, // sub_64	---
696	{ 16, 4 }, // sub_dsp16_19	---	696	{ 16, 4 }, // sub_dsp16_19	---
697	{ 20, 1 }, // sub_dsp20	---	697	{ 20, 1 }, // sub_dsp20	---
698	{ 21, 1 }, // sub_dsp21	---	698	{ 21, 1 }, // sub_dsp21	---
699	{ 22, 1 }, // sub_dsp22	---	699	{ 22, 1 }, // sub_dsp22	---
700	{ 23, 1 }, // sub_dsp23	---	700	{ 23, 1 }, // sub_dsp23	---
701	{ 32, 32 }, // sub_hi	---	701	{ 32, 32 }, // sub_hi	---
702	{ 0, 32 }, // sub_lo	---	702	{ 0, 32 }, // sub_lo	---
703	{ 32, 32 }, // sub_hi_then_sub_32	---	703	{ 32, 32 }, // sub_hi_then_sub_32	---
704	{ 0, 64 }, // sub_32_sub_hi_then_sub_32	---	704	{ 0, 64 }, // sub_32_sub_hi_then_sub_32	---
705	};	---	705	};	---
706		---	706		---
707		---	707		---
708	#ifdef __GNUC__	---	708	#ifdef __GNUC__	---
709	#pragma GCC diagnostic push	---	709	#pragma GCC diagnostic push	---
710	#pragma GCC diagnostic ignored "-Woverlength-strings"	---	710	#pragma GCC diagnostic ignored "-Woverlength-strings"	---
711	#endif	---	711	#endif	---
712	extern const char MipsRegStrings[] = {	---	712	extern const char MipsRegStrings[] = {	---
713	/* 0 */ "COP00\0"	---	713	/* 0 */ "COP00\0"	---
714	/* 6 */ "COP010\0"	---	714	/* 6 */ "COP010\0"	---
715	/* 13 */ "COP210\0"	---	715	/* 13 */ "COP210\0"	---
716	/* 20 */ "COP310\0"	---	716	/* 20 */ "COP310\0"	---
717	/* 27 */ "MSA10\0"	---	717	/* 27 */ "MSA10\0"	---
718	/* 33 */ "D10\0"	---	718	/* 33 */ "D10\0"	---
719	/* 37 */ "F10\0"	---	719	/* 37 */ "F10\0"	---
720	/* 41 */ "F_HI10\0"	---	720	/* 41 */ "F_HI10\0"	---
721	/* 48 */ "FCR10\0"	---	721	/* 48 */ "FCR10\0"	---
722	/* 54 */ "HWR10\0"	---	722	/* 54 */ "HWR10\0"	---
723	/* 60 */ "W10\0"	---	723	/* 60 */ "W10\0"	---
724	/* 64 */ "COP020\0"	---	724	/* 64 */ "COP020\0"	---
725	/* 71 */ "COP220\0"	---	725	/* 71 */ "COP220\0"	---
726	/* 78 */ "COP320\0"	---	726	/* 78 */ "COP320\0"	---
727	/* 85 */ "MSA20\0"	---	727	/* 85 */ "MSA20\0"	---
728	/* 91 */ "F20\0"	---	728	/* 91 */ "F20\0"	---
729	/* 95 */ "F_HI20\0"	---	729	/* 95 */ "F_HI20\0"	---
730	/* 102 */ "COP20\0"	---	730	/* 102 */ "COP20\0"	---
731	/* 108 */ "FCR20\0"	---	731	/* 108 */ "FCR20\0"	---
732	/* 114 */ "HWR20\0"	---	732	/* 114 */ "HWR20\0"	---
733	/* 120 */ "W20\0"	---	733	/* 120 */ "W20\0"	---
734	/* 124 */ "DSPOutFlag20\0"	---	734	/* 124 */ "DSPOutFlag20\0"	---
735	/* 137 */ "COP030\0"	---	735	/* 137 */ "COP030\0"	---
736	/* 144 */ "COP230\0"	---	736	/* 144 */ "COP230\0"	---
737	/* 151 */ "COP330\0"	---	737	/* 151 */ "COP330\0"	---
738	/* 158 */ "MSA30\0"	---	738	/* 158 */ "MSA30\0"	---
739	/* 164 */ "F30\0"	---	739	/* 164 */ "F30\0"	---
740	/* 168 */ "F_HI30\0"	---	740	/* 168 */ "F_HI30\0"	---
741	/* 175 */ "COP30\0"	---	741	/* 175 */ "COP30\0"	---
742	/* 181 */ "FCR30\0"	---	742	/* 181 */ "FCR30\0"	---
743	/* 187 */ "HWR30\0"	---	743	/* 187 */ "HWR30\0"	---
744	/* 193 */ "W30\0"	---	744	/* 193 */ "W30\0"	---
745	/* 197 */ "A0\0"	---	745	/* 197 */ "A0\0"	---
746	/* 200 */ "AC0\0"	---	746	/* 200 */ "AC0\0"	---
747	/* 204 */ "FCC0\0"	---	747	/* 204 */ "FCC0\0"	---
748	/* 209 */ "D0\0"	---	748	/* 209 */ "D0\0"	---
749	/* 212 */ "F0\0"	---	749	/* 212 */ "F0\0"	---
750	/* 215 */ "F_HI0\0"	---	750	/* 215 */ "F_HI0\0"	---
751	/* 221 */ "K0\0"	---	751	/* 221 */ "K0\0"	---
752	/* 224 */ "MPL0\0"	---	752	/* 224 */ "MPL0\0"	---
753	/* 229 */ "LO0\0"	---	753	/* 229 */ "LO0\0"	---
754	/* 233 */ "P0\0"	---	754	/* 233 */ "P0\0"	---
755	/* 236 */ "FCR0\0"	---	755	/* 236 */ "FCR0\0"	---
756	/* 241 */ "HWR0\0"	---	756	/* 241 */ "HWR0\0"	---
757	/* 246 */ "S0\0"	---	757	/* 246 */ "S0\0"	---
758	/* 249 */ "T0\0"	---	758	/* 249 */ "T0\0"	---
759	/* 252 */ "V0\0"	---	759	/* 252 */ "V0\0"	---
760	/* 255 */ "W0\0"	---	760	/* 255 */ "W0\0"	---
761	/* 258 */ "COP01\0"	---	761	/* 258 */ "COP01\0"	---
762	/* 264 */ "COP011\0"	---	762	/* 264 */ "COP011\0"	---
763	/* 271 */ "COP211\0"	---	763	/* 271 */ "COP211\0"	---
764	/* 278 */ "COP311\0"	---	764	/* 278 */ "COP311\0"	---
765	/* 285 */ "MSA11\0"	---	765	/* 285 */ "MSA11\0"	---
766	/* 291 */ "D11\0"	---	766	/* 291 */ "D11\0"	---
767	/* 295 */ "F11\0"	---	767	/* 295 */ "F11\0"	---
768	/* 299 */ "F_HI11\0"	---	768	/* 299 */ "F_HI11\0"	---
769	/* 306 */ "FCR11\0"	---	769	/* 306 */ "FCR11\0"	---
770	/* 312 */ "HWR11\0"	---	770	/* 312 */ "HWR11\0"	---
771	/* 318 */ "W11\0"	---	771	/* 318 */ "W11\0"	---
772	/* 322 */ "COP021\0"	---	772	/* 322 */ "COP021\0"	---
773	/* 329 */ "COP221\0"	---	773	/* 329 */ "COP221\0"	---
774	/* 336 */ "COP321\0"	---	774	/* 336 */ "COP321\0"	---
775	/* 343 */ "MSA21\0"	---	775	/* 343 */ "MSA21\0"	---
776	/* 349 */ "F21\0"	---	776	/* 349 */ "F21\0"	---
777	/* 353 */ "F_HI21\0"	---	777	/* 353 */ "F_HI21\0"	---
778	/* 360 */ "COP21\0"	---	778	/* 360 */ "COP21\0"	---
779	/* 366 */ "FCR21\0"	---	779	/* 366 */ "FCR21\0"	---
780	/* 372 */ "HWR21\0"	---	780	/* 372 */ "HWR21\0"	---
781	/* 378 */ "W21\0"	---	781	/* 378 */ "W21\0"	---
782	/* 382 */ "DSPOutFlag21\0"	---	782	/* 382 */ "DSPOutFlag21\0"	---
783	/* 395 */ "COP031\0"	---	783	/* 395 */ "COP031\0"	---
784	/* 402 */ "COP231\0"	---	784	/* 402 */ "COP231\0"	---
785	/* 409 */ "COP331\0"	---	785	/* 409 */ "COP331\0"	---
786	/* 416 */ "MSA31\0"	---	786	/* 416 */ "MSA31\0"	---
787	/* 422 */ "F31\0"	---	787	/* 422 */ "F31\0"	---
788	/* 426 */ "F_HI31\0"	---	788	/* 426 */ "F_HI31\0"	---
789	/* 433 */ "COP31\0"	---	789	/* 433 */ "COP31\0"	---
790	/* 439 */ "FCR31\0"	---	790	/* 439 */ "FCR31\0"	---
791	/* 445 */ "HWR31\0"	---	791	/* 445 */ "HWR31\0"	---
792	/* 451 */ "W31\0"	---	792	/* 451 */ "W31\0"	---
793	/* 455 */ "A1\0"	---	793	/* 455 */ "A1\0"	---
794	/* 458 */ "AC1\0"	---	794	/* 458 */ "AC1\0"	---
795	/* 462 */ "FCC1\0"	---	795	/* 462 */ "FCC1\0"	---
796	/* 467 */ "D1\0"	---	796	/* 467 */ "D1\0"	---
797	/* 470 */ "F1\0"	---	797	/* 470 */ "F1\0"	---
798	/* 473 */ "F_HI1\0"	---	798	/* 473 */ "F_HI1\0"	---
799	/* 479 */ "K1\0"	---	799	/* 479 */ "K1\0"	---
800	/* 482 */ "MPL1\0"	---	800	/* 482 */ "MPL1\0"	---
801	/* 487 */ "LO1\0"	---	801	/* 487 */ "LO1\0"	---
802	/* 491 */ "P1\0"	---	802	/* 491 */ "P1\0"	---
803	/* 494 */ "FCR1\0"	---	803	/* 494 */ "FCR1\0"	---
804	/* 499 */ "HWR1\0"	---	804	/* 499 */ "HWR1\0"	---
805	/* 504 */ "S1\0"	---	805	/* 504 */ "S1\0"	---
806	/* 507 */ "T1\0"	---	806	/* 507 */ "T1\0"	---
807	/* 510 */ "V1\0"	---	807	/* 510 */ "V1\0"	---
808	/* 513 */ "W1\0"	---	808	/* 513 */ "W1\0"	---
809	/* 516 */ "COP02\0"	---	809	/* 516 */ "COP02\0"	---
810	/* 522 */ "COP012\0"	---	810	/* 522 */ "COP012\0"	---
811	/* 529 */ "COP212\0"	---	811	/* 529 */ "COP212\0"	---
812	/* 536 */ "COP312\0"	---	812	/* 536 */ "COP312\0"	---
813	/* 543 */ "MSA12\0"	---	813	/* 543 */ "MSA12\0"	---
814	/* 549 */ "D12\0"	---	814	/* 549 */ "D12\0"	---
815	/* 553 */ "F12\0"	---	815	/* 553 */ "F12\0"	---
816	/* 557 */ "F_HI12\0"	---	816	/* 557 */ "F_HI12\0"	---
817	/* 564 */ "FCR12\0"	---	817	/* 564 */ "FCR12\0"	---
818	/* 570 */ "HWR12\0"	---	818	/* 570 */ "HWR12\0"	---
819	/* 576 */ "W12\0"	---	819	/* 576 */ "W12\0"	---
820	/* 580 */ "COP022\0"	---	820	/* 580 */ "COP022\0"	---
821	/* 587 */ "COP222\0"	---	821	/* 587 */ "COP222\0"	---
822	/* 594 */ "COP322\0"	---	822	/* 594 */ "COP322\0"	---
823	/* 601 */ "MSA22\0"	---	823	/* 601 */ "MSA22\0"	---
824	/* 607 */ "F22\0"	---	824	/* 607 */ "F22\0"	---
825	/* 611 */ "F_HI22\0"	---	825	/* 611 */ "F_HI22\0"	---
826	/* 618 */ "COP22\0"	---	826	/* 618 */ "COP22\0"	---
827	/* 624 */ "FCR22\0"	---	827	/* 624 */ "FCR22\0"	---
828	/* 630 */ "HWR22\0"	---	828	/* 630 */ "HWR22\0"	---
829	/* 636 */ "W22\0"	---	829	/* 636 */ "W22\0"	---
830	/* 640 */ "DSPOutFlag22\0"	---	830	/* 640 */ "DSPOutFlag22\0"	---
831	/* 653 */ "COP32\0"	---	831	/* 653 */ "COP32\0"	---
832	/* 659 */ "A2\0"	---	832	/* 659 */ "A2\0"	---
833	/* 662 */ "AC2\0"	---	833	/* 662 */ "AC2\0"	---
834	/* 666 */ "FCC2\0"	---	834	/* 666 */ "FCC2\0"	---
835	/* 671 */ "D2\0"	---	835	/* 671 */ "D2\0"	---
836	/* 674 */ "F2\0"	---	836	/* 674 */ "F2\0"	---
837	/* 677 */ "F_HI2\0"	---	837	/* 677 */ "F_HI2\0"	---
838	/* 683 */ "MPL2\0"	---	838	/* 683 */ "MPL2\0"	---
839	/* 688 */ "LO2\0"	---	839	/* 688 */ "LO2\0"	---
840	/* 692 */ "P2\0"	---	840	/* 692 */ "P2\0"	---
841	/* 695 */ "FCR2\0"	---	841	/* 695 */ "FCR2\0"	---
842	/* 700 */ "HWR2\0"	---	842	/* 700 */ "HWR2\0"	---
843	/* 705 */ "S2\0"	---	843	/* 705 */ "S2\0"	---
844	/* 708 */ "T2\0"	---	844	/* 708 */ "T2\0"	---
845	/* 711 */ "W2\0"	---	845	/* 711 */ "W2\0"	---
846	/* 714 */ "COP03\0"	---	846	/* 714 */ "COP03\0"	---
847	/* 720 */ "COP013\0"	---	847	/* 720 */ "COP013\0"	---
848	/* 727 */ "COP213\0"	---	848	/* 727 */ "COP213\0"	---
849	/* 734 */ "COP313\0"	---	849	/* 734 */ "COP313\0"	---
850	/* 741 */ "MSA13\0"	---	850	/* 741 */ "MSA13\0"	---
851	/* 747 */ "D13\0"	---	851	/* 747 */ "D13\0"	---
852	/* 751 */ "F13\0"	---	852	/* 751 */ "F13\0"	---
853	/* 755 */ "F_HI13\0"	---	853	/* 755 */ "F_HI13\0"	---
854	/* 762 */ "FCR13\0"	---	854	/* 762 */ "FCR13\0"	---
855	/* 768 */ "HWR13\0"	---	855	/* 768 */ "HWR13\0"	---
856	/* 774 */ "W13\0"	---	856	/* 774 */ "W13\0"	---
857	/* 778 */ "COP023\0"	---	857	/* 778 */ "COP023\0"	---
858	/* 785 */ "COP223\0"	---	858	/* 785 */ "COP223\0"	---
859	/* 792 */ "COP323\0"	---	859	/* 792 */ "COP323\0"	---
860	/* 799 */ "MSA23\0"	---	860	/* 799 */ "MSA23\0"	---
861	/* 805 */ "F23\0"	---	861	/* 805 */ "F23\0"	---
862	/* 809 */ "F_HI23\0"	---	862	/* 809 */ "F_HI23\0"	---
863	/* 816 */ "COP23\0"	---	863	/* 816 */ "COP23\0"	---
864	/* 822 */ "FCR23\0"	---	864	/* 822 */ "FCR23\0"	---
865	/* 828 */ "HWR23\0"	---	865	/* 828 */ "HWR23\0"	---
866	/* 834 */ "W23\0"	---	866	/* 834 */ "W23\0"	---
867	/* 838 */ "DSPOutFlag23\0"	---	867	/* 838 */ "DSPOutFlag23\0"	---
868	/* 851 */ "COP33\0"	---	868	/* 851 */ "COP33\0"	---
869	/* 857 */ "A3\0"	---	869	/* 857 */ "A3\0"	---
870	/* 860 */ "AC3\0"	---	870	/* 860 */ "AC3\0"	---
871	/* 864 */ "FCC3\0"	---	871	/* 864 */ "FCC3\0"	---
872	/* 869 */ "D3\0"	---	872	/* 869 */ "D3\0"	---
873	/* 872 */ "F3\0"	---	873	/* 872 */ "F3\0"	---
874	/* 875 */ "F_HI3\0"	---	874	/* 875 */ "F_HI3\0"	---
875	/* 881 */ "LO3\0"	---	875	/* 881 */ "LO3\0"	---
876	/* 885 */ "FCR3\0"	---	876	/* 885 */ "FCR3\0"	---
877	/* 890 */ "HWR3\0"	---	877	/* 890 */ "HWR3\0"	---
878	/* 895 */ "S3\0"	---	878	/* 895 */ "S3\0"	---
879	/* 898 */ "T3\0"	---	879	/* 898 */ "T3\0"	---
880	/* 901 */ "W3\0"	---	880	/* 901 */ "W3\0"	---
881	/* 904 */ "COP04\0"	---	881	/* 904 */ "COP04\0"	---
882	/* 910 */ "COP014\0"	---	882	/* 910 */ "COP014\0"	---
883	/* 917 */ "COP214\0"	---	883	/* 917 */ "COP214\0"	---
884	/* 924 */ "COP314\0"	---	884	/* 924 */ "COP314\0"	---
885	/* 931 */ "MSA14\0"	---	885	/* 931 */ "MSA14\0"	---
886	/* 937 */ "D14\0"	---	886	/* 937 */ "D14\0"	---
887	/* 941 */ "F14\0"	---	887	/* 941 */ "F14\0"	---
888	/* 945 */ "F_HI14\0"	---	888	/* 945 */ "F_HI14\0"	---
889	/* 952 */ "FCR14\0"	---	889	/* 952 */ "FCR14\0"	---
890	/* 958 */ "HWR14\0"	---	890	/* 958 */ "HWR14\0"	---
891	/* 964 */ "W14\0"	---	891	/* 964 */ "W14\0"	---
892	/* 968 */ "COP024\0"	---	892	/* 968 */ "COP024\0"	---
893	/* 975 */ "COP224\0"	---	893	/* 975 */ "COP224\0"	---
894	/* 982 */ "COP324\0"	---	894	/* 982 */ "COP324\0"	---
895	/* 989 */ "MSA24\0"	---	895	/* 989 */ "MSA24\0"	---
896	/* 995 */ "F24\0"	---	896	/* 995 */ "F24\0"	---
897	/* 999 */ "F_HI24\0"	---	897	/* 999 */ "F_HI24\0"	---
898	/* 1006 */ "COP24\0"	---	898	/* 1006 */ "COP24\0"	---
899	/* 1012 */ "FCR24\0"	---	899	/* 1012 */ "FCR24\0"	---
900	/* 1018 */ "HWR24\0"	---	900	/* 1018 */ "HWR24\0"	---
901	/* 1024 */ "W24\0"	---	901	/* 1024 */ "W24\0"	---
902	/* 1028 */ "COP34\0"	---	902	/* 1028 */ "COP34\0"	---
903	/* 1034 */ "D10_64\0"	---	903	/* 1034 */ "D10_64\0"	---
904	/* 1041 */ "D20_64\0"	---	904	/* 1041 */ "D20_64\0"	---
905	/* 1048 */ "D30_64\0"	---	905	/* 1048 */ "D30_64\0"	---
906	/* 1055 */ "A0_64\0"	---	906	/* 1055 */ "A0_64\0"	---
907	/* 1061 */ "AC0_64\0"	---	907	/* 1061 */ "AC0_64\0"	---
908	/* 1068 */ "D0_64\0"	---	908	/* 1068 */ "D0_64\0"	---
909	/* 1074 */ "HI0_64\0"	---	909	/* 1074 */ "HI0_64\0"	---
910	/* 1081 */ "K0_64\0"	---	910	/* 1081 */ "K0_64\0"	---
911	/* 1087 */ "LO0_64\0"	---	911	/* 1087 */ "LO0_64\0"	---
912	/* 1094 */ "S0_64\0"	---	912	/* 1094 */ "S0_64\0"	---
913	/* 1100 */ "T0_64\0"	---	913	/* 1100 */ "T0_64\0"	---
914	/* 1106 */ "V0_64\0"	---	914	/* 1106 */ "V0_64\0"	---
915	/* 1112 */ "D11_64\0"	---	915	/* 1112 */ "D11_64\0"	---
916	/* 1119 */ "D21_64\0"	---	916	/* 1119 */ "D21_64\0"	---
917	/* 1126 */ "D31_64\0"	---	917	/* 1126 */ "D31_64\0"	---
918	/* 1133 */ "A1_64\0"	---	918	/* 1133 */ "A1_64\0"	---
919	/* 1139 */ "D1_64\0"	---	919	/* 1139 */ "D1_64\0"	---
920	/* 1145 */ "K1_64\0"	---	920	/* 1145 */ "K1_64\0"	---
921	/* 1151 */ "S1_64\0"	---	921	/* 1151 */ "S1_64\0"	---
922	/* 1157 */ "T1_64\0"	---	922	/* 1157 */ "T1_64\0"	---
923	/* 1163 */ "V1_64\0"	---	923	/* 1163 */ "V1_64\0"	---
924	/* 1169 */ "D12_64\0"	---	924	/* 1169 */ "D12_64\0"	---
925	/* 1176 */ "D22_64\0"	---	925	/* 1176 */ "D22_64\0"	---
926	/* 1183 */ "A2_64\0"	---	926	/* 1183 */ "A2_64\0"	---
927	/* 1189 */ "D2_64\0"	---	927	/* 1189 */ "D2_64\0"	---
928	/* 1195 */ "S2_64\0"	---	928	/* 1195 */ "S2_64\0"	---
929	/* 1201 */ "T2_64\0"	---	929	/* 1201 */ "T2_64\0"	---
930	/* 1207 */ "D13_64\0"	---	930	/* 1207 */ "D13_64\0"	---
931	/* 1214 */ "D23_64\0"	---	931	/* 1214 */ "D23_64\0"	---
932	/* 1221 */ "A3_64\0"	---	932	/* 1221 */ "A3_64\0"	---
933	/* 1227 */ "D3_64\0"	---	933	/* 1227 */ "D3_64\0"	---
934	/* 1233 */ "S3_64\0"	---	934	/* 1233 */ "S3_64\0"	---
935	/* 1239 */ "T3_64\0"	---	935	/* 1239 */ "T3_64\0"	---
936	/* 1245 */ "D14_64\0"	---	936	/* 1245 */ "D14_64\0"	---
937	/* 1252 */ "D24_64\0"	---	937	/* 1252 */ "D24_64\0"	---
938	/* 1259 */ "D4_64\0"	---	938	/* 1259 */ "D4_64\0"	---
939	/* 1265 */ "S4_64\0"	---	939	/* 1265 */ "S4_64\0"	---
940	/* 1271 */ "T4_64\0"	---	940	/* 1271 */ "T4_64\0"	---
941	/* 1277 */ "D15_64\0"	---	941	/* 1277 */ "D15_64\0"	---
942	/* 1284 */ "D25_64\0"	---	942	/* 1284 */ "D25_64\0"	---
943	/* 1291 */ "D5_64\0"	---	943	/* 1291 */ "D5_64\0"	---
944	/* 1297 */ "S5_64\0"	---	944	/* 1297 */ "S5_64\0"	---
945	/* 1303 */ "T5_64\0"	---	945	/* 1303 */ "T5_64\0"	---
946	/* 1309 */ "D16_64\0"	---	946	/* 1309 */ "D16_64\0"	---
947	/* 1316 */ "D26_64\0"	---	947	/* 1316 */ "D26_64\0"	---
948	/* 1323 */ "D6_64\0"	---	948	/* 1323 */ "D6_64\0"	---
949	/* 1329 */ "S6_64\0"	---	949	/* 1329 */ "S6_64\0"	---
950	/* 1335 */ "T6_64\0"	---	950	/* 1335 */ "T6_64\0"	---
951	/* 1341 */ "D17_64\0"	---	951	/* 1341 */ "D17_64\0"	---
952	/* 1348 */ "D27_64\0"	---	952	/* 1348 */ "D27_64\0"	---
953	/* 1355 */ "D7_64\0"	---	953	/* 1355 */ "D7_64\0"	---
954	/* 1361 */ "S7_64\0"	---	954	/* 1361 */ "S7_64\0"	---
955	/* 1367 */ "T7_64\0"	---	955	/* 1367 */ "T7_64\0"	---
956	/* 1373 */ "D18_64\0"	---	956	/* 1373 */ "D18_64\0"	---
957	/* 1380 */ "D28_64\0"	---	957	/* 1380 */ "D28_64\0"	---
958	/* 1387 */ "D8_64\0"	---	958	/* 1387 */ "D8_64\0"	---
959	/* 1393 */ "T8_64\0"	---	959	/* 1393 */ "T8_64\0"	---
960	/* 1399 */ "D19_64\0"	---	960	/* 1399 */ "D19_64\0"	---
961	/* 1406 */ "D29_64\0"	---	961	/* 1406 */ "D29_64\0"	---
962	/* 1413 */ "D9_64\0"	---	962	/* 1413 */ "D9_64\0"	---
963	/* 1419 */ "T9_64\0"	---	963	/* 1419 */ "T9_64\0"	---
964	/* 1425 */ "RA_64\0"	---	964	/* 1425 */ "RA_64\0"	---
965	/* 1431 */ "ZERO_64\0"	---	965	/* 1431 */ "ZERO_64\0"	---
966	/* 1439 */ "FP_64\0"	---	966	/* 1439 */ "FP_64\0"	---
967	/* 1445 */ "GP_64\0"	---	967	/* 1445 */ "GP_64\0"	---
968	/* 1451 */ "SP_64\0"	---	968	/* 1451 */ "SP_64\0"	---
969	/* 1457 */ "AT_64\0"	---	969	/* 1457 */ "AT_64\0"	---
970	/* 1463 */ "FCC4\0"	---	970	/* 1463 */ "FCC4\0"	---
971	/* 1468 */ "D4\0"	---	971	/* 1468 */ "D4\0"	---
972	/* 1471 */ "F4\0"	---	972	/* 1471 */ "F4\0"	---
973	/* 1474 */ "F_HI4\0"	---	973	/* 1474 */ "F_HI4\0"	---
974	/* 1480 */ "FCR4\0"	---	974	/* 1480 */ "FCR4\0"	---
975	/* 1485 */ "HWR4\0"	---	975	/* 1485 */ "HWR4\0"	---
976	/* 1490 */ "S4\0"	---	976	/* 1490 */ "S4\0"	---
977	/* 1493 */ "T4\0"	---	977	/* 1493 */ "T4\0"	---
978	/* 1496 */ "W4\0"	---	978	/* 1496 */ "W4\0"	---
979	/* 1499 */ "COP05\0"	---	979	/* 1499 */ "COP05\0"	---
980	/* 1505 */ "COP015\0"	---	980	/* 1505 */ "COP015\0"	---
981	/* 1512 */ "COP215\0"	---	981	/* 1512 */ "COP215\0"	---
982	/* 1519 */ "COP315\0"	---	982	/* 1519 */ "COP315\0"	---
983	/* 1526 */ "MSA15\0"	---	983	/* 1526 */ "MSA15\0"	---
984	/* 1532 */ "D15\0"	---	984	/* 1532 */ "D15\0"	---
985	/* 1536 */ "F15\0"	---	985	/* 1536 */ "F15\0"	---
986	/* 1540 */ "F_HI15\0"	---	986	/* 1540 */ "F_HI15\0"	---
987	/* 1547 */ "FCR15\0"	---	987	/* 1547 */ "FCR15\0"	---
988	/* 1553 */ "HWR15\0"	---	988	/* 1553 */ "HWR15\0"	---
989	/* 1559 */ "W15\0"	---	989	/* 1559 */ "W15\0"	---
990	/* 1563 */ "COP025\0"	---	990	/* 1563 */ "COP025\0"	---
991	/* 1570 */ "COP225\0"	---	991	/* 1570 */ "COP225\0"	---
992	/* 1577 */ "COP325\0"	---	992	/* 1577 */ "COP325\0"	---
993	/* 1584 */ "MSA25\0"	---	993	/* 1584 */ "MSA25\0"	---
994	/* 1590 */ "F25\0"	---	994	/* 1590 */ "F25\0"	---
995	/* 1594 */ "F_HI25\0"	---	995	/* 1594 */ "F_HI25\0"	---
996	/* 1601 */ "COP25\0"	---	996	/* 1601 */ "COP25\0"	---
997	/* 1607 */ "FCR25\0"	---	997	/* 1607 */ "FCR25\0"	---
998	/* 1613 */ "HWR25\0"	---	998	/* 1613 */ "HWR25\0"	---
999	/* 1619 */ "W25\0"	---	999	/* 1619 */ "W25\0"	---
1000	/* 1623 */ "COP35\0"	---	1000	/* 1623 */ "COP35\0"	---
1001	/* 1629 */ "FCC5\0"	---	1001	/* 1629 */ "FCC5\0"	---
1002	/* 1634 */ "D5\0"	---	1002	/* 1634 */ "D5\0"	---
1003	/* 1637 */ "F5\0"	---	1003	/* 1637 */ "F5\0"	---
1004	/* 1640 */ "F_HI5\0"	---	1004	/* 1640 */ "F_HI5\0"	---
1005	/* 1646 */ "FCR5\0"	---	1005	/* 1646 */ "FCR5\0"	---
1006	/* 1651 */ "HWR5\0"	---	1006	/* 1651 */ "HWR5\0"	---
1007	/* 1656 */ "S5\0"	---	1007	/* 1656 */ "S5\0"	---
1008	/* 1659 */ "T5\0"	---	1008	/* 1659 */ "T5\0"	---
1009	/* 1662 */ "W5\0"	---	1009	/* 1662 */ "W5\0"	---
1010	/* 1665 */ "COP06\0"	---	1010	/* 1665 */ "COP06\0"	---
1011	/* 1671 */ "COP016\0"	---	1011	/* 1671 */ "COP016\0"	---
1012	/* 1678 */ "COP216\0"	---	1012	/* 1678 */ "COP216\0"	---
1013	/* 1685 */ "COP316\0"	---	1013	/* 1685 */ "COP316\0"	---
1014	/* 1692 */ "MSA16\0"	---	1014	/* 1692 */ "MSA16\0"	---
1015	/* 1698 */ "F16\0"	---	1015	/* 1698 */ "F16\0"	---
1016	/* 1702 */ "F_HI16\0"	---	1016	/* 1702 */ "F_HI16\0"	---
1017	/* 1709 */ "FCR16\0"	---	1017	/* 1709 */ "FCR16\0"	---
1018	/* 1715 */ "HWR16\0"	---	1018	/* 1715 */ "HWR16\0"	---
1019	/* 1721 */ "W16\0"	---	1019	/* 1721 */ "W16\0"	---
1020	/* 1725 */ "COP026\0"	---	1020	/* 1725 */ "COP026\0"	---
1021	/* 1732 */ "COP226\0"	---	1021	/* 1732 */ "COP226\0"	---
1022	/* 1739 */ "COP326\0"	---	1022	/* 1739 */ "COP326\0"	---
1023	/* 1746 */ "MSA26\0"	---	1023	/* 1746 */ "MSA26\0"	---
1024	/* 1752 */ "F26\0"	---	1024	/* 1752 */ "F26\0"	---
1025	/* 1756 */ "F_HI26\0"	---	1025	/* 1756 */ "F_HI26\0"	---
1026	/* 1763 */ "COP26\0"	---	1026	/* 1763 */ "COP26\0"	---
1027	/* 1769 */ "FCR26\0"	---	1027	/* 1769 */ "FCR26\0"	---
1028	/* 1775 */ "HWR26\0"	---	1028	/* 1775 */ "HWR26\0"	---
1029	/* 1781 */ "W26\0"	---	1029	/* 1781 */ "W26\0"	---
1030	/* 1785 */ "COP36\0"	---	1030	/* 1785 */ "COP36\0"	---
1031	/* 1791 */ "FCC6\0"	---	1031	/* 1791 */ "FCC6\0"	---
1032	/* 1796 */ "D6\0"	---	1032	/* 1796 */ "D6\0"	---
1033	/* 1799 */ "F6\0"	---	1033	/* 1799 */ "F6\0"	---
1034	/* 1802 */ "F_HI6\0"	---	1034	/* 1802 */ "F_HI6\0"	---
1035	/* 1808 */ "FCR6\0"	---	1035	/* 1808 */ "FCR6\0"	---
1036	/* 1813 */ "HWR6\0"	---	1036	/* 1813 */ "HWR6\0"	---
1037	/* 1818 */ "S6\0"	---	1037	/* 1818 */ "S6\0"	---
1038	/* 1821 */ "T6\0"	---	1038	/* 1821 */ "T6\0"	---
1039	/* 1824 */ "W6\0"	---	1039	/* 1824 */ "W6\0"	---
1040	/* 1827 */ "COP07\0"	---	1040	/* 1827 */ "COP07\0"	---
1041	/* 1833 */ "COP017\0"	---	1041	/* 1833 */ "COP017\0"	---
1042	/* 1840 */ "COP217\0"	---	1042	/* 1840 */ "COP217\0"	---
1043	/* 1847 */ "COP317\0"	---	1043	/* 1847 */ "COP317\0"	---
1044	/* 1854 */ "MSA17\0"	---	1044	/* 1854 */ "MSA17\0"	---
1045	/* 1860 */ "F17\0"	---	1045	/* 1860 */ "F17\0"	---
1046	/* 1864 */ "F_HI17\0"	---	1046	/* 1864 */ "F_HI17\0"	---
1047	/* 1871 */ "FCR17\0"	---	1047	/* 1871 */ "FCR17\0"	---
1048	/* 1877 */ "HWR17\0"	---	1048	/* 1877 */ "HWR17\0"	---
1049	/* 1883 */ "W17\0"	---	1049	/* 1883 */ "W17\0"	---
1050	/* 1887 */ "COP027\0"	---	1050	/* 1887 */ "COP027\0"	---
1051	/* 1894 */ "COP227\0"	---	1051	/* 1894 */ "COP227\0"	---
1052	/* 1901 */ "COP327\0"	---	1052	/* 1901 */ "COP327\0"	---
1053	/* 1908 */ "MSA27\0"	---	1053	/* 1908 */ "MSA27\0"	---
1054	/* 1914 */ "F27\0"	---	1054	/* 1914 */ "F27\0"	---
1055	/* 1918 */ "F_HI27\0"	---	1055	/* 1918 */ "F_HI27\0"	---
1056	/* 1925 */ "COP27\0"	---	1056	/* 1925 */ "COP27\0"	---
1057	/* 1931 */ "FCR27\0"	---	1057	/* 1931 */ "FCR27\0"	---
1058	/* 1937 */ "HWR27\0"	---	1058	/* 1937 */ "HWR27\0"	---
1059	/* 1943 */ "W27\0"	---	1059	/* 1943 */ "W27\0"	---
1060	/* 1947 */ "COP37\0"	---	1060	/* 1947 */ "COP37\0"	---
1061	/* 1953 */ "FCC7\0"	---	1061	/* 1953 */ "FCC7\0"	---
1062	/* 1958 */ "D7\0"	---	1062	/* 1958 */ "D7\0"	---
1063	/* 1961 */ "F7\0"	---	1063	/* 1961 */ "F7\0"	---
1064	/* 1964 */ "F_HI7\0"	---	1064	/* 1964 */ "F_HI7\0"	---
1065	/* 1970 */ "FCR7\0"	---	1065	/* 1970 */ "FCR7\0"	---
1066	/* 1975 */ "HWR7\0"	---	1066	/* 1975 */ "HWR7\0"	---
1067	/* 1980 */ "S7\0"	---	1067	/* 1980 */ "S7\0"	---
1068	/* 1983 */ "T7\0"	---	1068	/* 1983 */ "T7\0"	---
1069	/* 1986 */ "W7\0"	---	1069	/* 1986 */ "W7\0"	---
1070	/* 1989 */ "COP08\0"	---	1070	/* 1989 */ "COP08\0"	---
1071	/* 1995 */ "COP018\0"	---	1071	/* 1995 */ "COP018\0"	---
1072	/* 2002 */ "COP218\0"	---	1072	/* 2002 */ "COP218\0"	---
1073	/* 2009 */ "COP318\0"	---	1073	/* 2009 */ "COP318\0"	---
1074	/* 2016 */ "MSA18\0"	---	1074	/* 2016 */ "MSA18\0"	---
1075	/* 2022 */ "F18\0"	---	1075	/* 2022 */ "F18\0"	---
1076	/* 2026 */ "F_HI18\0"	---	1076	/* 2026 */ "F_HI18\0"	---
1077	/* 2033 */ "FCR18\0"	---	1077	/* 2033 */ "FCR18\0"	---
1078	/* 2039 */ "HWR18\0"	---	1078	/* 2039 */ "HWR18\0"	---
1079	/* 2045 */ "W18\0"	---	1079	/* 2045 */ "W18\0"	---
1080	/* 2049 */ "COP028\0"	---	1080	/* 2049 */ "COP028\0"	---
1081	/* 2056 */ "COP228\0"	---	1081	/* 2056 */ "COP228\0"	---
1082	/* 2063 */ "COP328\0"	---	1082	/* 2063 */ "COP328\0"	---
1083	/* 2070 */ "MSA28\0"	---	1083	/* 2070 */ "MSA28\0"	---
1084	/* 2076 */ "F28\0"	---	1084	/* 2076 */ "F28\0"	---
1085	/* 2080 */ "F_HI28\0"	---	1085	/* 2080 */ "F_HI28\0"	---
1086	/* 2087 */ "COP28\0"	---	1086	/* 2087 */ "COP28\0"	---
1087	/* 2093 */ "FCR28\0"	---	1087	/* 2093 */ "FCR28\0"	---
1088	/* 2099 */ "HWR28\0"	---	1088	/* 2099 */ "HWR28\0"	---
1089	/* 2105 */ "W28\0"	---	1089	/* 2105 */ "W28\0"	---
1090	/* 2109 */ "COP38\0"	---	1090	/* 2109 */ "COP38\0"	---
1091	/* 2115 */ "MSA8\0"	---	1091	/* 2115 */ "MSA8\0"	---
1092	/* 2120 */ "D8\0"	---	1092	/* 2120 */ "D8\0"	---
1093	/* 2123 */ "F8\0"	---	1093	/* 2123 */ "F8\0"	---
1094	/* 2126 */ "F_HI8\0"	---	1094	/* 2126 */ "F_HI8\0"	---
1095	/* 2132 */ "FCR8\0"	---	1095	/* 2132 */ "FCR8\0"	---
1096	/* 2137 */ "HWR8\0"	---	1096	/* 2137 */ "HWR8\0"	---
1097	/* 2142 */ "T8\0"	---	1097	/* 2142 */ "T8\0"	---
1098	/* 2145 */ "W8\0"	---	1098	/* 2145 */ "W8\0"	---
1099	/* 2148 */ "COP09\0"	---	1099	/* 2148 */ "COP09\0"	---
1100	/* 2154 */ "COP019\0"	---	1100	/* 2154 */ "COP019\0"	---
1101	/* 2161 */ "COP219\0"	---	1101	/* 2161 */ "COP219\0"	---
1102	/* 2168 */ "COP319\0"	---	1102	/* 2168 */ "COP319\0"	---
1103	/* 2175 */ "MSA19\0"	---	1103	/* 2175 */ "MSA19\0"	---
1104	/* 2181 */ "F19\0"	---	1104	/* 2181 */ "F19\0"	---
1105	/* 2185 */ "F_HI19\0"	---	1105	/* 2185 */ "F_HI19\0"	---
1106	/* 2192 */ "FCR19\0"	---	1106	/* 2192 */ "FCR19\0"	---
1107	/* 2198 */ "HWR19\0"	---	1107	/* 2198 */ "HWR19\0"	---
1108	/* 2204 */ "W19\0"	---	1108	/* 2204 */ "W19\0"	---
1109	/* 2208 */ "DSPOutFlag16_19\0"	---	1109	/* 2208 */ "DSPOutFlag16_19\0"	---
1110	/* 2224 */ "COP029\0"	---	1110	/* 2224 */ "COP029\0"	---
1111	/* 2231 */ "COP229\0"	---	1111	/* 2231 */ "COP229\0"	---
1112	/* 2238 */ "COP329\0"	---	1112	/* 2238 */ "COP329\0"	---
1113	/* 2245 */ "MSA29\0"	---	1113	/* 2245 */ "MSA29\0"	---
1114	/* 2251 */ "F29\0"	---	1114	/* 2251 */ "F29\0"	---
1115	/* 2255 */ "F_HI29\0"	---	1115	/* 2255 */ "F_HI29\0"	---
1116	/* 2262 */ "COP29\0"	---	1116	/* 2262 */ "COP29\0"	---
1117	/* 2268 */ "FCR29\0"	---	1117	/* 2268 */ "FCR29\0"	---
1118	/* 2274 */ "HWR29\0"	---	1118	/* 2274 */ "HWR29\0"	---
1119	/* 2280 */ "W29\0"	---	1119	/* 2280 */ "W29\0"	---
1120	/* 2284 */ "COP39\0"	---	1120	/* 2284 */ "COP39\0"	---
1121	/* 2290 */ "MSA9\0"	---	1121	/* 2290 */ "MSA9\0"	---
1122	/* 2295 */ "D9\0"	---	1122	/* 2295 */ "D9\0"	---
1123	/* 2298 */ "F9\0"	---	1123	/* 2298 */ "F9\0"	---
1124	/* 2301 */ "F_HI9\0"	---	1124	/* 2301 */ "F_HI9\0"	---
1125	/* 2307 */ "FCR9\0"	---	1125	/* 2307 */ "FCR9\0"	---
1126	/* 2312 */ "HWR9\0"	---	1126	/* 2312 */ "HWR9\0"	---
1127	/* 2317 */ "T9\0"	---	1127	/* 2317 */ "T9\0"	---
1128	/* 2320 */ "W9\0"	---	1128	/* 2320 */ "W9\0"	---
1129	/* 2323 */ "RA\0"	---	1129	/* 2323 */ "RA\0"	---
1130	/* 2326 */ "PC\0"	---	1130	/* 2326 */ "PC\0"	---
1131	/* 2329 */ "DSPEFI\0"	---	1131	/* 2329 */ "DSPEFI\0"	---
1132	/* 2336 */ "ZERO\0"	---	1132	/* 2336 */ "ZERO\0"	---
1133	/* 2341 */ "FP\0"	---	1133	/* 2341 */ "FP\0"	---
1134	/* 2344 */ "GP\0"	---	1134	/* 2344 */ "GP\0"	---
1135	/* 2347 */ "SP\0"	---	1135	/* 2347 */ "SP\0"	---
1136	/* 2350 */ "MSAIR\0"	---	1136	/* 2350 */ "MSAIR\0"	---
1137	/* 2356 */ "MSACSR\0"	---	1137	/* 2356 */ "MSACSR\0"	---
1138	/* 2363 */ "AT\0"	---	1138	/* 2363 */ "AT\0"	---
1139	/* 2366 */ "DSPCCond\0"	---	1139	/* 2366 */ "DSPCCond\0"	---
1140	/* 2375 */ "MSASave\0"	---	1140	/* 2375 */ "MSASave\0"	---
1141	/* 2383 */ "DSPOutFlag\0"	---	1141	/* 2383 */ "DSPOutFlag\0"	---
1142	/* 2394 */ "MSAMap\0"	---	1142	/* 2394 */ "MSAMap\0"	---
1143	/* 2401 */ "MSAUnmap\0"	---	1143	/* 2401 */ "MSAUnmap\0"	---
1144	/* 2410 */ "DSPPos\0"	---	1144	/* 2410 */ "DSPPos\0"	---
1145	/* 2417 */ "MSAAccess\0"	---	1145	/* 2417 */ "MSAAccess\0"	---
1146	/* 2427 */ "DSPSCount\0"	---	1146	/* 2427 */ "DSPSCount\0"	---
1147	/* 2437 */ "MSARequest\0"	---	1147	/* 2437 */ "MSARequest\0"	---
1148	/* 2448 */ "MSAModify\0"	---	1148	/* 2448 */ "MSAModify\0"	---
1149	/* 2458 */ "DSPCarry\0"	---	1149	/* 2458 */ "DSPCarry\0"	---
1150	};	---	1150	};	---
1151	#ifdef __GNUC__	---	1151	#ifdef __GNUC__	---
1152	#pragma GCC diagnostic pop	---	1152	#pragma GCC diagnostic pop	---
1153	#endif	---	1153	#endif	---
1154		---	1154		---
1155	extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors	---	1155	extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors	---
1156	{ 5, 0, 0, 0, 0, 0 },	---	1156	{ 5, 0, 0, 0, 0, 0 },	---
1157	{ 2363, 1, 176, 1, 4096, 0 },	---	1157	{ 2363, 1, 176, 1, 4096, 0 },	---
1158	{ 2366, 1, 1, 1, 4097, 0 },	---	1158	{ 2366, 1, 1, 1, 4097, 0 },	---
1159	{ 2458, 1, 1, 1, 4098, 0 },	---	1159	{ 2458, 1, 1, 1, 4098, 0 },	---
1160	{ 2329, 1, 1, 1, 4099, 0 },	---	1160	{ 2329, 1, 1, 1, 4099, 0 },	---
1161	{ 2383, 117, 1, 2, 503812, 4 },	---	1161	{ 2383, 117, 1, 2, 503812, 4 },	---
1162	{ 2410, 1, 1, 1, 4105, 0 },	---	1162	{ 2410, 1, 1, 1, 4105, 0 },	---
1163	{ 2427, 1, 1, 1, 4106, 0 },	---	1163	{ 2427, 1, 1, 1, 4106, 0 },	---
1164	{ 2341, 1, 190, 1, 4107, 0 },	---	1164	{ 2341, 1, 190, 1, 4107, 0 },	---
1165	{ 2344, 1, 192, 1, 4108, 0 },	---	1165	{ 2344, 1, 192, 1, 4108, 0 },	---
1166	{ 2417, 1, 1, 1, 4109, 0 },	---	1166	{ 2417, 1, 1, 1, 4109, 0 },	---
1167	{ 2356, 1, 1, 1, 4110, 0 },	---	1167	{ 2356, 1, 1, 1, 4110, 0 },	---
1168	{ 2350, 1, 1, 1, 4111, 0 },	---	1168	{ 2350, 1, 1, 1, 4111, 0 },	---
1169	{ 2394, 1, 1, 1, 4112, 0 },	---	1169	{ 2394, 1, 1, 1, 4112, 0 },	---
1170	{ 2448, 1, 1, 1, 4113, 0 },	---	1170	{ 2448, 1, 1, 1, 4113, 0 },	---
1171	{ 2437, 1, 1, 1, 4114, 0 },	---	1171	{ 2437, 1, 1, 1, 4114, 0 },	---
1172	{ 2375, 1, 1, 1, 4115, 0 },	---	1172	{ 2375, 1, 1, 1, 4115, 0 },	---
1173	{ 2401, 1, 1, 1, 4116, 0 },	---	1173	{ 2401, 1, 1, 1, 4116, 0 },	---
1174	{ 2326, 1, 1, 1, 4117, 0 },	---	1174	{ 2326, 1, 1, 1, 4117, 0 },	---
1175	{ 2323, 1, 194, 1, 4118, 0 },	---	1175	{ 2323, 1, 194, 1, 4118, 0 },	---
1176	{ 2347, 1, 196, 1, 4119, 0 },	---	1176	{ 2347, 1, 196, 1, 4119, 0 },	---
1177	{ 2336, 1, 198, 1, 4120, 0 },	---	1177	{ 2336, 1, 198, 1, 4120, 0 },	---
1178	{ 197, 1, 198, 1, 4121, 0 },	---	1178	{ 197, 1, 198, 1, 4121, 0 },	---
1179	{ 455, 1, 198, 1, 4122, 0 },	---	1179	{ 455, 1, 198, 1, 4122, 0 },	---
1180	{ 659, 1, 198, 1, 4123, 0 },	---	1180	{ 659, 1, 198, 1, 4123, 0 },	---
1181	{ 857, 1, 198, 1, 4124, 0 },	---	1181	{ 857, 1, 198, 1, 4124, 0 },	---
1182	{ 200, 68, 198, 9, 495645, 10 },	---	1182	{ 200, 68, 198, 9, 495645, 10 },	---
1183	{ 458, 68, 1, 9, 495647, 10 },	---	1183	{ 458, 68, 1, 9, 495647, 10 },	---
1184	{ 662, 68, 1, 9, 495649, 10 },	---	1184	{ 662, 68, 1, 9, 495649, 10 },	---
1185	{ 860, 68, 1, 9, 495651, 10 },	---	1185	{ 860, 68, 1, 9, 495651, 10 },	---
1186	{ 1457, 115, 1, 0, 4096, 2 },	---	1186	{ 1457, 115, 1, 0, 4096, 2 },	---
1187	{ 0, 1, 1, 1, 4133, 0 },	---	1187	{ 0, 1, 1, 1, 4133, 0 },	---
1188	{ 258, 1, 1, 1, 4134, 0 },	---	1188	{ 258, 1, 1, 1, 4134, 0 },	---
1189	{ 516, 1, 1, 1, 4135, 0 },	---	1189	{ 516, 1, 1, 1, 4135, 0 },	---
1190	{ 714, 1, 1, 1, 4136, 0 },	---	1190	{ 714, 1, 1, 1, 4136, 0 },	---
1191	{ 904, 1, 1, 1, 4137, 0 },	---	1191	{ 904, 1, 1, 1, 4137, 0 },	---
1192	{ 1499, 1, 1, 1, 4138, 0 },	---	1192	{ 1499, 1, 1, 1, 4138, 0 },	---
1193	{ 1665, 1, 1, 1, 4139, 0 },	---	1193	{ 1665, 1, 1, 1, 4139, 0 },	---
1194	{ 1827, 1, 1, 1, 4140, 0 },	---	1194	{ 1827, 1, 1, 1, 4140, 0 },	---
1195	{ 1989, 1, 1, 1, 4141, 0 },	---	1195	{ 1989, 1, 1, 1, 4141, 0 },	---
1196	{ 2148, 1, 1, 1, 4142, 0 },	---	1196	{ 2148, 1, 1, 1, 4142, 0 },	---
1197	{ 102, 1, 1, 1, 4143, 0 },	---	1197	{ 102, 1, 1, 1, 4143, 0 },	---
1198	{ 360, 1, 1, 1, 4144, 0 },	---	1198	{ 360, 1, 1, 1, 4144, 0 },	---
1199	{ 618, 1, 1, 1, 4145, 0 },	---	1199	{ 618, 1, 1, 1, 4145, 0 },	---
1200	{ 816, 1, 1, 1, 4146, 0 },	---	1200	{ 816, 1, 1, 1, 4146, 0 },	---
1201	{ 1006, 1, 1, 1, 4147, 0 },	---	1201	{ 1006, 1, 1, 1, 4147, 0 },	---
1202	{ 1601, 1, 1, 1, 4148, 0 },	---	1202	{ 1601, 1, 1, 1, 4148, 0 },	---
1203	{ 1763, 1, 1, 1, 4149, 0 },	---	1203	{ 1763, 1, 1, 1, 4149, 0 },	---
1204	{ 1925, 1, 1, 1, 4150, 0 },	---	1204	{ 1925, 1, 1, 1, 4150, 0 },	---
1205	{ 2087, 1, 1, 1, 4151, 0 },	---	1205	{ 2087, 1, 1, 1, 4151, 0 },	---
1206	{ 2262, 1, 1, 1, 4152, 0 },	---	1206	{ 2262, 1, 1, 1, 4152, 0 },	---
1207	{ 175, 1, 1, 1, 4153, 0 },	---	1207	{ 175, 1, 1, 1, 4153, 0 },	---
1208	{ 433, 1, 1, 1, 4154, 0 },	---	1208	{ 433, 1, 1, 1, 4154, 0 },	---
1209	{ 653, 1, 1, 1, 4155, 0 },	---	1209	{ 653, 1, 1, 1, 4155, 0 },	---
1210	{ 851, 1, 1, 1, 4156, 0 },	---	1210	{ 851, 1, 1, 1, 4156, 0 },	---
1211	{ 1028, 1, 1, 1, 4157, 0 },	---	1211	{ 1028, 1, 1, 1, 4157, 0 },	---
1212	{ 1623, 1, 1, 1, 4158, 0 },	---	1212	{ 1623, 1, 1, 1, 4158, 0 },	---
1213	{ 1785, 1, 1, 1, 4159, 0 },	---	1213	{ 1785, 1, 1, 1, 4159, 0 },	---
1214	{ 1947, 1, 1, 1, 4160, 0 },	---	1214	{ 1947, 1, 1, 1, 4160, 0 },	---
1215	{ 2109, 1, 1, 1, 4161, 0 },	---	1215	{ 2109, 1, 1, 1, 4161, 0 },	---
1216	{ 2284, 1, 1, 1, 4162, 0 },	---	1216	{ 2284, 1, 1, 1, 4162, 0 },	---
1217	{ 6, 1, 1, 1, 4163, 0 },	---	1217	{ 6, 1, 1, 1, 4163, 0 },	---
1218	{ 264, 1, 1, 1, 4164, 0 },	---	1218	{ 264, 1, 1, 1, 4164, 0 },	---
1219	{ 522, 1, 1, 1, 4165, 0 },	---	1219	{ 522, 1, 1, 1, 4165, 0 },	---
1220	{ 720, 1, 1, 1, 4166, 0 },	---	1220	{ 720, 1, 1, 1, 4166, 0 },	---
1221	{ 910, 1, 1, 1, 4167, 0 },	---	1221	{ 910, 1, 1, 1, 4167, 0 },	---
1222	{ 1505, 1, 1, 1, 4168, 0 },	---	1222	{ 1505, 1, 1, 1, 4168, 0 },	---
1223	{ 1671, 1, 1, 1, 4169, 0 },	---	1223	{ 1671, 1, 1, 1, 4169, 0 },	---
1224	{ 1833, 1, 1, 1, 4170, 0 },	---	1224	{ 1833, 1, 1, 1, 4170, 0 },	---
1225	{ 1995, 1, 1, 1, 4171, 0 },	---	1225	{ 1995, 1, 1, 1, 4171, 0 },	---
1226	{ 2154, 1, 1, 1, 4172, 0 },	---	1226	{ 2154, 1, 1, 1, 4172, 0 },	---
1227	{ 64, 1, 1, 1, 4173, 0 },	---	1227	{ 64, 1, 1, 1, 4173, 0 },	---
1228	{ 322, 1, 1, 1, 4174, 0 },	---	1228	{ 322, 1, 1, 1, 4174, 0 },	---
1229	{ 580, 1, 1, 1, 4175, 0 },	---	1229	{ 580, 1, 1, 1, 4175, 0 },	---
1230	{ 778, 1, 1, 1, 4176, 0 },	---	1230	{ 778, 1, 1, 1, 4176, 0 },	---
1231	{ 968, 1, 1, 1, 4177, 0 },	---	1231	{ 968, 1, 1, 1, 4177, 0 },	---
1232	{ 1563, 1, 1, 1, 4178, 0 },	---	1232	{ 1563, 1, 1, 1, 4178, 0 },	---
1233	{ 1725, 1, 1, 1, 4179, 0 },	---	1233	{ 1725, 1, 1, 1, 4179, 0 },	---
1234	{ 1887, 1, 1, 1, 4180, 0 },	---	1234	{ 1887, 1, 1, 1, 4180, 0 },	---
1235	{ 2049, 1, 1, 1, 4181, 0 },	---	1235	{ 2049, 1, 1, 1, 4181, 0 },	---
1236	{ 2224, 1, 1, 1, 4182, 0 },	---	1236	{ 2224, 1, 1, 1, 4182, 0 },	---
1237	{ 137, 1, 1, 1, 4183, 0 },	---	1237	{ 137, 1, 1, 1, 4183, 0 },	---
1238	{ 395, 1, 1, 1, 4184, 0 },	---	1238	{ 395, 1, 1, 1, 4184, 0 },	---
1239	{ 13, 1, 1, 1, 4185, 0 },	---	1239	{ 13, 1, 1, 1, 4185, 0 },	---
1240	{ 271, 1, 1, 1, 4186, 0 },	---	1240	{ 271, 1, 1, 1, 4186, 0 },	---
1241	{ 529, 1, 1, 1, 4187, 0 },	---	1241	{ 529, 1, 1, 1, 4187, 0 },	---
1242	{ 727, 1, 1, 1, 4188, 0 },	---	1242	{ 727, 1, 1, 1, 4188, 0 },	---
1243	{ 917, 1, 1, 1, 4189, 0 },	---	1243	{ 917, 1, 1, 1, 4189, 0 },	---
1244	{ 1512, 1, 1, 1, 4190, 0 },	---	1244	{ 1512, 1, 1, 1, 4190, 0 },	---
1245	{ 1678, 1, 1, 1, 4191, 0 },	---	1245	{ 1678, 1, 1, 1, 4191, 0 },	---
1246	{ 1840, 1, 1, 1, 4192, 0 },	---	1246	{ 1840, 1, 1, 1, 4192, 0 },	---
1247	{ 2002, 1, 1, 1, 4193, 0 },	---	1247	{ 2002, 1, 1, 1, 4193, 0 },	---
1248	{ 2161, 1, 1, 1, 4194, 0 },	---	1248	{ 2161, 1, 1, 1, 4194, 0 },	---
1249	{ 71, 1, 1, 1, 4195, 0 },	---	1249	{ 71, 1, 1, 1, 4195, 0 },	---
1250	{ 329, 1, 1, 1, 4196, 0 },	---	1250	{ 329, 1, 1, 1, 4196, 0 },	---
1251	{ 587, 1, 1, 1, 4197, 0 },	---	1251	{ 587, 1, 1, 1, 4197, 0 },	---
1252	{ 785, 1, 1, 1, 4198, 0 },	---	1252	{ 785, 1, 1, 1, 4198, 0 },	---
1253	{ 975, 1, 1, 1, 4199, 0 },	---	1253	{ 975, 1, 1, 1, 4199, 0 },	---
1254	{ 1570, 1, 1, 1, 4200, 0 },	---	1254	{ 1570, 1, 1, 1, 4200, 0 },	---
1255	{ 1732, 1, 1, 1, 4201, 0 },	---	1255	{ 1732, 1, 1, 1, 4201, 0 },	---
1256	{ 1894, 1, 1, 1, 4202, 0 },	---	1256	{ 1894, 1, 1, 1, 4202, 0 },	---
1257	{ 2056, 1, 1, 1, 4203, 0 },	---	1257	{ 2056, 1, 1, 1, 4203, 0 },	---
1258	{ 2231, 1, 1, 1, 4204, 0 },	---	1258	{ 2231, 1, 1, 1, 4204, 0 },	---
1259	{ 144, 1, 1, 1, 4205, 0 },	---	1259	{ 144, 1, 1, 1, 4205, 0 },	---
1260	{ 402, 1, 1, 1, 4206, 0 },	---	1260	{ 402, 1, 1, 1, 4206, 0 },	---
1261	{ 20, 1, 1, 1, 4207, 0 },	---	1261	{ 20, 1, 1, 1, 4207, 0 },	---
1262	{ 278, 1, 1, 1, 4208, 0 },	---	1262	{ 278, 1, 1, 1, 4208, 0 },	---
1263	{ 536, 1, 1, 1, 4209, 0 },	---	1263	{ 536, 1, 1, 1, 4209, 0 },	---
1264	{ 734, 1, 1, 1, 4210, 0 },	---	1264	{ 734, 1, 1, 1, 4210, 0 },	---
1265	{ 924, 1, 1, 1, 4211, 0 },	---	1265	{ 924, 1, 1, 1, 4211, 0 },	---
1266	{ 1519, 1, 1, 1, 4212, 0 },	---	1266	{ 1519, 1, 1, 1, 4212, 0 },	---
1267	{ 1685, 1, 1, 1, 4213, 0 },	---	1267	{ 1685, 1, 1, 1, 4213, 0 },	---
1268	{ 1847, 1, 1, 1, 4214, 0 },	---	1268	{ 1847, 1, 1, 1, 4214, 0 },	---
1269	{ 2009, 1, 1, 1, 4215, 0 },	---	1269	{ 2009, 1, 1, 1, 4215, 0 },	---
1270	{ 2168, 1, 1, 1, 4216, 0 },	---	1270	{ 2168, 1, 1, 1, 4216, 0 },	---
1271	{ 78, 1, 1, 1, 4217, 0 },	---	1271	{ 78, 1, 1, 1, 4217, 0 },	---
1272	{ 336, 1, 1, 1, 4218, 0 },	---	1272	{ 336, 1, 1, 1, 4218, 0 },	---
1273	{ 594, 1, 1, 1, 4219, 0 },	---	1273	{ 594, 1, 1, 1, 4219, 0 },	---
1274	{ 792, 1, 1, 1, 4220, 0 },	---	1274	{ 792, 1, 1, 1, 4220, 0 },	---
1275	{ 982, 1, 1, 1, 4221, 0 },	---	1275	{ 982, 1, 1, 1, 4221, 0 },	---
1276	{ 1577, 1, 1, 1, 4222, 0 },	---	1276	{ 1577, 1, 1, 1, 4222, 0 },	---
1277	{ 1739, 1, 1, 1, 4223, 0 },	---	1277	{ 1739, 1, 1, 1, 4223, 0 },	---
1278	{ 1901, 1, 1, 1, 4224, 0 },	---	1278	{ 1901, 1, 1, 1, 4224, 0 },	---
1279	{ 2063, 1, 1, 1, 4225, 0 },	---	1279	{ 2063, 1, 1, 1, 4225, 0 },	---
1280	{ 2238, 1, 1, 1, 4226, 0 },	---	1280	{ 2238, 1, 1, 1, 4226, 0 },	---
1281	{ 151, 1, 1, 1, 4227, 0 },	---	1281	{ 151, 1, 1, 1, 4227, 0 },	---
1282	{ 409, 1, 1, 1, 4228, 0 },	---	1282	{ 409, 1, 1, 1, 4228, 0 },	---
1283	{ 209, 128, 1, 9, 495749, 10 },	---	1283	{ 209, 128, 1, 9, 495749, 10 },	---
1284	{ 467, 131, 1, 9, 495751, 10 },	---	1284	{ 467, 131, 1, 9, 495751, 10 },	---
1285	{ 671, 134, 1, 9, 495753, 10 },	---	1285	{ 671, 134, 1, 9, 495753, 10 },	---
1286	{ 869, 137, 1, 9, 495755, 10 },	---	1286	{ 869, 137, 1, 9, 495755, 10 },	---
1287	{ 1468, 140, 1, 9, 495757, 10 },	---	1287	{ 1468, 140, 1, 9, 495757, 10 },	---
1288	{ 1634, 143, 1, 9, 495759, 10 },	---	1288	{ 1634, 143, 1, 9, 495759, 10 },	---
1289	{ 1796, 146, 1, 9, 495761, 10 },	---	1289	{ 1796, 146, 1, 9, 495761, 10 },	---
1290	{ 1958, 149, 1, 9, 495763, 10 },	---	1290	{ 1958, 149, 1, 9, 495763, 10 },	---
1291	{ 2120, 152, 1, 9, 495765, 10 },	---	1291	{ 2120, 152, 1, 9, 495765, 10 },	---
1292	{ 2295, 155, 1, 9, 495767, 10 },	---	1292	{ 2295, 155, 1, 9, 495767, 10 },	---
1293	{ 33, 158, 1, 9, 495769, 10 },	---	1293	{ 33, 158, 1, 9, 495769, 10 },	---
1294	{ 291, 161, 1, 9, 495771, 10 },	---	1294	{ 291, 161, 1, 9, 495771, 10 },	---
1295	{ 549, 164, 1, 9, 495773, 10 },	---	1295	{ 549, 164, 1, 9, 495773, 10 },	---
1296	{ 747, 167, 1, 9, 495775, 10 },	---	1296	{ 747, 167, 1, 9, 495775, 10 },	---
1297	{ 937, 170, 1, 9, 495777, 10 },	---	1297	{ 937, 170, 1, 9, 495777, 10 },	---
1298	{ 1532, 173, 1, 9, 495779, 10 },	---	1298	{ 1532, 173, 1, 9, 495779, 10 },	---
1299	{ 124, 1, 28, 1, 4101, 0 },	---	1299	{ 124, 1, 28, 1, 4101, 0 },	---
1300	{ 382, 1, 26, 1, 4102, 0 },	---	1300	{ 382, 1, 26, 1, 4102, 0 },	---
1301	{ 640, 1, 24, 1, 4103, 0 },	---	1301	{ 640, 1, 24, 1, 4103, 0 },	---
1302	{ 838, 1, 22, 1, 4104, 0 },	---	1302	{ 838, 1, 22, 1, 4104, 0 },	---
1303	{ 212, 1, 39, 1, 4229, 0 },	---	1303	{ 212, 1, 39, 1, 4229, 0 },	---
1304	{ 470, 1, 43, 1, 4230, 0 },	---	1304	{ 470, 1, 43, 1, 4230, 0 },	---
1305	{ 674, 1, 43, 1, 4231, 0 },	---	1305	{ 674, 1, 43, 1, 4231, 0 },	---
1306	{ 872, 1, 47, 1, 4232, 0 },	---	1306	{ 872, 1, 47, 1, 4232, 0 },	---
1307	{ 1471, 1, 47, 1, 4233, 0 },	---	1307	{ 1471, 1, 47, 1, 4233, 0 },	---
1308	{ 1637, 1, 51, 1, 4234, 0 },	---	1308	{ 1637, 1, 51, 1, 4234, 0 },	---
1309	{ 1799, 1, 51, 1, 4235, 0 },	---	1309	{ 1799, 1, 51, 1, 4235, 0 },	---
1310	{ 1961, 1, 55, 1, 4236, 0 },	---	1310	{ 1961, 1, 55, 1, 4236, 0 },	---
1311	{ 2123, 1, 55, 1, 4237, 0 },	---	1311	{ 2123, 1, 55, 1, 4237, 0 },	---
1312	{ 2298, 1, 59, 1, 4238, 0 },	---	1312	{ 2298, 1, 59, 1, 4238, 0 },	---
1313	{ 37, 1, 59, 1, 4239, 0 },	---	1313	{ 37, 1, 59, 1, 4239, 0 },	---
1314	{ 295, 1, 63, 1, 4240, 0 },	---	1314	{ 295, 1, 63, 1, 4240, 0 },	---
1315	{ 553, 1, 63, 1, 4241, 0 },	---	1315	{ 553, 1, 63, 1, 4241, 0 },	---
1316	{ 751, 1, 67, 1, 4242, 0 },	---	1316	{ 751, 1, 67, 1, 4242, 0 },	---
1317	{ 941, 1, 67, 1, 4243, 0 },	---	1317	{ 941, 1, 67, 1, 4243, 0 },	---
1318	{ 1536, 1, 71, 1, 4244, 0 },	---	1318	{ 1536, 1, 71, 1, 4244, 0 },	---
1319	{ 1698, 1, 71, 1, 4245, 0 },	---	1319	{ 1698, 1, 71, 1, 4245, 0 },	---
1320	{ 1860, 1, 75, 1, 4246, 0 },	---	1320	{ 1860, 1, 75, 1, 4246, 0 },	---
1321	{ 2022, 1, 75, 1, 4247, 0 },	---	1321	{ 2022, 1, 75, 1, 4247, 0 },	---
1322	{ 2181, 1, 79, 1, 4248, 0 },	---	1322	{ 2181, 1, 79, 1, 4248, 0 },	---
1323	{ 91, 1, 79, 1, 4249, 0 },	---	1323	{ 91, 1, 79, 1, 4249, 0 },	---
1324	{ 349, 1, 83, 1, 4250, 0 },	---	1324	{ 349, 1, 83, 1, 4250, 0 },	---
1325	{ 607, 1, 83, 1, 4251, 0 },	---	1325	{ 607, 1, 83, 1, 4251, 0 },	---
1326	{ 805, 1, 87, 1, 4252, 0 },	---	1326	{ 805, 1, 87, 1, 4252, 0 },	---
1327	{ 995, 1, 87, 1, 4253, 0 },	---	1327	{ 995, 1, 87, 1, 4253, 0 },	---
1328	{ 1590, 1, 91, 1, 4254, 0 },	---	1328	{ 1590, 1, 91, 1, 4254, 0 },	---
1329	{ 1752, 1, 91, 1, 4255, 0 },	---	1329	{ 1752, 1, 91, 1, 4255, 0 },	---
1330	{ 1914, 1, 95, 1, 4256, 0 },	---	1330	{ 1914, 1, 95, 1, 4256, 0 },	---
1331	{ 2076, 1, 95, 1, 4257, 0 },	---	1331	{ 2076, 1, 95, 1, 4257, 0 },	---
1332	{ 2251, 1, 99, 1, 4258, 0 },	---	1332	{ 2251, 1, 99, 1, 4258, 0 },	---
1333	{ 164, 1, 99, 1, 4259, 0 },	---	1333	{ 164, 1, 99, 1, 4259, 0 },	---
1334	{ 422, 1, 103, 1, 4260, 0 },	---	1334	{ 422, 1, 103, 1, 4260, 0 },	---
1335	{ 204, 1, 1, 1, 4261, 0 },	---	1335	{ 204, 1, 1, 1, 4261, 0 },	---
1336	{ 462, 1, 1, 1, 4262, 0 },	---	1336	{ 462, 1, 1, 1, 4262, 0 },	---
1337	{ 666, 1, 1, 1, 4263, 0 },	---	1337	{ 666, 1, 1, 1, 4263, 0 },	---
1338	{ 864, 1, 1, 1, 4264, 0 },	---	1338	{ 864, 1, 1, 1, 4264, 0 },	---
1339	{ 1463, 1, 1, 1, 4265, 0 },	---	1339	{ 1463, 1, 1, 1, 4265, 0 },	---
1340	{ 1629, 1, 1, 1, 4266, 0 },	---	1340	{ 1629, 1, 1, 1, 4266, 0 },	---
1341	{ 1791, 1, 1, 1, 4267, 0 },	---	1341	{ 1791, 1, 1, 1, 4267, 0 },	---
1342	{ 1953, 1, 1, 1, 4268, 0 },	---	1342	{ 1953, 1, 1, 1, 4268, 0 },	---
1343	{ 236, 1, 1, 1, 4269, 0 },	---	1343	{ 236, 1, 1, 1, 4269, 0 },	---
1344	{ 494, 1, 1, 1, 4270, 0 },	---	1344	{ 494, 1, 1, 1, 4270, 0 },	---
1345	{ 695, 1, 1, 1, 4271, 0 },	---	1345	{ 695, 1, 1, 1, 4271, 0 },	---
1346	{ 885, 1, 1, 1, 4272, 0 },	---	1346	{ 885, 1, 1, 1, 4272, 0 },	---
1347	{ 1480, 1, 1, 1, 4273, 0 },	---	1347	{ 1480, 1, 1, 1, 4273, 0 },	---
1348	{ 1646, 1, 1, 1, 4274, 0 },	---	1348	{ 1646, 1, 1, 1, 4274, 0 },	---
1349	{ 1808, 1, 1, 1, 4275, 0 },	---	1349	{ 1808, 1, 1, 1, 4275, 0 },	---
1350	{ 1970, 1, 1, 1, 4276, 0 },	---	1350	{ 1970, 1, 1, 1, 4276, 0 },	---
1351	{ 2132, 1, 1, 1, 4277, 0 },	---	1351	{ 2132, 1, 1, 1, 4277, 0 },	---
1352	{ 2307, 1, 1, 1, 4278, 0 },	---	1352	{ 2307, 1, 1, 1, 4278, 0 },	---
1353	{ 48, 1, 1, 1, 4279, 0 },	---	1353	{ 48, 1, 1, 1, 4279, 0 },	---
1354	{ 306, 1, 1, 1, 4280, 0 },	---	1354	{ 306, 1, 1, 1, 4280, 0 },	---
1355	{ 564, 1, 1, 1, 4281, 0 },	---	1355	{ 564, 1, 1, 1, 4281, 0 },	---
1356	{ 762, 1, 1, 1, 4282, 0 },	---	1356	{ 762, 1, 1, 1, 4282, 0 },	---
1357	{ 952, 1, 1, 1, 4283, 0 },	---	1357	{ 952, 1, 1, 1, 4283, 0 },	---
1358	{ 1547, 1, 1, 1, 4284, 0 },	---	1358	{ 1547, 1, 1, 1, 4284, 0 },	---
1359	{ 1709, 1, 1, 1, 4285, 0 },	---	1359	{ 1709, 1, 1, 1, 4285, 0 },	---
1360	{ 1871, 1, 1, 1, 4286, 0 },	---	1360	{ 1871, 1, 1, 1, 4286, 0 },	---
1361	{ 2033, 1, 1, 1, 4287, 0 },	---	1361	{ 2033, 1, 1, 1, 4287, 0 },	---
1362	{ 2192, 1, 1, 1, 4288, 0 },	---	1362	{ 2192, 1, 1, 1, 4288, 0 },	---
1363	{ 108, 1, 1, 1, 4289, 0 },	---	1363	{ 108, 1, 1, 1, 4289, 0 },	---
1364	{ 366, 1, 1, 1, 4290, 0 },	---	1364	{ 366, 1, 1, 1, 4290, 0 },	---
1365	{ 624, 1, 1, 1, 4291, 0 },	---	1365	{ 624, 1, 1, 1, 4291, 0 },	---
1366	{ 822, 1, 1, 1, 4292, 0 },	---	1366	{ 822, 1, 1, 1, 4292, 0 },	---
1367	{ 1012, 1, 1, 1, 4293, 0 },	---	1367	{ 1012, 1, 1, 1, 4293, 0 },	---
1368	{ 1607, 1, 1, 1, 4294, 0 },	---	1368	{ 1607, 1, 1, 1, 4294, 0 },	---
1369	{ 1769, 1, 1, 1, 4295, 0 },	---	1369	{ 1769, 1, 1, 1, 4295, 0 },	---
1370	{ 1931, 1, 1, 1, 4296, 0 },	---	1370	{ 1931, 1, 1, 1, 4296, 0 },	---
1371	{ 2093, 1, 1, 1, 4297, 0 },	---	1371	{ 2093, 1, 1, 1, 4297, 0 },	---
1372	{ 2268, 1, 1, 1, 4298, 0 },	---	1372	{ 2268, 1, 1, 1, 4298, 0 },	---
1373	{ 181, 1, 1, 1, 4299, 0 },	---	1373	{ 181, 1, 1, 1, 4299, 0 },	---
1374	{ 439, 1, 1, 1, 4300, 0 },	---	1374	{ 439, 1, 1, 1, 4300, 0 },	---
1375	{ 1439, 18, 1, 0, 4107, 2 },	---	1375	{ 1439, 18, 1, 0, 4107, 2 },	---
1376	{ 215, 1, 36, 1, 4301, 0 },	---	1376	{ 215, 1, 36, 1, 4301, 0 },	---
1377	{ 473, 1, 36, 1, 4302, 0 },	---	1377	{ 473, 1, 36, 1, 4302, 0 },	---
1378	{ 677, 1, 36, 1, 4303, 0 },	---	1378	{ 677, 1, 36, 1, 4303, 0 },	---
1379	{ 875, 1, 36, 1, 4304, 0 },	---	1379	{ 875, 1, 36, 1, 4304, 0 },	---
1380	{ 1474, 1, 36, 1, 4305, 0 },	---	1380	{ 1474, 1, 36, 1, 4305, 0 },	---
1381	{ 1640, 1, 36, 1, 4306, 0 },	---	1381	{ 1640, 1, 36, 1, 4306, 0 },	---
1382	{ 1802, 1, 36, 1, 4307, 0 },	---	1382	{ 1802, 1, 36, 1, 4307, 0 },	---
1383	{ 1964, 1, 36, 1, 4308, 0 },	---	1383	{ 1964, 1, 36, 1, 4308, 0 },	---
1384	{ 2126, 1, 36, 1, 4309, 0 },	---	1384	{ 2126, 1, 36, 1, 4309, 0 },	---
1385	{ 2301, 1, 36, 1, 4310, 0 },	---	1385	{ 2301, 1, 36, 1, 4310, 0 },	---
1386	{ 41, 1, 36, 1, 4311, 0 },	---	1386	{ 41, 1, 36, 1, 4311, 0 },	---
1387	{ 299, 1, 36, 1, 4312, 0 },	---	1387	{ 299, 1, 36, 1, 4312, 0 },	---
1388	{ 557, 1, 36, 1, 4313, 0 },	---	1388	{ 557, 1, 36, 1, 4313, 0 },	---
1389	{ 755, 1, 36, 1, 4314, 0 },	---	1389	{ 755, 1, 36, 1, 4314, 0 },	---
1390	{ 945, 1, 36, 1, 4315, 0 },	---	1390	{ 945, 1, 36, 1, 4315, 0 },	---
1391	{ 1540, 1, 36, 1, 4316, 0 },	---	1391	{ 1540, 1, 36, 1, 4316, 0 },	---
1392	{ 1702, 1, 36, 1, 4317, 0 },	---	1392	{ 1702, 1, 36, 1, 4317, 0 },	---
1393	{ 1864, 1, 36, 1, 4318, 0 },	---	1393	{ 1864, 1, 36, 1, 4318, 0 },	---
1394	{ 2026, 1, 36, 1, 4319, 0 },	---	1394	{ 2026, 1, 36, 1, 4319, 0 },	---
1395	{ 2185, 1, 36, 1, 4320, 0 },	---	1395	{ 2185, 1, 36, 1, 4320, 0 },	---
1396	{ 95, 1, 36, 1, 4321, 0 },	---	1396	{ 95, 1, 36, 1, 4321, 0 },	---
1397	{ 353, 1, 36, 1, 4322, 0 },	---	1397	{ 353, 1, 36, 1, 4322, 0 },	---
1398	{ 611, 1, 36, 1, 4323, 0 },	---	1398	{ 611, 1, 36, 1, 4323, 0 },	---
1399	{ 809, 1, 36, 1, 4324, 0 },	---	1399	{ 809, 1, 36, 1, 4324, 0 },	---
1400	{ 999, 1, 36, 1, 4325, 0 },	---	1400	{ 999, 1, 36, 1, 4325, 0 },	---
1401	{ 1594, 1, 36, 1, 4326, 0 },	---	1401	{ 1594, 1, 36, 1, 4326, 0 },	---
1402	{ 1756, 1, 36, 1, 4327, 0 },	---	1402	{ 1756, 1, 36, 1, 4327, 0 },	---
1403	{ 1918, 1, 36, 1, 4328, 0 },	---	1403	{ 1918, 1, 36, 1, 4328, 0 },	---
1404	{ 2080, 1, 36, 1, 4329, 0 },	---	1404	{ 2080, 1, 36, 1, 4329, 0 },	---
1405	{ 2255, 1, 36, 1, 4330, 0 },	---	1405	{ 2255, 1, 36, 1, 4330, 0 },	---
1406	{ 168, 1, 36, 1, 4331, 0 },	---	1406	{ 168, 1, 36, 1, 4331, 0 },	---
1407	{ 426, 1, 36, 1, 4332, 0 },	---	1407	{ 426, 1, 36, 1, 4332, 0 },	---
1408	{ 1445, 10, 1, 0, 4108, 2 },	---	1408	{ 1445, 10, 1, 0, 4108, 2 },	---
1409	{ 217, 1, 111, 1, 4126, 0 },	---	1409	{ 217, 1, 111, 1, 4126, 0 },	---
1410	{ 475, 1, 16, 1, 4128, 0 },	---	1410	{ 475, 1, 16, 1, 4128, 0 },	---
1411	{ 679, 1, 16, 1, 4130, 0 },	---	1411	{ 679, 1, 16, 1, 4130, 0 },	---
1412	{ 877, 1, 16, 1, 4132, 0 },	---	1412	{ 877, 1, 16, 1, 4132, 0 },	---
1413	{ 241, 1, 1, 1, 4333, 0 },	---	1413	{ 241, 1, 1, 1, 4333, 0 },	---
1414	{ 499, 1, 1, 1, 4334, 0 },	---	1414	{ 499, 1, 1, 1, 4334, 0 },	---
1415	{ 700, 1, 1, 1, 4335, 0 },	---	1415	{ 700, 1, 1, 1, 4335, 0 },	---
1416	{ 890, 1, 1, 1, 4336, 0 },	---	1416	{ 890, 1, 1, 1, 4336, 0 },	---
1417	{ 1485, 1, 1, 1, 4337, 0 },	---	1417	{ 1485, 1, 1, 1, 4337, 0 },	---
1418	{ 1651, 1, 1, 1, 4338, 0 },	---	1418	{ 1651, 1, 1, 1, 4338, 0 },	---
1419	{ 1813, 1, 1, 1, 4339, 0 },	---	1419	{ 1813, 1, 1, 1, 4339, 0 },	---
1420	{ 1975, 1, 1, 1, 4340, 0 },	---	1420	{ 1975, 1, 1, 1, 4340, 0 },	---
1421	{ 2137, 1, 1, 1, 4341, 0 },	---	1421	{ 2137, 1, 1, 1, 4341, 0 },	---
1422	{ 2312, 1, 1, 1, 4342, 0 },	---	1422	{ 2312, 1, 1, 1, 4342, 0 },	---
1423	{ 54, 1, 1, 1, 4343, 0 },	---	1423	{ 54, 1, 1, 1, 4343, 0 },	---
1424	{ 312, 1, 1, 1, 4344, 0 },	---	1424	{ 312, 1, 1, 1, 4344, 0 },	---
1425	{ 570, 1, 1, 1, 4345, 0 },	---	1425	{ 570, 1, 1, 1, 4345, 0 },	---
1426	{ 768, 1, 1, 1, 4346, 0 },	---	1426	{ 768, 1, 1, 1, 4346, 0 },	---
1427	{ 958, 1, 1, 1, 4347, 0 },	---	1427	{ 958, 1, 1, 1, 4347, 0 },	---
1428	{ 1553, 1, 1, 1, 4348, 0 },	---	1428	{ 1553, 1, 1, 1, 4348, 0 },	---
1429	{ 1715, 1, 1, 1, 4349, 0 },	---	1429	{ 1715, 1, 1, 1, 4349, 0 },	---
1430	{ 1877, 1, 1, 1, 4350, 0 },	---	1430	{ 1877, 1, 1, 1, 4350, 0 },	---
1431	{ 2039, 1, 1, 1, 4351, 0 },	---	1431	{ 2039, 1, 1, 1, 4351, 0 },	---
1432	{ 2198, 1, 1, 1, 4352, 0 },	---	1432	{ 2198, 1, 1, 1, 4352, 0 },	---
1433	{ 114, 1, 1, 1, 4353, 0 },	---	1433	{ 114, 1, 1, 1, 4353, 0 },	---
1434	{ 372, 1, 1, 1, 4354, 0 },	---	1434	{ 372, 1, 1, 1, 4354, 0 },	---
1435	{ 630, 1, 1, 1, 4355, 0 },	---	1435	{ 630, 1, 1, 1, 4355, 0 },	---
1436	{ 828, 1, 1, 1, 4356, 0 },	---	1436	{ 828, 1, 1, 1, 4356, 0 },	---
1437	{ 1018, 1, 1, 1, 4357, 0 },	---	1437	{ 1018, 1, 1, 1, 4357, 0 },	---
1438	{ 1613, 1, 1, 1, 4358, 0 },	---	1438	{ 1613, 1, 1, 1, 4358, 0 },	---
1439	{ 1775, 1, 1, 1, 4359, 0 },	---	1439	{ 1775, 1, 1, 1, 4359, 0 },	---
1440	{ 1937, 1, 1, 1, 4360, 0 },	---	1440	{ 1937, 1, 1, 1, 4360, 0 },	---
1441	{ 2099, 1, 1, 1, 4361, 0 },	---	1441	{ 2099, 1, 1, 1, 4361, 0 },	---
1442	{ 2274, 1, 1, 1, 4362, 0 },	---	1442	{ 2274, 1, 1, 1, 4362, 0 },	---
1443	{ 187, 1, 1, 1, 4363, 0 },	---	1443	{ 187, 1, 1, 1, 4363, 0 },	---
1444	{ 445, 1, 1, 1, 4364, 0 },	---	1444	{ 445, 1, 1, 1, 4364, 0 },	---
1445	{ 221, 1, 188, 1, 4365, 0 },	---	1445	{ 221, 1, 188, 1, 4365, 0 },	---
1446	{ 479, 1, 188, 1, 4366, 0 },	---	1446	{ 479, 1, 188, 1, 4366, 0 },	---
1447	{ 229, 1, 107, 1, 4125, 0 },	---	1447	{ 229, 1, 107, 1, 4125, 0 },	---
1448	{ 487, 1, 8, 1, 4127, 0 },	---	1448	{ 487, 1, 8, 1, 4127, 0 },	---
1449	{ 688, 1, 8, 1, 4129, 0 },	---	1449	{ 688, 1, 8, 1, 4129, 0 },	---
1450	{ 881, 1, 8, 1, 4131, 0 },	---	1450	{ 881, 1, 8, 1, 4131, 0 },	---
1451	{ 224, 1, 1, 1, 4367, 0 },	---	1451	{ 224, 1, 1, 1, 4367, 0 },	---
1452	{ 482, 1, 1, 1, 4368, 0 },	---	1452	{ 482, 1, 1, 1, 4368, 0 },	---
1453	{ 683, 1, 1, 1, 4369, 0 },	---	1453	{ 683, 1, 1, 1, 4369, 0 },	---
1454	{ 2115, 1, 1, 1, 4370, 0 },	---	1454	{ 2115, 1, 1, 1, 4370, 0 },	---
1455	{ 2290, 1, 1, 1, 4371, 0 },	---	1455	{ 2290, 1, 1, 1, 4371, 0 },	---
1456	{ 27, 1, 1, 1, 4372, 0 },	---	1456	{ 27, 1, 1, 1, 4372, 0 },	---
1457	{ 285, 1, 1, 1, 4373, 0 },	---	1457	{ 285, 1, 1, 1, 4373, 0 },	---
1458	{ 543, 1, 1, 1, 4374, 0 },	---	1458	{ 543, 1, 1, 1, 4374, 0 },	---
1459	{ 741, 1, 1, 1, 4375, 0 },	---	1459	{ 741, 1, 1, 1, 4375, 0 },	---
1460	{ 931, 1, 1, 1, 4376, 0 },	---	1460	{ 931, 1, 1, 1, 4376, 0 },	---
1461	{ 1526, 1, 1, 1, 4377, 0 },	---	1461	{ 1526, 1, 1, 1, 4377, 0 },	---
1462	{ 1692, 1, 1, 1, 4378, 0 },	---	1462	{ 1692, 1, 1, 1, 4378, 0 },	---
1463	{ 1854, 1, 1, 1, 4379, 0 },	---	1463	{ 1854, 1, 1, 1, 4379, 0 },	---
1464	{ 2016, 1, 1, 1, 4380, 0 },	---	1464	{ 2016, 1, 1, 1, 4380, 0 },	---
1465	{ 2175, 1, 1, 1, 4381, 0 },	---	1465	{ 2175, 1, 1, 1, 4381, 0 },	---
1466	{ 85, 1, 1, 1, 4382, 0 },	---	1466	{ 85, 1, 1, 1, 4382, 0 },	---
1467	{ 343, 1, 1, 1, 4383, 0 },	---	1467	{ 343, 1, 1, 1, 4383, 0 },	---
1468	{ 601, 1, 1, 1, 4384, 0 },	---	1468	{ 601, 1, 1, 1, 4384, 0 },	---
1469	{ 799, 1, 1, 1, 4385, 0 },	---	1469	{ 799, 1, 1, 1, 4385, 0 },	---
1470	{ 989, 1, 1, 1, 4386, 0 },	---	1470	{ 989, 1, 1, 1, 4386, 0 },	---
1471	{ 1584, 1, 1, 1, 4387, 0 },	---	1471	{ 1584, 1, 1, 1, 4387, 0 },	---
1472	{ 1746, 1, 1, 1, 4388, 0 },	---	1472	{ 1746, 1, 1, 1, 4388, 0 },	---
1473	{ 1908, 1, 1, 1, 4389, 0 },	---	1473	{ 1908, 1, 1, 1, 4389, 0 },	---
1474	{ 2070, 1, 1, 1, 4390, 0 },	---	1474	{ 2070, 1, 1, 1, 4390, 0 },	---
1475	{ 2245, 1, 1, 1, 4391, 0 },	---	1475	{ 2245, 1, 1, 1, 4391, 0 },	---
1476	{ 158, 1, 1, 1, 4392, 0 },	---	1476	{ 158, 1, 1, 1, 4392, 0 },	---
1477	{ 416, 1, 1, 1, 4393, 0 },	---	1477	{ 416, 1, 1, 1, 4393, 0 },	---
1478	{ 233, 1, 1, 1, 4394, 0 },	---	1478	{ 233, 1, 1, 1, 4394, 0 },	---
1479	{ 491, 1, 1, 1, 4395, 0 },	---	1479	{ 491, 1, 1, 1, 4395, 0 },	---
1480	{ 692, 1, 1, 1, 4396, 0 },	---	1480	{ 692, 1, 1, 1, 4396, 0 },	---
1481	{ 1425, 6, 1, 0, 4118, 2 },	---	1481	{ 1425, 6, 1, 0, 4118, 2 },	---
1482	{ 246, 1, 186, 1, 4397, 0 },	---	1482	{ 246, 1, 186, 1, 4397, 0 },	---
1483	{ 504, 1, 186, 1, 4398, 0 },	---	1483	{ 504, 1, 186, 1, 4398, 0 },	---
1484	{ 705, 1, 186, 1, 4399, 0 },	---	1484	{ 705, 1, 186, 1, 4399, 0 },	---
1485	{ 895, 1, 186, 1, 4400, 0 },	---	1485	{ 895, 1, 186, 1, 4400, 0 },	---
1486	{ 1490, 1, 186, 1, 4401, 0 },	---	1486	{ 1490, 1, 186, 1, 4401, 0 },	---
1487	{ 1656, 1, 186, 1, 4402, 0 },	---	1487	{ 1656, 1, 186, 1, 4402, 0 },	---
1488	{ 1818, 1, 186, 1, 4403, 0 },	---	1488	{ 1818, 1, 186, 1, 4403, 0 },	---
1489	{ 1980, 1, 186, 1, 4404, 0 },	---	1489	{ 1980, 1, 186, 1, 4404, 0 },	---
1490	{ 1451, 4, 1, 0, 4119, 2 },	---	1490	{ 1451, 4, 1, 0, 4119, 2 },	---
1491	{ 249, 1, 184, 1, 4405, 0 },	---	1491	{ 249, 1, 184, 1, 4405, 0 },	---
1492	{ 507, 1, 184, 1, 4406, 0 },	---	1492	{ 507, 1, 184, 1, 4406, 0 },	---
1493	{ 708, 1, 184, 1, 4407, 0 },	---	1493	{ 708, 1, 184, 1, 4407, 0 },	---
1494	{ 898, 1, 184, 1, 4408, 0 },	---	1494	{ 898, 1, 184, 1, 4408, 0 },	---
1495	{ 1493, 1, 184, 1, 4409, 0 },	---	1495	{ 1493, 1, 184, 1, 4409, 0 },	---
1496	{ 1659, 1, 184, 1, 4410, 0 },	---	1496	{ 1659, 1, 184, 1, 4410, 0 },	---
1497	{ 1821, 1, 184, 1, 4411, 0 },	---	1497	{ 1821, 1, 184, 1, 4411, 0 },	---
1498	{ 1983, 1, 184, 1, 4412, 0 },	---	1498	{ 1983, 1, 184, 1, 4412, 0 },	---
1499	{ 2142, 1, 184, 1, 4413, 0 },	---	1499	{ 2142, 1, 184, 1, 4413, 0 },	---
1500	{ 2317, 1, 184, 1, 4414, 0 },	---	1500	{ 2317, 1, 184, 1, 4414, 0 },	---
1501	{ 252, 1, 184, 1, 4415, 0 },	---	1501	{ 252, 1, 184, 1, 4415, 0 },	---
1502	{ 510, 1, 184, 1, 4416, 0 },	---	1502	{ 510, 1, 184, 1, 4416, 0 },	---
1503	{ 255, 180, 1, 8, 729221, 10 },	---	1503	{ 255, 180, 1, 8, 729221, 10 },	---
1504	{ 513, 180, 1, 8, 729222, 10 },	---	1504	{ 513, 180, 1, 8, 729222, 10 },	---
1505	{ 711, 180, 1, 8, 729223, 10 },	---	1505	{ 711, 180, 1, 8, 729223, 10 },	---
1506	{ 901, 180, 1, 8, 729224, 10 },	---	1506	{ 901, 180, 1, 8, 729224, 10 },	---
1507	{ 1496, 180, 1, 8, 729225, 10 },	---	1507	{ 1496, 180, 1, 8, 729225, 10 },	---
1508	{ 1662, 180, 1, 8, 729226, 10 },	---	1508	{ 1662, 180, 1, 8, 729226, 10 },	---
1509	{ 1824, 180, 1, 8, 729227, 10 },	---	1509	{ 1824, 180, 1, 8, 729227, 10 },	---
1510	{ 1986, 180, 1, 8, 729228, 10 },	---	1510	{ 1986, 180, 1, 8, 729228, 10 },	---
1511	{ 2145, 180, 1, 8, 729229, 10 },	---	1511	{ 2145, 180, 1, 8, 729229, 10 },	---
1512	{ 2320, 180, 1, 8, 729230, 10 },	---	1512	{ 2320, 180, 1, 8, 729230, 10 },	---
1513	{ 60, 180, 1, 8, 729231, 10 },	---	1513	{ 60, 180, 1, 8, 729231, 10 },	---
1514	{ 318, 180, 1, 8, 729232, 10 },	---	1514	{ 318, 180, 1, 8, 729232, 10 },	---
1515	{ 576, 180, 1, 8, 729233, 10 },	---	1515	{ 576, 180, 1, 8, 729233, 10 },	---
1516	{ 774, 180, 1, 8, 729234, 10 },	---	1516	{ 774, 180, 1, 8, 729234, 10 },	---
1517	{ 964, 180, 1, 8, 729235, 10 },	---	1517	{ 964, 180, 1, 8, 729235, 10 },	---
1518	{ 1559, 180, 1, 8, 729236, 10 },	---	1518	{ 1559, 180, 1, 8, 729236, 10 },	---
1519	{ 1721, 180, 1, 8, 729237, 10 },	---	1519	{ 1721, 180, 1, 8, 729237, 10 },	---
1520	{ 1883, 180, 1, 8, 729238, 10 },	---	1520	{ 1883, 180, 1, 8, 729238, 10 },	---
1521	{ 2045, 180, 1, 8, 729239, 10 },	---	1521	{ 2045, 180, 1, 8, 729239, 10 },	---
1522	{ 2204, 180, 1, 8, 729240, 10 },	---	1522	{ 2204, 180, 1, 8, 729240, 10 },	---
1523	{ 120, 180, 1, 8, 729241, 10 },	---	1523	{ 120, 180, 1, 8, 729241, 10 },	---
1524	{ 378, 180, 1, 8, 729242, 10 },	---	1524	{ 378, 180, 1, 8, 729242, 10 },	---
1525	{ 636, 180, 1, 8, 729243, 10 },	---	1525	{ 636, 180, 1, 8, 729243, 10 },	---
1526	{ 834, 180, 1, 8, 729244, 10 },	---	1526	{ 834, 180, 1, 8, 729244, 10 },	---
1527	{ 1024, 180, 1, 8, 729245, 10 },	---	1527	{ 1024, 180, 1, 8, 729245, 10 },	---
1528	{ 1619, 180, 1, 8, 729246, 10 },	---	1528	{ 1619, 180, 1, 8, 729246, 10 },	---
1529	{ 1781, 180, 1, 8, 729247, 10 },	---	1529	{ 1781, 180, 1, 8, 729247, 10 },	---
1530	{ 1943, 180, 1, 8, 729248, 10 },	---	1530	{ 1943, 180, 1, 8, 729248, 10 },	---
1531	{ 2105, 180, 1, 8, 729249, 10 },	---	1531	{ 2105, 180, 1, 8, 729249, 10 },	---
1532	{ 2280, 180, 1, 8, 729250, 10 },	---	1532	{ 2280, 180, 1, 8, 729250, 10 },	---
1533	{ 193, 180, 1, 8, 729251, 10 },	---	1533	{ 193, 180, 1, 8, 729251, 10 },	---
1534	{ 451, 180, 1, 8, 729252, 10 },	---	1534	{ 451, 180, 1, 8, 729252, 10 },	---
1535	{ 1431, 2, 1, 0, 4120, 2 },	---	1535	{ 1431, 2, 1, 0, 4120, 2 },	---
1536	{ 1055, 2, 1, 0, 4121, 2 },	---	1536	{ 1055, 2, 1, 0, 4121, 2 },	---
1537	{ 1133, 2, 1, 0, 4122, 2 },	---	1537	{ 1133, 2, 1, 0, 4122, 2 },	---
1538	{ 1183, 2, 1, 0, 4123, 2 },	---	1538	{ 1183, 2, 1, 0, 4123, 2 },	---
1539	{ 1221, 2, 1, 0, 4124, 2 },	---	1539	{ 1221, 2, 1, 0, 4124, 2 },	---
1540	{ 1061, 12, 1, 12, 495645, 10 },	---	1540	{ 1061, 12, 1, 12, 495645, 10 },	---
1541	{ 1068, 181, 37, 9, 729221, 10 },	---	1541	{ 1068, 181, 37, 9, 729221, 10 },	---
1542	{ 1139, 181, 37, 9, 729222, 10 },	---	1542	{ 1139, 181, 37, 9, 729222, 10 },	---
1543	{ 1189, 181, 37, 9, 729223, 10 },	---	1543	{ 1189, 181, 37, 9, 729223, 10 },	---
1544	{ 1227, 181, 37, 9, 729224, 10 },	---	1544	{ 1227, 181, 37, 9, 729224, 10 },	---
1545	{ 1259, 181, 37, 9, 729225, 10 },	---	1545	{ 1259, 181, 37, 9, 729225, 10 },	---
1546	{ 1291, 181, 37, 9, 729226, 10 },	---	1546	{ 1291, 181, 37, 9, 729226, 10 },	---
1547	{ 1323, 181, 37, 9, 729227, 10 },	---	1547	{ 1323, 181, 37, 9, 729227, 10 },	---
1548	{ 1355, 181, 37, 9, 729228, 10 },	---	1548	{ 1355, 181, 37, 9, 729228, 10 },	---
1549	{ 1387, 181, 37, 9, 729229, 10 },	---	1549	{ 1387, 181, 37, 9, 729229, 10 },	---
1550	{ 1413, 181, 37, 9, 729230, 10 },	---	1550	{ 1413, 181, 37, 9, 729230, 10 },	---
1551	{ 1034, 181, 37, 9, 729231, 10 },	---	1551	{ 1034, 181, 37, 9, 729231, 10 },	---
1552	{ 1112, 181, 37, 9, 729232, 10 },	---	1552	{ 1112, 181, 37, 9, 729232, 10 },	---
1553	{ 1169, 181, 37, 9, 729233, 10 },	---	1553	{ 1169, 181, 37, 9, 729233, 10 },	---
1554	{ 1207, 181, 37, 9, 729234, 10 },	---	1554	{ 1207, 181, 37, 9, 729234, 10 },	---
1555	{ 1245, 181, 37, 9, 729235, 10 },	---	1555	{ 1245, 181, 37, 9, 729235, 10 },	---
1556	{ 1277, 181, 37, 9, 729236, 10 },	---	1556	{ 1277, 181, 37, 9, 729236, 10 },	---
1557	{ 1309, 181, 37, 9, 729237, 10 },	---	1557	{ 1309, 181, 37, 9, 729237, 10 },	---
1558	{ 1341, 181, 37, 9, 729238, 10 },	---	1558	{ 1341, 181, 37, 9, 729238, 10 },	---
1559	{ 1373, 181, 37, 9, 729239, 10 },	---	1559	{ 1373, 181, 37, 9, 729239, 10 },	---
1560	{ 1399, 181, 37, 9, 729240, 10 },	---	1560	{ 1399, 181, 37, 9, 729240, 10 },	---
1561	{ 1041, 181, 37, 9, 729241, 10 },	---	1561	{ 1041, 181, 37, 9, 729241, 10 },	---
1562	{ 1119, 181, 37, 9, 729242, 10 },	---	1562	{ 1119, 181, 37, 9, 729242, 10 },	---
1563	{ 1176, 181, 37, 9, 729243, 10 },	---	1563	{ 1176, 181, 37, 9, 729243, 10 },	---
1564	{ 1214, 181, 37, 9, 729244, 10 },	---	1564	{ 1214, 181, 37, 9, 729244, 10 },	---
1565	{ 1252, 181, 37, 9, 729245, 10 },	---	1565	{ 1252, 181, 37, 9, 729245, 10 },	---
1566	{ 1284, 181, 37, 9, 729246, 10 },	---	1566	{ 1284, 181, 37, 9, 729246, 10 },	---
1567	{ 1316, 181, 37, 9, 729247, 10 },	---	1567	{ 1316, 181, 37, 9, 729247, 10 },	---
1568	{ 1348, 181, 37, 9, 729248, 10 },	---	1568	{ 1348, 181, 37, 9, 729248, 10 },	---
1569	{ 1380, 181, 37, 9, 729249, 10 },	---	1569	{ 1380, 181, 37, 9, 729249, 10 },	---
1570	{ 1406, 181, 37, 9, 729250, 10 },	---	1570	{ 1406, 181, 37, 9, 729250, 10 },	---
1571	{ 1048, 181, 37, 9, 729251, 10 },	---	1571	{ 1048, 181, 37, 9, 729251, 10 },	---
1572	{ 1126, 181, 37, 9, 729252, 10 },	---	1572	{ 1126, 181, 37, 9, 729252, 10 },	---
1573	{ 2208, 1, 0, 1, 4100, 0 },	---	1573	{ 2208, 1, 0, 1, 4100, 0 },	---
1574	{ 1074, 20, 113, 0, 4126, 2 },	---	1574	{ 1074, 20, 113, 0, 4126, 2 },	---
1575	{ 1081, 30, 1, 0, 4365, 2 },	---	1575	{ 1081, 30, 1, 0, 4365, 2 },	---
1576	{ 1145, 30, 1, 0, 4366, 2 },	---	1576	{ 1145, 30, 1, 0, 4366, 2 },	---
1577	{ 1087, 30, 109, 0, 4125, 2 },	---	1577	{ 1087, 30, 109, 0, 4125, 2 },	---
1578	{ 1094, 32, 1, 0, 4397, 2 },	---	1578	{ 1094, 32, 1, 0, 4397, 2 },	---
1579	{ 1151, 32, 1, 0, 4398, 2 },	---	1579	{ 1151, 32, 1, 0, 4398, 2 },	---
1580	{ 1195, 32, 1, 0, 4399, 2 },	---	1580	{ 1195, 32, 1, 0, 4399, 2 },	---
1581	{ 1233, 32, 1, 0, 4400, 2 },	---	1581	{ 1233, 32, 1, 0, 4400, 2 },	---
1582	{ 1265, 32, 1, 0, 4401, 2 },	---	1582	{ 1265, 32, 1, 0, 4401, 2 },	---
1583	{ 1297, 32, 1, 0, 4402, 2 },	---	1583	{ 1297, 32, 1, 0, 4402, 2 },	---
1584	{ 1329, 32, 1, 0, 4403, 2 },	---	1584	{ 1329, 32, 1, 0, 4403, 2 },	---
1585	{ 1361, 32, 1, 0, 4404, 2 },	---	1585	{ 1361, 32, 1, 0, 4404, 2 },	---
1586	{ 1100, 34, 1, 0, 4405, 2 },	---	1586	{ 1100, 34, 1, 0, 4405, 2 },	---
1587	{ 1157, 34, 1, 0, 4406, 2 },	---	1587	{ 1157, 34, 1, 0, 4406, 2 },	---
1588	{ 1201, 34, 1, 0, 4407, 2 },	---	1588	{ 1201, 34, 1, 0, 4407, 2 },	---
1589	{ 1239, 34, 1, 0, 4408, 2 },	---	1589	{ 1239, 34, 1, 0, 4408, 2 },	---
1590	{ 1271, 34, 1, 0, 4409, 2 },	---	1590	{ 1271, 34, 1, 0, 4409, 2 },	---
1591	{ 1303, 34, 1, 0, 4410, 2 },	---	1591	{ 1303, 34, 1, 0, 4410, 2 },	---
1592	{ 1335, 34, 1, 0, 4411, 2 },	---	1592	{ 1335, 34, 1, 0, 4411, 2 },	---
1593	{ 1367, 34, 1, 0, 4412, 2 },	---	1593	{ 1367, 34, 1, 0, 4412, 2 },	---
1594	{ 1393, 34, 1, 0, 4413, 2 },	---	1594	{ 1393, 34, 1, 0, 4413, 2 },	---
1595	{ 1419, 34, 1, 0, 4414, 2 },	---	1595	{ 1419, 34, 1, 0, 4414, 2 },	---
1596	{ 1106, 34, 1, 0, 4415, 2 },	---	1596	{ 1106, 34, 1, 0, 4415, 2 },	---
1597	{ 1163, 34, 1, 0, 4416, 2 },	---	1597	{ 1163, 34, 1, 0, 4416, 2 },	---
1598	};	---	1598	};	---
1599		---	1599		---
1600	extern const MCPhysReg MipsRegUnitRoots[][2] = {	---	1600	extern const MCPhysReg MipsRegUnitRoots[][2] = {	---
1601	{ Mips::AT },	---	1601	{ Mips::AT },	---
1602	{ Mips::DSPCCond },	---	1602	{ Mips::DSPCCond },	---
1603	{ Mips::DSPCarry },	---	1603	{ Mips::DSPCarry },	---
1604	{ Mips::DSPEFI },	---	1604	{ Mips::DSPEFI },	---
1605	{ Mips::DSPOutFlag16_19 },	---	1605	{ Mips::DSPOutFlag16_19 },	---
1606	{ Mips::DSPOutFlag20 },	---	1606	{ Mips::DSPOutFlag20 },	---
1607	{ Mips::DSPOutFlag21 },	---	1607	{ Mips::DSPOutFlag21 },	---
1608	{ Mips::DSPOutFlag22 },	---	1608	{ Mips::DSPOutFlag22 },	---
1609	{ Mips::DSPOutFlag23 },	---	1609	{ Mips::DSPOutFlag23 },	---
1610	{ Mips::DSPPos },	---	1610	{ Mips::DSPPos },	---
1611	{ Mips::DSPSCount },	---	1611	{ Mips::DSPSCount },	---
1612	{ Mips::FP },	---	1612	{ Mips::FP },	---
1613	{ Mips::GP },	---	1613	{ Mips::GP },	---
1614	{ Mips::MSAAccess },	---	1614	{ Mips::MSAAccess },	---
1615	{ Mips::MSACSR },	---	1615	{ Mips::MSACSR },	---
1616	{ Mips::MSAIR },	---	1616	{ Mips::MSAIR },	---
1617	{ Mips::MSAMap },	---	1617	{ Mips::MSAMap },	---
1618	{ Mips::MSAModify },	---	1618	{ Mips::MSAModify },	---
1619	{ Mips::MSARequest },	---	1619	{ Mips::MSARequest },	---
1620	{ Mips::MSASave },	---	1620	{ Mips::MSASave },	---
1621	{ Mips::MSAUnmap },	---	1621	{ Mips::MSAUnmap },	---
1622	{ Mips::PC },	---	1622	{ Mips::PC },	---
1623	{ Mips::RA },	---	1623	{ Mips::RA },	---
1624	{ Mips::SP },	---	1624	{ Mips::SP },	---
1625	{ Mips::ZERO },	---	1625	{ Mips::ZERO },	---
1626	{ Mips::A0 },	---	1626	{ Mips::A0 },	---
1627	{ Mips::A1 },	---	1627	{ Mips::A1 },	---
1628	{ Mips::A2 },	---	1628	{ Mips::A2 },	---
1629	{ Mips::A3 },	---	1629	{ Mips::A3 },	---
1630	{ Mips::LO0 },	---	1630	{ Mips::LO0 },	---
1631	{ Mips::HI0 },	---	1631	{ Mips::HI0 },	---
1632	{ Mips::LO1 },	---	1632	{ Mips::LO1 },	---
1633	{ Mips::HI1 },	---	1633	{ Mips::HI1 },	---
1634	{ Mips::LO2 },	---	1634	{ Mips::LO2 },	---
1635	{ Mips::HI2 },	---	1635	{ Mips::HI2 },	---
1636	{ Mips::LO3 },	---	1636	{ Mips::LO3 },	---
1637	{ Mips::HI3 },	---	1637	{ Mips::HI3 },	---
1638	{ Mips::COP00 },	---	1638	{ Mips::COP00 },	---
1639	{ Mips::COP01 },	---	1639	{ Mips::COP01 },	---
1640	{ Mips::COP02 },	---	1640	{ Mips::COP02 },	---
1641	{ Mips::COP03 },	---	1641	{ Mips::COP03 },	---
1642	{ Mips::COP04 },	---	1642	{ Mips::COP04 },	---
1643	{ Mips::COP05 },	---	1643	{ Mips::COP05 },	---
1644	{ Mips::COP06 },	---	1644	{ Mips::COP06 },	---
1645	{ Mips::COP07 },	---	1645	{ Mips::COP07 },	---
1646	{ Mips::COP08 },	---	1646	{ Mips::COP08 },	---
1647	{ Mips::COP09 },	---	1647	{ Mips::COP09 },	---
1648	{ Mips::COP20 },	---	1648	{ Mips::COP20 },	---
1649	{ Mips::COP21 },	---	1649	{ Mips::COP21 },	---
1650	{ Mips::COP22 },	---	1650	{ Mips::COP22 },	---
1651	{ Mips::COP23 },	---	1651	{ Mips::COP23 },	---
1652	{ Mips::COP24 },	---	1652	{ Mips::COP24 },	---
1653	{ Mips::COP25 },	---	1653	{ Mips::COP25 },	---
1654	{ Mips::COP26 },	---	1654	{ Mips::COP26 },	---
1655	{ Mips::COP27 },	---	1655	{ Mips::COP27 },	---
1656	{ Mips::COP28 },	---	1656	{ Mips::COP28 },	---
1657	{ Mips::COP29 },	---	1657	{ Mips::COP29 },	---
1658	{ Mips::COP30 },	---	1658	{ Mips::COP30 },	---
1659	{ Mips::COP31 },	---	1659	{ Mips::COP31 },	---
1660	{ Mips::COP32 },	---	1660	{ Mips::COP32 },	---
1661	{ Mips::COP33 },	---	1661	{ Mips::COP33 },	---
1662	{ Mips::COP34 },	---	1662	{ Mips::COP34 },	---
1663	{ Mips::COP35 },	---	1663	{ Mips::COP35 },	---
1664	{ Mips::COP36 },	---	1664	{ Mips::COP36 },	---
1665	{ Mips::COP37 },	---	1665	{ Mips::COP37 },	---
1666	{ Mips::COP38 },	---	1666	{ Mips::COP38 },	---
1667	{ Mips::COP39 },	---	1667	{ Mips::COP39 },	---
1668	{ Mips::COP010 },	---	1668	{ Mips::COP010 },	---
1669	{ Mips::COP011 },	---	1669	{ Mips::COP011 },	---
1670	{ Mips::COP012 },	---	1670	{ Mips::COP012 },	---
1671	{ Mips::COP013 },	---	1671	{ Mips::COP013 },	---
1672	{ Mips::COP014 },	---	1672	{ Mips::COP014 },	---
1673	{ Mips::COP015 },	---	1673	{ Mips::COP015 },	---
1674	{ Mips::COP016 },	---	1674	{ Mips::COP016 },	---
1675	{ Mips::COP017 },	---	1675	{ Mips::COP017 },	---
1676	{ Mips::COP018 },	---	1676	{ Mips::COP018 },	---
1677	{ Mips::COP019 },	---	1677	{ Mips::COP019 },	---
1678	{ Mips::COP020 },	---	1678	{ Mips::COP020 },	---
1679	{ Mips::COP021 },	---	1679	{ Mips::COP021 },	---
1680	{ Mips::COP022 },	---	1680	{ Mips::COP022 },	---
1681	{ Mips::COP023 },	---	1681	{ Mips::COP023 },	---
1682	{ Mips::COP024 },	---	1682	{ Mips::COP024 },	---
1683	{ Mips::COP025 },	---	1683	{ Mips::COP025 },	---
1684	{ Mips::COP026 },	---	1684	{ Mips::COP026 },	---
1685	{ Mips::COP027 },	---	1685	{ Mips::COP027 },	---
1686	{ Mips::COP028 },	---	1686	{ Mips::COP028 },	---
1687	{ Mips::COP029 },	---	1687	{ Mips::COP029 },	---
1688	{ Mips::COP030 },	---	1688	{ Mips::COP030 },	---
1689	{ Mips::COP031 },	---	1689	{ Mips::COP031 },	---
1690	{ Mips::COP210 },	---	1690	{ Mips::COP210 },	---
1691	{ Mips::COP211 },	---	1691	{ Mips::COP211 },	---
1692	{ Mips::COP212 },	---	1692	{ Mips::COP212 },	---
1693	{ Mips::COP213 },	---	1693	{ Mips::COP213 },	---
1694	{ Mips::COP214 },	---	1694	{ Mips::COP214 },	---
1695	{ Mips::COP215 },	---	1695	{ Mips::COP215 },	---
1696	{ Mips::COP216 },	---	1696	{ Mips::COP216 },	---
1697	{ Mips::COP217 },	---	1697	{ Mips::COP217 },	---
1698	{ Mips::COP218 },	---	1698	{ Mips::COP218 },	---
1699	{ Mips::COP219 },	---	1699	{ Mips::COP219 },	---
1700	{ Mips::COP220 },	---	1700	{ Mips::COP220 },	---
1701	{ Mips::COP221 },	---	1701	{ Mips::COP221 },	---
1702	{ Mips::COP222 },	---	1702	{ Mips::COP222 },	---
1703	{ Mips::COP223 },	---	1703	{ Mips::COP223 },	---
1704	{ Mips::COP224 },	---	1704	{ Mips::COP224 },	---
1705	{ Mips::COP225 },	---	1705	{ Mips::COP225 },	---
1706	{ Mips::COP226 },	---	1706	{ Mips::COP226 },	---
1707	{ Mips::COP227 },	---	1707	{ Mips::COP227 },	---
1708	{ Mips::COP228 },	---	1708	{ Mips::COP228 },	---
1709	{ Mips::COP229 },	---	1709	{ Mips::COP229 },	---
1710	{ Mips::COP230 },	---	1710	{ Mips::COP230 },	---
1711	{ Mips::COP231 },	---	1711	{ Mips::COP231 },	---
1712	{ Mips::COP310 },	---	1712	{ Mips::COP310 },	---
1713	{ Mips::COP311 },	---	1713	{ Mips::COP311 },	---
1714	{ Mips::COP312 },	---	1714	{ Mips::COP312 },	---
1715	{ Mips::COP313 },	---	1715	{ Mips::COP313 },	---
1716	{ Mips::COP314 },	---	1716	{ Mips::COP314 },	---
1717	{ Mips::COP315 },	---	1717	{ Mips::COP315 },	---
1718	{ Mips::COP316 },	---	1718	{ Mips::COP316 },	---
1719	{ Mips::COP317 },	---	1719	{ Mips::COP317 },	---
1720	{ Mips::COP318 },	---	1720	{ Mips::COP318 },	---
1721	{ Mips::COP319 },	---	1721	{ Mips::COP319 },	---
1722	{ Mips::COP320 },	---	1722	{ Mips::COP320 },	---
1723	{ Mips::COP321 },	---	1723	{ Mips::COP321 },	---
1724	{ Mips::COP322 },	---	1724	{ Mips::COP322 },	---
1725	{ Mips::COP323 },	---	1725	{ Mips::COP323 },	---
1726	{ Mips::COP324 },	---	1726	{ Mips::COP324 },	---
1727	{ Mips::COP325 },	---	1727	{ Mips::COP325 },	---
1728	{ Mips::COP326 },	---	1728	{ Mips::COP326 },	---
1729	{ Mips::COP327 },	---	1729	{ Mips::COP327 },	---
1730	{ Mips::COP328 },	---	1730	{ Mips::COP328 },	---
1731	{ Mips::COP329 },	---	1731	{ Mips::COP329 },	---
1732	{ Mips::COP330 },	---	1732	{ Mips::COP330 },	---
1733	{ Mips::COP331 },	---	1733	{ Mips::COP331 },	---
1734	{ Mips::F0 },	---	1734	{ Mips::F0 },	---
1735	{ Mips::F1 },	---	1735	{ Mips::F1 },	---
1736	{ Mips::F2 },	---	1736	{ Mips::F2 },	---
1737	{ Mips::F3 },	---	1737	{ Mips::F3 },	---
1738	{ Mips::F4 },	---	1738	{ Mips::F4 },	---
1739	{ Mips::F5 },	---	1739	{ Mips::F5 },	---
1740	{ Mips::F6 },	---	1740	{ Mips::F6 },	---
1741	{ Mips::F7 },	---	1741	{ Mips::F7 },	---
1742	{ Mips::F8 },	---	1742	{ Mips::F8 },	---
1743	{ Mips::F9 },	---	1743	{ Mips::F9 },	---
1744	{ Mips::F10 },	---	1744	{ Mips::F10 },	---
1745	{ Mips::F11 },	---	1745	{ Mips::F11 },	---
1746	{ Mips::F12 },	---	1746	{ Mips::F12 },	---
1747	{ Mips::F13 },	---	1747	{ Mips::F13 },	---
1748	{ Mips::F14 },	---	1748	{ Mips::F14 },	---
1749	{ Mips::F15 },	---	1749	{ Mips::F15 },	---
1750	{ Mips::F16 },	---	1750	{ Mips::F16 },	---
1751	{ Mips::F17 },	---	1751	{ Mips::F17 },	---
1752	{ Mips::F18 },	---	1752	{ Mips::F18 },	---
1753	{ Mips::F19 },	---	1753	{ Mips::F19 },	---
1754	{ Mips::F20 },	---	1754	{ Mips::F20 },	---
1755	{ Mips::F21 },	---	1755	{ Mips::F21 },	---
1756	{ Mips::F22 },	---	1756	{ Mips::F22 },	---
1757	{ Mips::F23 },	---	1757	{ Mips::F23 },	---
1758	{ Mips::F24 },	---	1758	{ Mips::F24 },	---
1759	{ Mips::F25 },	---	1759	{ Mips::F25 },	---
1760	{ Mips::F26 },	---	1760	{ Mips::F26 },	---
1761	{ Mips::F27 },	---	1761	{ Mips::F27 },	---
1762	{ Mips::F28 },	---	1762	{ Mips::F28 },	---
1763	{ Mips::F29 },	---	1763	{ Mips::F29 },	---
1764	{ Mips::F30 },	---	1764	{ Mips::F30 },	---
1765	{ Mips::F31 },	---	1765	{ Mips::F31 },	---
1766	{ Mips::FCC0 },	---	1766	{ Mips::FCC0 },	---
1767	{ Mips::FCC1 },	---	1767	{ Mips::FCC1 },	---
1768	{ Mips::FCC2 },	---	1768	{ Mips::FCC2 },	---
1769	{ Mips::FCC3 },	---	1769	{ Mips::FCC3 },	---
1770	{ Mips::FCC4 },	---	1770	{ Mips::FCC4 },	---
1771	{ Mips::FCC5 },	---	1771	{ Mips::FCC5 },	---
1772	{ Mips::FCC6 },	---	1772	{ Mips::FCC6 },	---
1773	{ Mips::FCC7 },	---	1773	{ Mips::FCC7 },	---
1774	{ Mips::FCR0 },	---	1774	{ Mips::FCR0 },	---
1775	{ Mips::FCR1 },	---	1775	{ Mips::FCR1 },	---
1776	{ Mips::FCR2 },	---	1776	{ Mips::FCR2 },	---
1777	{ Mips::FCR3 },	---	1777	{ Mips::FCR3 },	---
1778	{ Mips::FCR4 },	---	1778	{ Mips::FCR4 },	---
1779	{ Mips::FCR5 },	---	1779	{ Mips::FCR5 },	---
1780	{ Mips::FCR6 },	---	1780	{ Mips::FCR6 },	---
1781	{ Mips::FCR7 },	---	1781	{ Mips::FCR7 },	---
1782	{ Mips::FCR8 },	---	1782	{ Mips::FCR8 },	---
1783	{ Mips::FCR9 },	---	1783	{ Mips::FCR9 },	---
1784	{ Mips::FCR10 },	---	1784	{ Mips::FCR10 },	---
1785	{ Mips::FCR11 },	---	1785	{ Mips::FCR11 },	---
1786	{ Mips::FCR12 },	---	1786	{ Mips::FCR12 },	---
1787	{ Mips::FCR13 },	---	1787	{ Mips::FCR13 },	---
1788	{ Mips::FCR14 },	---	1788	{ Mips::FCR14 },	---
1789	{ Mips::FCR15 },	---	1789	{ Mips::FCR15 },	---
1790	{ Mips::FCR16 },	---	1790	{ Mips::FCR16 },	---
1791	{ Mips::FCR17 },	---	1791	{ Mips::FCR17 },	---
1792	{ Mips::FCR18 },	---	1792	{ Mips::FCR18 },	---
1793	{ Mips::FCR19 },	---	1793	{ Mips::FCR19 },	---
1794	{ Mips::FCR20 },	---	1794	{ Mips::FCR20 },	---
1795	{ Mips::FCR21 },	---	1795	{ Mips::FCR21 },	---
1796	{ Mips::FCR22 },	---	1796	{ Mips::FCR22 },	---
1797	{ Mips::FCR23 },	---	1797	{ Mips::FCR23 },	---
1798	{ Mips::FCR24 },	---	1798	{ Mips::FCR24 },	---
1799	{ Mips::FCR25 },	---	1799	{ Mips::FCR25 },	---
1800	{ Mips::FCR26 },	---	1800	{ Mips::FCR26 },	---
1801	{ Mips::FCR27 },	---	1801	{ Mips::FCR27 },	---
1802	{ Mips::FCR28 },	---	1802	{ Mips::FCR28 },	---
1803	{ Mips::FCR29 },	---	1803	{ Mips::FCR29 },	---
1804	{ Mips::FCR30 },	---	1804	{ Mips::FCR30 },	---
1805	{ Mips::FCR31 },	---	1805	{ Mips::FCR31 },	---
1806	{ Mips::F_HI0 },	---	1806	{ Mips::F_HI0 },	---
1807	{ Mips::F_HI1 },	---	1807	{ Mips::F_HI1 },	---
1808	{ Mips::F_HI2 },	---	1808	{ Mips::F_HI2 },	---
1809	{ Mips::F_HI3 },	---	1809	{ Mips::F_HI3 },	---
1810	{ Mips::F_HI4 },	---	1810	{ Mips::F_HI4 },	---
1811	{ Mips::F_HI5 },	---	1811	{ Mips::F_HI5 },	---
1812	{ Mips::F_HI6 },	---	1812	{ Mips::F_HI6 },	---
1813	{ Mips::F_HI7 },	---	1813	{ Mips::F_HI7 },	---
1814	{ Mips::F_HI8 },	---	1814	{ Mips::F_HI8 },	---
1815	{ Mips::F_HI9 },	---	1815	{ Mips::F_HI9 },	---
1816	{ Mips::F_HI10 },	---	1816	{ Mips::F_HI10 },	---
1817	{ Mips::F_HI11 },	---	1817	{ Mips::F_HI11 },	---
1818	{ Mips::F_HI12 },	---	1818	{ Mips::F_HI12 },	---
1819	{ Mips::F_HI13 },	---	1819	{ Mips::F_HI13 },	---
1820	{ Mips::F_HI14 },	---	1820	{ Mips::F_HI14 },	---
1821	{ Mips::F_HI15 },	---	1821	{ Mips::F_HI15 },	---
1822	{ Mips::F_HI16 },	---	1822	{ Mips::F_HI16 },	---
1823	{ Mips::F_HI17 },	---	1823	{ Mips::F_HI17 },	---
1824	{ Mips::F_HI18 },	---	1824	{ Mips::F_HI18 },	---
1825	{ Mips::F_HI19 },	---	1825	{ Mips::F_HI19 },	---
1826	{ Mips::F_HI20 },	---	1826	{ Mips::F_HI20 },	---
1827	{ Mips::F_HI21 },	---	1827	{ Mips::F_HI21 },	---
1828	{ Mips::F_HI22 },	---	1828	{ Mips::F_HI22 },	---
1829	{ Mips::F_HI23 },	---	1829	{ Mips::F_HI23 },	---
1830	{ Mips::F_HI24 },	---	1830	{ Mips::F_HI24 },	---
1831	{ Mips::F_HI25 },	---	1831	{ Mips::F_HI25 },	---
1832	{ Mips::F_HI26 },	---	1832	{ Mips::F_HI26 },	---
1833	{ Mips::F_HI27 },	---	1833	{ Mips::F_HI27 },	---
1834	{ Mips::F_HI28 },	---	1834	{ Mips::F_HI28 },	---
1835	{ Mips::F_HI29 },	---	1835	{ Mips::F_HI29 },	---
1836	{ Mips::F_HI30 },	---	1836	{ Mips::F_HI30 },	---
1837	{ Mips::F_HI31 },	---	1837	{ Mips::F_HI31 },	---
1838	{ Mips::HWR0 },	---	1838	{ Mips::HWR0 },	---
1839	{ Mips::HWR1 },	---	1839	{ Mips::HWR1 },	---
1840	{ Mips::HWR2 },	---	1840	{ Mips::HWR2 },	---
1841	{ Mips::HWR3 },	---	1841	{ Mips::HWR3 },	---
1842	{ Mips::HWR4 },	---	1842	{ Mips::HWR4 },	---
1843	{ Mips::HWR5 },	---	1843	{ Mips::HWR5 },	---
1844	{ Mips::HWR6 },	---	1844	{ Mips::HWR6 },	---
1845	{ Mips::HWR7 },	---	1845	{ Mips::HWR7 },	---
1846	{ Mips::HWR8 },	---	1846	{ Mips::HWR8 },	---
1847	{ Mips::HWR9 },	---	1847	{ Mips::HWR9 },	---
1848	{ Mips::HWR10 },	---	1848	{ Mips::HWR10 },	---
1849	{ Mips::HWR11 },	---	1849	{ Mips::HWR11 },	---
1850	{ Mips::HWR12 },	---	1850	{ Mips::HWR12 },	---
1851	{ Mips::HWR13 },	---	1851	{ Mips::HWR13 },	---
1852	{ Mips::HWR14 },	---	1852	{ Mips::HWR14 },	---
1853	{ Mips::HWR15 },	---	1853	{ Mips::HWR15 },	---
1854	{ Mips::HWR16 },	---	1854	{ Mips::HWR16 },	---
1855	{ Mips::HWR17 },	---	1855	{ Mips::HWR17 },	---
1856	{ Mips::HWR18 },	---	1856	{ Mips::HWR18 },	---
1857	{ Mips::HWR19 },	---	1857	{ Mips::HWR19 },	---
1858	{ Mips::HWR20 },	---	1858	{ Mips::HWR20 },	---
1859	{ Mips::HWR21 },	---	1859	{ Mips::HWR21 },	---
1860	{ Mips::HWR22 },	---	1860	{ Mips::HWR22 },	---
1861	{ Mips::HWR23 },	---	1861	{ Mips::HWR23 },	---
1862	{ Mips::HWR24 },	---	1862	{ Mips::HWR24 },	---
1863	{ Mips::HWR25 },	---	1863	{ Mips::HWR25 },	---
1864	{ Mips::HWR26 },	---	1864	{ Mips::HWR26 },	---
1865	{ Mips::HWR27 },	---	1865	{ Mips::HWR27 },	---
1866	{ Mips::HWR28 },	---	1866	{ Mips::HWR28 },	---
1867	{ Mips::HWR29 },	---	1867	{ Mips::HWR29 },	---
1868	{ Mips::HWR30 },	---	1868	{ Mips::HWR30 },	---
1869	{ Mips::HWR31 },	---	1869	{ Mips::HWR31 },	---
1870	{ Mips::K0 },	---	1870	{ Mips::K0 },	---
1871	{ Mips::K1 },	---	1871	{ Mips::K1 },	---
1872	{ Mips::MPL0 },	---	1872	{ Mips::MPL0 },	---
1873	{ Mips::MPL1 },	---	1873	{ Mips::MPL1 },	---
1874	{ Mips::MPL2 },	---	1874	{ Mips::MPL2 },	---
1875	{ Mips::MSA8 },	---	1875	{ Mips::MSA8 },	---
1876	{ Mips::MSA9 },	---	1876	{ Mips::MSA9 },	---
1877	{ Mips::MSA10 },	---	1877	{ Mips::MSA10 },	---
1878	{ Mips::MSA11 },	---	1878	{ Mips::MSA11 },	---
1879	{ Mips::MSA12 },	---	1879	{ Mips::MSA12 },	---
1880	{ Mips::MSA13 },	---	1880	{ Mips::MSA13 },	---
1881	{ Mips::MSA14 },	---	1881	{ Mips::MSA14 },	---
1882	{ Mips::MSA15 },	---	1882	{ Mips::MSA15 },	---
1883	{ Mips::MSA16 },	---	1883	{ Mips::MSA16 },	---
1884	{ Mips::MSA17 },	---	1884	{ Mips::MSA17 },	---
1885	{ Mips::MSA18 },	---	1885	{ Mips::MSA18 },	---
1886	{ Mips::MSA19 },	---	1886	{ Mips::MSA19 },	---
1887	{ Mips::MSA20 },	---	1887	{ Mips::MSA20 },	---
1888	{ Mips::MSA21 },	---	1888	{ Mips::MSA21 },	---
1889	{ Mips::MSA22 },	---	1889	{ Mips::MSA22 },	---
1890	{ Mips::MSA23 },	---	1890	{ Mips::MSA23 },	---
1891	{ Mips::MSA24 },	---	1891	{ Mips::MSA24 },	---
1892	{ Mips::MSA25 },	---	1892	{ Mips::MSA25 },	---
1893	{ Mips::MSA26 },	---	1893	{ Mips::MSA26 },	---
1894	{ Mips::MSA27 },	---	1894	{ Mips::MSA27 },	---
1895	{ Mips::MSA28 },	---	1895	{ Mips::MSA28 },	---
1896	{ Mips::MSA29 },	---	1896	{ Mips::MSA29 },	---
1897	{ Mips::MSA30 },	---	1897	{ Mips::MSA30 },	---
1898	{ Mips::MSA31 },	---	1898	{ Mips::MSA31 },	---
1899	{ Mips::P0 },	---	1899	{ Mips::P0 },	---
1900	{ Mips::P1 },	---	1900	{ Mips::P1 },	---
1901	{ Mips::P2 },	---	1901	{ Mips::P2 },	---
1902	{ Mips::S0 },	---	1902	{ Mips::S0 },	---
1903	{ Mips::S1 },	---	1903	{ Mips::S1 },	---
1904	{ Mips::S2 },	---	1904	{ Mips::S2 },	---
1905	{ Mips::S3 },	---	1905	{ Mips::S3 },	---
1906	{ Mips::S4 },	---	1906	{ Mips::S4 },	---
1907	{ Mips::S5 },	---	1907	{ Mips::S5 },	---
1908	{ Mips::S6 },	---	1908	{ Mips::S6 },	---
1909	{ Mips::S7 },	---	1909	{ Mips::S7 },	---
1910	{ Mips::T0 },	---	1910	{ Mips::T0 },	---
1911	{ Mips::T1 },	---	1911	{ Mips::T1 },	---
1912	{ Mips::T2 },	---	1912	{ Mips::T2 },	---
1913	{ Mips::T3 },	---	1913	{ Mips::T3 },	---
1914	{ Mips::T4 },	---	1914	{ Mips::T4 },	---
1915	{ Mips::T5 },	---	1915	{ Mips::T5 },	---
1916	{ Mips::T6 },	---	1916	{ Mips::T6 },	---
1917	{ Mips::T7 },	---	1917	{ Mips::T7 },	---
1918	{ Mips::T8 },	---	1918	{ Mips::T8 },	---
1919	{ Mips::T9 },	---	1919	{ Mips::T9 },	---
1920	{ Mips::V0 },	---	1920	{ Mips::V0 },	---
1921	{ Mips::V1 },	---	1921	{ Mips::V1 },	---
1922	};	---	1922	};	---
1923		---	1923		---
1924	namespace { // Register classes...	---	1924	namespace { // Register classes...	---
1925	// MSA128F16 Register Class...	---	1925	// MSA128F16 Register Class...	---
1926	const MCPhysReg MSA128F16[] = {	---	1926	const MCPhysReg MSA128F16[] = {	---
1927	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---	1927	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---
1928	};	---	1928	};	---
1929		---	1929		---
1930	// MSA128F16 Bit set.	---	1930	// MSA128F16 Bit set.	---
1931	const uint8_t MSA128F16Bits[] = {	---	1931	const uint8_t MSA128F16Bits[] = {	---
1932	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	1932	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
1933	};	---	1933	};	---
1934		---	1934		---
1935	// CCR Register Class...	---	1935	// CCR Register Class...	---
1936	const MCPhysReg CCR[] = {	---	1936	const MCPhysReg CCR[] = {	---
1937	Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,	---	1937	Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,	---
1938	};	---	1938	};	---
1939		---	1939		---
1940	// CCR Bit set.	---	1940	// CCR Bit set.	---
1941	const uint8_t CCRBits[] = {	---	1941	const uint8_t CCRBits[] = {	---
1942	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	1942	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
1943	};	---	1943	};	---
1944		---	1944		---
1945	// COP0 Register Class...	---	1945	// COP0 Register Class...	---
1946	const MCPhysReg COP0[] = {	---	1946	const MCPhysReg COP0[] = {	---
1947	Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,	---	1947	Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,	---
1948	};	---	1948	};	---
1949		---	1949		---
1950	// COP0 Bit set.	---	1950	// COP0 Bit set.	---
1951	const uint8_t COP0Bits[] = {	---	1951	const uint8_t COP0Bits[] = {	---
1952	0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,	---	1952	0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,	---
1953	};	---	1953	};	---
1954		---	1954		---
1955	// COP2 Register Class...	---	1955	// COP2 Register Class...	---
1956	const MCPhysReg COP2[] = {	---	1956	const MCPhysReg COP2[] = {	---
1957	Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,	---	1957	Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,	---
1958	};	---	1958	};	---
1959		---	1959		---
1960	// COP2 Bit set.	---	1960	// COP2 Bit set.	---
1961	const uint8_t COP2Bits[] = {	---	1961	const uint8_t COP2Bits[] = {	---
1962	0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,	---	1962	0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,	---
1963	};	---	1963	};	---
1964		---	1964		---
1965	// COP3 Register Class...	---	1965	// COP3 Register Class...	---
1966	const MCPhysReg COP3[] = {	---	1966	const MCPhysReg COP3[] = {	---
1967	Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,	---	1967	Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,	---
1968	};	---	1968	};	---
1969		---	1969		---
1970	// COP3 Bit set.	---	1970	// COP3 Bit set.	---
1971	const uint8_t COP3Bits[] = {	---	1971	const uint8_t COP3Bits[] = {	---
1972	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,	---	1972	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,	---
1973	};	---	1973	};	---
1974		---	1974		---
1975	// DSPR Register Class...	---	1975	// DSPR Register Class...	---
1976	const MCPhysReg DSPR[] = {	---	1976	const MCPhysReg DSPR[] = {	---
1977	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---	1977	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---
1978	};	---	1978	};	---
1979		---	1979		---
1980	// DSPR Bit set.	---	1980	// DSPR Bit set.	---
1981	const uint8_t DSPRBits[] = {	---	1981	const uint8_t DSPRBits[] = {	---
1982	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---	1982	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---
1983	};	---	1983	};	---
1984		---	1984		---
1985	// FGR32 Register Class...	---	1985	// FGR32 Register Class...	---
1986	const MCPhysReg FGR32[] = {	---	1986	const MCPhysReg FGR32[] = {	---
1987	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	---	1987	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	---
1988	};	---	1988	};	---
1989		---	1989		---
1990	// FGR32 Bit set.	---	1990	// FGR32 Bit set.	---
1991	const uint8_t FGR32Bits[] = {	---	1991	const uint8_t FGR32Bits[] = {	---
1992	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	1992	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
1993	};	---	1993	};	---
1994		---	1994		---
1995	// FGRCC Register Class...	---	1995	// FGRCC Register Class...	---
1996	const MCPhysReg FGRCC[] = {	---	1996	const MCPhysReg FGRCC[] = {	---
1997	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	---	1997	Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,	---
1998	};	---	1998	};	---
1999		---	1999		---
2000	// FGRCC Bit set.	---	2000	// FGRCC Bit set.	---
2001	const uint8_t FGRCCBits[] = {	---	2001	const uint8_t FGRCCBits[] = {	---
2002	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	2002	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
2003	};	---	2003	};	---
2004		---	2004		---
2005	// GPR32 Register Class...	---	2005	// GPR32 Register Class...	---
2006	const MCPhysReg GPR32[] = {	---	2006	const MCPhysReg GPR32[] = {	---
2007	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---	2007	Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---
2008	};	---	2008	};	---
2009		---	2009		---
2010	// GPR32 Bit set.	---	2010	// GPR32 Bit set.	---
2011	const uint8_t GPR32Bits[] = {	---	2011	const uint8_t GPR32Bits[] = {	---
2012	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---	2012	0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---
2013	};	---	2013	};	---
2014		---	2014		---
2015	// HWRegs Register Class...	---	2015	// HWRegs Register Class...	---
2016	const MCPhysReg HWRegs[] = {	---	2016	const MCPhysReg HWRegs[] = {	---
2017	Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,	---	2017	Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,	---
2018	};	---	2018	};	---
2019		---	2019		---
2020	// HWRegs Bit set.	---	2020	// HWRegs Bit set.	---
2021	const uint8_t HWRegsBits[] = {	---	2021	const uint8_t HWRegsBits[] = {	---
2022	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	---	2022	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	---
2023	};	---	2023	};	---
2024		---	2024		---
2025	// MSACtrl Register Class...	---	2025	// MSACtrl Register Class...	---
2026	const MCPhysReg MSACtrl[] = {	---	2026	const MCPhysReg MSACtrl[] = {	---
2027	Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,	---	2027	Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31,	---
2028	};	---	2028	};	---
2029		---	2029		---
2030	// MSACtrl Bit set.	---	2030	// MSACtrl Bit set.	---
2031	const uint8_t MSACtrlBits[] = {	---	2031	const uint8_t MSACtrlBits[] = {	---
2032	0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,	---	2032	0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03,	---
2033	};	---	2033	};	---
2034		---	2034		---
2035	// GPR32NONZERO Register Class...	---	2035	// GPR32NONZERO Register Class...	---
2036	const MCPhysReg GPR32NONZERO[] = {	---	2036	const MCPhysReg GPR32NONZERO[] = {	---
2037	Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---	2037	Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,	---
2038	};	---	2038	};	---
2039		---	2039		---
2040	// GPR32NONZERO Bit set.	---	2040	// GPR32NONZERO Bit set.	---
2041	const uint8_t GPR32NONZEROBits[] = {	---	2041	const uint8_t GPR32NONZEROBits[] = {	---
2042	0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---	2042	0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07,	---
2043	};	---	2043	};	---
2044		---	2044		---
2045	// CPU16RegsPlusSP Register Class...	---	2045	// CPU16RegsPlusSP Register Class...	---
2046	const MCPhysReg CPU16RegsPlusSP[] = {	---	2046	const MCPhysReg CPU16RegsPlusSP[] = {	---
2047	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,	---	2047	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,	---
2048	};	---	2048	};	---
2049		---	2049		---
2050	// CPU16RegsPlusSP Bit set.	---	2050	// CPU16RegsPlusSP Bit set.	---
2051	const uint8_t CPU16RegsPlusSPBits[] = {	---	2051	const uint8_t CPU16RegsPlusSPBits[] = {	---
2052	0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---	2052	0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---
2053	};	---	2053	};	---
2054		---	2054		---
2055	// CPU16Regs Register Class...	---	2055	// CPU16Regs Register Class...	---
2056	const MCPhysReg CPU16Regs[] = {	---	2056	const MCPhysReg CPU16Regs[] = {	---
2057	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,	---	2057	Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,	---
2058	};	---	2058	};	---
2059		---	2059		---
2060	// CPU16Regs Bit set.	---	2060	// CPU16Regs Bit set.	---
2061	const uint8_t CPU16RegsBits[] = {	---	2061	const uint8_t CPU16RegsBits[] = {	---
2062	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---	2062	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---
2063	};	---	2063	};	---
2064		---	2064		---
2065	// FCC Register Class...	---	2065	// FCC Register Class...	---
2066	const MCPhysReg FCC[] = {	---	2066	const MCPhysReg FCC[] = {	---
2067	Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,	---	2067	Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,	---
2068	};	---	2068	};	---
2069		---	2069		---
2070	// FCC Bit set.	---	2070	// FCC Bit set.	---
2071	const uint8_t FCCBits[] = {	---	2071	const uint8_t FCCBits[] = {	---
2072	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,	---	2072	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,	---
2073	};	---	2073	};	---
2074		---	2074		---
2075	// GPRMM16 Register Class...	---	2075	// GPRMM16 Register Class...	---
2076	const MCPhysReg GPRMM16[] = {	---	2076	const MCPhysReg GPRMM16[] = {	---
2077	Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---	2077	Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---
2078	};	---	2078	};	---
2079		---	2079		---
2080	// GPRMM16 Bit set.	---	2080	// GPRMM16 Bit set.	---
2081	const uint8_t GPRMM16Bits[] = {	---	2081	const uint8_t GPRMM16Bits[] = {	---
2082	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---	2082	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---
2083	};	---	2083	};	---
2084		---	2084		---
2085	// GPRMM16MoveP Register Class...	---	2085	// GPRMM16MoveP Register Class...	---
2086	const MCPhysReg GPRMM16MoveP[] = {	---	2086	const MCPhysReg GPRMM16MoveP[] = {	---
2087	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	---	2087	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	---
2088	};	---	2088	};	---
2089		---	2089		---
2090	// GPRMM16MoveP Bit set.	---	2090	// GPRMM16MoveP Bit set.	---
2091	const uint8_t GPRMM16MovePBits[] = {	---	2091	const uint8_t GPRMM16MovePBits[] = {	---
2092	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	---	2092	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	---
2093	};	---	2093	};	---
2094		---	2094		---
2095	// GPRMM16Zero Register Class...	---	2095	// GPRMM16Zero Register Class...	---
2096	const MCPhysReg GPRMM16Zero[] = {	---	2096	const MCPhysReg GPRMM16Zero[] = {	---
2097	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---	2097	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---
2098	};	---	2098	};	---
2099		---	2099		---
2100	// GPRMM16Zero Bit set.	---	2100	// GPRMM16Zero Bit set.	---
2101	const uint8_t GPRMM16ZeroBits[] = {	---	2101	const uint8_t GPRMM16ZeroBits[] = {	---
2102	0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---	2102	0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---
2103	};	---	2103	};	---
2104		---	2104		---
2105	// CPU16Regs_and_GPRMM16Zero Register Class...	---	2105	// CPU16Regs_and_GPRMM16Zero Register Class...	---
2106	const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {	---	2106	const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {	---
2107	Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---	2107	Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,	---
2108	};	---	2108	};	---
2109		---	2109		---
2110	// CPU16Regs_and_GPRMM16Zero Bit set.	---	2110	// CPU16Regs_and_GPRMM16Zero Bit set.	---
2111	const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {	---	2111	const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {	---
2112	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---	2112	0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---
2113	};	---	2113	};	---
2114		---	2114		---
2115	// GPR32NONZERO_and_GPRMM16MoveP Register Class...	---	2115	// GPR32NONZERO_and_GPRMM16MoveP Register Class...	---
2116	const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {	---	2116	const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {	---
2117	Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	---	2117	Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,	---
2118	};	---	2118	};	---
2119		---	2119		---
2120	// GPR32NONZERO_and_GPRMM16MoveP Bit set.	---	2120	// GPR32NONZERO_and_GPRMM16MoveP Bit set.	---
2121	const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {	---	2121	const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {	---
2122	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	---	2122	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,	---
2123	};	---	2123	};	---
2124		---	2124		---
2125	// GPRMM16MovePPairSecond Register Class...	---	2125	// GPRMM16MovePPairSecond Register Class...	---
2126	const MCPhysReg GPRMM16MovePPairSecond[] = {	---	2126	const MCPhysReg GPRMM16MovePPairSecond[] = {	---
2127	Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,	---	2127	Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6,	---
2128	};	---	2128	};	---
2129		---	2129		---
2130	// GPRMM16MovePPairSecond Bit set.	---	2130	// GPRMM16MovePPairSecond Bit set.	---
2131	const uint8_t GPRMM16MovePPairSecondBits[] = {	---	2131	const uint8_t GPRMM16MovePPairSecondBits[] = {	---
2132	0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	---	2132	0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	---
2133	};	---	2133	};	---
2134		---	2134		---
2135	// CPU16Regs_and_GPRMM16MoveP Register Class...	---	2135	// CPU16Regs_and_GPRMM16MoveP Register Class...	---
2136	const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {	---	2136	const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {	---
2137	Mips::S1, Mips::V0, Mips::V1, Mips::S0,	---	2137	Mips::S1, Mips::V0, Mips::V1, Mips::S0,	---
2138	};	---	2138	};	---
2139		---	2139		---
2140	// CPU16Regs_and_GPRMM16MoveP Bit set.	---	2140	// CPU16Regs_and_GPRMM16MoveP Bit set.	---
2141	const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {	---	2141	const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {	---
2142	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---	2142	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,	---
2143	};	---	2143	};	---
2144		---	2144		---
2145	// GPRMM16MoveP_and_GPRMM16Zero Register Class...	---	2145	// GPRMM16MoveP_and_GPRMM16Zero Register Class...	---
2146	const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {	---	2146	const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {	---
2147	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,	---	2147	Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,	---
2148	};	---	2148	};	---
2149		---	2149		---
2150	// GPRMM16MoveP_and_GPRMM16Zero Bit set.	---	2150	// GPRMM16MoveP_and_GPRMM16Zero Bit set.	---
2151	const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	---	2151	const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	---
2152	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---	2152	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---
2153	};	---	2153	};	---
2154		---	2154		---
2155	// HI32DSP Register Class...	---	2155	// HI32DSP Register Class...	---
2156	const MCPhysReg HI32DSP[] = {	---	2156	const MCPhysReg HI32DSP[] = {	---
2157	Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,	---	2157	Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,	---
2158	};	---	2158	};	---
2159		---	2159		---
2160	// HI32DSP Bit set.	---	2160	// HI32DSP Bit set.	---
2161	const uint8_t HI32DSPBits[] = {	---	2161	const uint8_t HI32DSPBits[] = {	---
2162	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,	---	2162	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,	---
2163	};	---	2163	};	---
2164		---	2164		---
2165	// LO32DSP Register Class...	---	2165	// LO32DSP Register Class...	---
2166	const MCPhysReg LO32DSP[] = {	---	2166	const MCPhysReg LO32DSP[] = {	---
2167	Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,	---	2167	Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,	---
2168	};	---	2168	};	---
2169		---	2169		---
2170	// LO32DSP Bit set.	---	2170	// LO32DSP Bit set.	---
2171	const uint8_t LO32DSPBits[] = {	---	2171	const uint8_t LO32DSPBits[] = {	---
2172	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,	---	2172	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,	---
2173	};	---	2173	};	---
2174		---	2174		---
2175	// CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	---	2175	// CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	---
2176	const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {	---	2176	const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {	---
2177	Mips::A1, Mips::A2, Mips::A3,	---	2177	Mips::A1, Mips::A2, Mips::A3,	---
2178	};	---	2178	};	---
2179		---	2179		---
2180	// CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	---	2180	// CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	---
2181	const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	---	2181	const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	---
2182	0x00, 0x00, 0x80, 0x03,	---	2182	0x00, 0x00, 0x80, 0x03,	---
2183	};	---	2183	};	---
2184		---	2184		---
2185	// GPRMM16MovePPairFirst Register Class...	---	2185	// GPRMM16MovePPairFirst Register Class...	---
2186	const MCPhysReg GPRMM16MovePPairFirst[] = {	---	2186	const MCPhysReg GPRMM16MovePPairFirst[] = {	---
2187	Mips::A0, Mips::A1, Mips::A2,	---	2187	Mips::A0, Mips::A1, Mips::A2,	---
2188	};	---	2188	};	---
2189		---	2189		---
2190	// GPRMM16MovePPairFirst Bit set.	---	2190	// GPRMM16MovePPairFirst Bit set.	---
2191	const uint8_t GPRMM16MovePPairFirstBits[] = {	---	2191	const uint8_t GPRMM16MovePPairFirstBits[] = {	---
2192	0x00, 0x00, 0xc0, 0x01,	---	2192	0x00, 0x00, 0xc0, 0x01,	---
2193	};	---	2193	};	---
2194		---	2194		---
2195	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	---	2195	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	---
2196	const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	---	2196	const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	---
2197	Mips::S1, Mips::V0, Mips::V1,	---	2197	Mips::S1, Mips::V0, Mips::V1,	---
2198	};	---	2198	};	---
2199		---	2199		---
2200	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	---	2200	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	---
2201	const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	---	2201	const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	---
2202	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---	2202	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,	---
2203	};	---	2203	};	---
2204		---	2204		---
2205	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	---	2205	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	---
2206	const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	---	2206	const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	---
2207	Mips::A1, Mips::A2,	---	2207	Mips::A1, Mips::A2,	---
2208	};	---	2208	};	---
2209		---	2209		---
2210	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	---	2210	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	---
2211	const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	---	2211	const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	---
2212	0x00, 0x00, 0x80, 0x01,	---	2212	0x00, 0x00, 0x80, 0x01,	---
2213	};	---	2213	};	---
2214		---	2214		---
2215	// CPURAReg Register Class...	---	2215	// CPURAReg Register Class...	---
2216	const MCPhysReg CPURAReg[] = {	---	2216	const MCPhysReg CPURAReg[] = {	---
2217	Mips::RA,	---	2217	Mips::RA,	---
2218	};	---	2218	};	---
2219		---	2219		---
2220	// CPURAReg Bit set.	---	2220	// CPURAReg Bit set.	---
2221	const uint8_t CPURARegBits[] = {	---	2221	const uint8_t CPURARegBits[] = {	---
2222	0x00, 0x00, 0x08,	---	2222	0x00, 0x00, 0x08,	---
2223	};	---	2223	};	---
2224		---	2224		---
2225	// CPUSPReg Register Class...	---	2225	// CPUSPReg Register Class...	---
2226	const MCPhysReg CPUSPReg[] = {	---	2226	const MCPhysReg CPUSPReg[] = {	---
2227	Mips::SP,	---	2227	Mips::SP,	---
2228	};	---	2228	};	---
2229		---	2229		---
2230	// CPUSPReg Bit set.	---	2230	// CPUSPReg Bit set.	---
2231	const uint8_t CPUSPRegBits[] = {	---	2231	const uint8_t CPUSPRegBits[] = {	---
2232	0x00, 0x00, 0x10,	---	2232	0x00, 0x00, 0x10,	---
2233	};	---	2233	};	---
2234		---	2234		---
2235	// DSPCC Register Class...	---	2235	// DSPCC Register Class...	---
2236	const MCPhysReg DSPCC[] = {	---	2236	const MCPhysReg DSPCC[] = {	---
2237	Mips::DSPCCond,	---	2237	Mips::DSPCCond,	---
2238	};	---	2238	};	---
2239		---	2239		---
2240	// DSPCC Bit set.	---	2240	// DSPCC Bit set.	---
2241	const uint8_t DSPCCBits[] = {	---	2241	const uint8_t DSPCCBits[] = {	---
2242	0x04,	---	2242	0x04,	---
2243	};	---	2243	};	---
2244		---	2244		---
2245	// GP32 Register Class...	---	2245	// GP32 Register Class...	---
2246	const MCPhysReg GP32[] = {	---	2246	const MCPhysReg GP32[] = {	---
2247	Mips::GP,	---	2247	Mips::GP,	---
2248	};	---	2248	};	---
2249		---	2249		---
2250	// GP32 Bit set.	---	2250	// GP32 Bit set.	---
2251	const uint8_t GP32Bits[] = {	---	2251	const uint8_t GP32Bits[] = {	---
2252	0x00, 0x02,	---	2252	0x00, 0x02,	---
2253	};	---	2253	};	---
2254		---	2254		---
2255	// GPR32ZERO Register Class...	---	2255	// GPR32ZERO Register Class...	---
2256	const MCPhysReg GPR32ZERO[] = {	---	2256	const MCPhysReg GPR32ZERO[] = {	---
2257	Mips::ZERO,	---	2257	Mips::ZERO,	---
2258	};	---	2258	};	---
2259		---	2259		---
2260	// GPR32ZERO Bit set.	---	2260	// GPR32ZERO Bit set.	---
2261	const uint8_t GPR32ZEROBits[] = {	---	2261	const uint8_t GPR32ZEROBits[] = {	---
2262	0x00, 0x00, 0x20,	---	2262	0x00, 0x00, 0x20,	---
2263	};	---	2263	};	---
2264		---	2264		---
2265	// HI32 Register Class...	---	2265	// HI32 Register Class...	---
2266	const MCPhysReg HI32[] = {	---	2266	const MCPhysReg HI32[] = {	---
2267	Mips::HI0,	---	2267	Mips::HI0,	---
2268	};	---	2268	};	---
2269		---	2269		---
2270	// HI32 Bit set.	---	2270	// HI32 Bit set.	---
2271	const uint8_t HI32Bits[] = {	---	2271	const uint8_t HI32Bits[] = {	---
2272	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---	2272	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---
2273	};	---	2273	};	---
2274		---	2274		---
2275	// LO32 Register Class...	---	2275	// LO32 Register Class...	---
2276	const MCPhysReg LO32[] = {	---	2276	const MCPhysReg LO32[] = {	---
2277	Mips::LO0,	---	2277	Mips::LO0,	---
2278	};	---	2278	};	---
2279		---	2279		---
2280	// LO32 Bit set.	---	2280	// LO32 Bit set.	---
2281	const uint8_t LO32Bits[] = {	---	2281	const uint8_t LO32Bits[] = {	---
2282	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	---	2282	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	---
2283	};	---	2283	};	---
2284		---	2284		---
2285	// SP32 Register Class...	---	2285	// SP32 Register Class...	---
2286	const MCPhysReg SP32[] = {	---	2286	const MCPhysReg SP32[] = {	---
2287	Mips::SP,	---	2287	Mips::SP,	---
2288	};	---	2288	};	---
2289		---	2289		---
2290	// SP32 Bit set.	---	2290	// SP32 Bit set.	---
2291	const uint8_t SP32Bits[] = {	---	2291	const uint8_t SP32Bits[] = {	---
2292	0x00, 0x00, 0x10,	---	2292	0x00, 0x00, 0x10,	---
2293	};	---	2293	};	---
2294		---	2294		---
2295	// FGR64 Register Class...	---	2295	// FGR64 Register Class...	---
2296	const MCPhysReg FGR64[] = {	---	2296	const MCPhysReg FGR64[] = {	---
2297	Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,	---	2297	Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,	---
2298	};	---	2298	};	---
2299		---	2299		---
2300	// FGR64 Bit set.	---	2300	// FGR64 Bit set.	---
2301	const uint8_t FGR64Bits[] = {	---	2301	const uint8_t FGR64Bits[] = {	---
2302	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	---	2302	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,	---
2303	};	---	2303	};	---
2304		---	2304		---
2305	// GPR64 Register Class...	---	2305	// GPR64 Register Class...	---
2306	const MCPhysReg GPR64[] = {	---	2306	const MCPhysReg GPR64[] = {	---
2307	Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	---	2307	Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	---
2308	};	---	2308	};	---
2309		---	2309		---
2310	// GPR64 Bit set.	---	2310	// GPR64 Bit set.	---
2311	const uint8_t GPR64Bits[] = {	---	2311	const uint8_t GPR64Bits[] = {	---
2312	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	---	2312	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	---
2313	};	---	2313	};	---
2314		---	2314		---
2315	// GPR64_with_sub_32_in_GPR32NONZERO Register Class...	---	2315	// GPR64_with_sub_32_in_GPR32NONZERO Register Class...	---
2316	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {	---	2316	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {	---
2317	Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	---	2317	Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,	---
2318	};	---	2318	};	---
2319		---	2319		---
2320	// GPR64_with_sub_32_in_GPR32NONZERO Bit set.	---	2320	// GPR64_with_sub_32_in_GPR32NONZERO Bit set.	---
2321	const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {	---	2321	const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {	---
2322	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	---	2322	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,	---
2323	};	---	2323	};	---
2324		---	2324		---
2325	// AFGR64 Register Class...	---	2325	// AFGR64 Register Class...	---
2326	const MCPhysReg AFGR64[] = {	---	2326	const MCPhysReg AFGR64[] = {	---
2327	Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,	---	2327	Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,	---
2328	};	---	2328	};	---
2329		---	2329		---
2330	// AFGR64 Bit set.	---	2330	// AFGR64 Bit set.	---
2331	const uint8_t AFGR64Bits[] = {	---	2331	const uint8_t AFGR64Bits[] = {	---
2332	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,	---	2332	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,	---
2333	};	---	2333	};	---
2334		---	2334		---
2335	// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...	---	2335	// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...	---
2336	const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {	---	2336	const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {	---
2337	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,	---	2337	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,	---
2338	};	---	2338	};	---
2339		---	2339		---
2340	// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.	---	2340	// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.	---
2341	const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {	---	2341	const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {	---
2342	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---	2342	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---
2343	};	---	2343	};	---
2344		---	2344		---
2345	// GPR64_with_sub_32_in_CPU16Regs Register Class...	---	2345	// GPR64_with_sub_32_in_CPU16Regs Register Class...	---
2346	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {	---	2346	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {	---
2347	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,	---	2347	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,	---
2348	};	---	2348	};	---
2349		---	2349		---
2350	// GPR64_with_sub_32_in_CPU16Regs Bit set.	---	2350	// GPR64_with_sub_32_in_CPU16Regs Bit set.	---
2351	const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {	---	2351	const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {	---
2352	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---	2352	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---
2353	};	---	2353	};	---
2354		---	2354		---
2355	// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...	---	2355	// GPR64_with_sub_32_in_GPRMM16MoveP Register Class...	---
2356	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {	---	2356	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {	---
2357	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	---	2357	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	---
2358	};	---	2358	};	---
2359		---	2359		---
2360	// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.	---	2360	// GPR64_with_sub_32_in_GPRMM16MoveP Bit set.	---
2361	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {	---	2361	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {	---
2362	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	---	2362	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	---
2363	};	---	2363	};	---
2364		---	2364		---
2365	// GPR64_with_sub_32_in_GPRMM16Zero Register Class...	---	2365	// GPR64_with_sub_32_in_GPRMM16Zero Register Class...	---
2366	const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {	---	2366	const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {	---
2367	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	---	2367	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	---
2368	};	---	2368	};	---
2369		---	2369		---
2370	// GPR64_with_sub_32_in_GPRMM16Zero Bit set.	---	2370	// GPR64_with_sub_32_in_GPRMM16Zero Bit set.	---
2371	const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {	---	2371	const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {	---
2372	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---	2372	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---
2373	};	---	2373	};	---
2374		---	2374		---
2375	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...	---	2375	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...	---
2376	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {	---	2376	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {	---
2377	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	---	2377	Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,	---
2378	};	---	2378	};	---
2379		---	2379		---
2380	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.	---	2380	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.	---
2381	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {	---	2381	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {	---
2382	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---	2382	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---
2383	};	---	2383	};	---
2384		---	2384		---
2385	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...	---	2385	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...	---
2386	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {	---	2386	const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {	---
2387	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	---	2387	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,	---
2388	};	---	2388	};	---
2389		---	2389		---
2390	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.	---	2390	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.	---
2391	const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {	---	2391	const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {	---
2392	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	---	2392	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,	---
2393	};	---	2393	};	---
2394		---	2394		---
2395	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...	---	2395	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...	---
2396	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {	---	2396	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {	---
2397	Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,	---	2397	Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64,	---
2398	};	---	2398	};	---
2399		---	2399		---
2400	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.	---	2400	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.	---
2401	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {	---	2401	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {	---
2402	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	---	2402	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,	---
2403	};	---	2403	};	---
2404		---	2404		---
2405	// ACC64DSP Register Class...	---	2405	// ACC64DSP Register Class...	---
2406	const MCPhysReg ACC64DSP[] = {	---	2406	const MCPhysReg ACC64DSP[] = {	---
2407	Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,	---	2407	Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,	---
2408	};	---	2408	};	---
2409		---	2409		---
2410	// ACC64DSP Bit set.	---	2410	// ACC64DSP Bit set.	---
2411	const uint8_t ACC64DSPBits[] = {	---	2411	const uint8_t ACC64DSPBits[] = {	---
2412	0x00, 0x00, 0x00, 0x3c,	---	2412	0x00, 0x00, 0x00, 0x3c,	---
2413	};	---	2413	};	---
2414		---	2414		---
2415	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...	---	2415	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...	---
2416	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {	---	2416	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {	---
2417	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,	---	2417	Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,	---
2418	};	---	2418	};	---
2419		---	2419		---
2420	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.	---	2420	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.	---
2421	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {	---	2421	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {	---
2422	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---	2422	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,	---
2423	};	---	2423	};	---
2424		---	2424		---
2425	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...	---	2425	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...	---
2426	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {	---	2426	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {	---
2427	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,	---	2427	Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,	---
2428	};	---	2428	};	---
2429		---	2429		---
2430	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.	---	2430	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.	---
2431	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	---	2431	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {	---
2432	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---	2432	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---
2433	};	---	2433	};	---
2434		---	2434		---
2435	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	---	2435	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...	---
2436	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {	---	2436	const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {	---
2437	Mips::A1_64, Mips::A2_64, Mips::A3_64,	---	2437	Mips::A1_64, Mips::A2_64, Mips::A3_64,	---
2438	};	---	2438	};	---
2439		---	2439		---
2440	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	---	2440	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.	---
2441	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	---	2441	const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {	---
2442	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,	---	2442	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,	---
2443	};	---	2443	};	---
2444		---	2444		---
2445	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...	---	2445	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...	---
2446	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {	---	2446	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {	---
2447	Mips::A0_64, Mips::A1_64, Mips::A2_64,	---	2447	Mips::A0_64, Mips::A1_64, Mips::A2_64,	---
2448	};	---	2448	};	---
2449		---	2449		---
2450	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.	---	2450	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.	---
2451	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {	---	2451	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {	---
2452	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,	---	2452	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,	---
2453	};	---	2453	};	---
2454		---	2454		---
2455	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	---	2455	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...	---
2456	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	---	2456	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {	---
2457	Mips::V0_64, Mips::V1_64, Mips::S1_64,	---	2457	Mips::V0_64, Mips::V1_64, Mips::S1_64,	---
2458	};	---	2458	};	---
2459		---	2459		---
2460	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	---	2460	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.	---
2461	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	---	2461	const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {	---
2462	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---	2462	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,	---
2463	};	---	2463	};	---
2464		---	2464		---
2465	// OCTEON_MPL Register Class...	---	2465	// OCTEON_MPL Register Class...	---
2466	const MCPhysReg OCTEON_MPL[] = {	---	2466	const MCPhysReg OCTEON_MPL[] = {	---
2467	Mips::MPL0, Mips::MPL1, Mips::MPL2,	---	2467	Mips::MPL0, Mips::MPL1, Mips::MPL2,	---
2468	};	---	2468	};	---
2469		---	2469		---
2470	// OCTEON_MPL Bit set.	---	2470	// OCTEON_MPL Bit set.	---
2471	const uint8_t OCTEON_MPLBits[] = {	---	2471	const uint8_t OCTEON_MPLBits[] = {	---
2472	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,	---	2472	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,	---
2473	};	---	2473	};	---
2474		---	2474		---
2475	// OCTEON_P Register Class...	---	2475	// OCTEON_P Register Class...	---
2476	const MCPhysReg OCTEON_P[] = {	---	2476	const MCPhysReg OCTEON_P[] = {	---
2477	Mips::P0, Mips::P1, Mips::P2,	---	2477	Mips::P0, Mips::P1, Mips::P2,	---
2478	};	---	2478	};	---
2479		---	2479		---
2480	// OCTEON_P Bit set.	---	2480	// OCTEON_P Bit set.	---
2481	const uint8_t OCTEON_PBits[] = {	---	2481	const uint8_t OCTEON_PBits[] = {	---
2482	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,	---	2482	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,	---
2483	};	---	2483	};	---
2484		---	2484		---
2485	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	---	2485	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...	---
2486	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	---	2486	const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {	---
2487	Mips::A1_64, Mips::A2_64,	---	2487	Mips::A1_64, Mips::A2_64,	---
2488	};	---	2488	};	---
2489		---	2489		---
2490	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	---	2490	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.	---
2491	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	---	2491	const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {	---
2492	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,	---	2492	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,	---
2493	};	---	2493	};	---
2494		---	2494		---
2495	// ACC64 Register Class...	---	2495	// ACC64 Register Class...	---
2496	const MCPhysReg ACC64[] = {	---	2496	const MCPhysReg ACC64[] = {	---
2497	Mips::AC0,	---	2497	Mips::AC0,	---
2498	};	---	2498	};	---
2499		---	2499		---
2500	// ACC64 Bit set.	---	2500	// ACC64 Bit set.	---
2501	const uint8_t ACC64Bits[] = {	---	2501	const uint8_t ACC64Bits[] = {	---
2502	0x00, 0x00, 0x00, 0x04,	---	2502	0x00, 0x00, 0x00, 0x04,	---
2503	};	---	2503	};	---
2504		---	2504		---
2505	// GP64 Register Class...	---	2505	// GP64 Register Class...	---
2506	const MCPhysReg GP64[] = {	---	2506	const MCPhysReg GP64[] = {	---
2507	Mips::GP_64,	---	2507	Mips::GP_64,	---
2508	};	---	2508	};	---
2509		---	2509		---
2510	// GP64 Bit set.	---	2510	// GP64 Bit set.	---
2511	const uint8_t GP64Bits[] = {	---	2511	const uint8_t GP64Bits[] = {	---
2512	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,	---	2512	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,	---
2513	};	---	2513	};	---
2514		---	2514		---
2515	// GPR64_with_sub_32_in_CPURAReg Register Class...	---	2515	// GPR64_with_sub_32_in_CPURAReg Register Class...	---
2516	const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {	---	2516	const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {	---
2517	Mips::RA_64,	---	2517	Mips::RA_64,	---
2518	};	---	2518	};	---
2519		---	2519		---
2520	// GPR64_with_sub_32_in_CPURAReg Bit set.	---	2520	// GPR64_with_sub_32_in_CPURAReg Bit set.	---
2521	const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {	---	2521	const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {	---
2522	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---	2522	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---
2523	};	---	2523	};	---
2524		---	2524		---
2525	// GPR64_with_sub_32_in_GPR32ZERO Register Class...	---	2525	// GPR64_with_sub_32_in_GPR32ZERO Register Class...	---
2526	const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {	---	2526	const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {	---
2527	Mips::ZERO_64,	---	2527	Mips::ZERO_64,	---
2528	};	---	2528	};	---
2529		---	2529		---
2530	// GPR64_with_sub_32_in_GPR32ZERO Bit set.	---	2530	// GPR64_with_sub_32_in_GPR32ZERO Bit set.	---
2531	const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {	---	2531	const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {	---
2532	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	---	2532	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,	---
2533	};	---	2533	};	---
2534		---	2534		---
2535	// HI64 Register Class...	---	2535	// HI64 Register Class...	---
2536	const MCPhysReg HI64[] = {	---	2536	const MCPhysReg HI64[] = {	---
2537	Mips::HI0_64,	---	2537	Mips::HI0_64,	---
2538	};	---	2538	};	---
2539		---	2539		---
2540	// HI64 Bit set.	---	2540	// HI64 Bit set.	---
2541	const uint8_t HI64Bits[] = {	---	2541	const uint8_t HI64Bits[] = {	---
2542	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,	---	2542	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,	---
2543	};	---	2543	};	---
2544		---	2544		---
2545	// LO64 Register Class...	---	2545	// LO64 Register Class...	---
2546	const MCPhysReg LO64[] = {	---	2546	const MCPhysReg LO64[] = {	---
2547	Mips::LO0_64,	---	2547	Mips::LO0_64,	---
2548	};	---	2548	};	---
2549		---	2549		---
2550	// LO64 Bit set.	---	2550	// LO64 Bit set.	---
2551	const uint8_t LO64Bits[] = {	---	2551	const uint8_t LO64Bits[] = {	---
2552	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---	2552	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,	---
2553	};	---	2553	};	---
2554		---	2554		---
2555	// SP64 Register Class...	---	2555	// SP64 Register Class...	---
2556	const MCPhysReg SP64[] = {	---	2556	const MCPhysReg SP64[] = {	---
2557	Mips::SP_64,	---	2557	Mips::SP_64,	---
2558	};	---	2558	};	---
2559		---	2559		---
2560	// SP64 Bit set.	---	2560	// SP64 Bit set.	---
2561	const uint8_t SP64Bits[] = {	---	2561	const uint8_t SP64Bits[] = {	---
2562	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,	---	2562	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,	---
2563	};	---	2563	};	---
2564		---	2564		---
2565	// MSA128B Register Class...	---	2565	// MSA128B Register Class...	---
2566	const MCPhysReg MSA128B[] = {	---	2566	const MCPhysReg MSA128B[] = {	---
2567	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---	2567	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---
2568	};	---	2568	};	---
2569		---	2569		---
2570	// MSA128B Bit set.	---	2570	// MSA128B Bit set.	---
2571	const uint8_t MSA128BBits[] = {	---	2571	const uint8_t MSA128BBits[] = {	---
2572	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	2572	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
2573	};	---	2573	};	---
2574		---	2574		---
2575	// MSA128D Register Class...	---	2575	// MSA128D Register Class...	---
2576	const MCPhysReg MSA128D[] = {	---	2576	const MCPhysReg MSA128D[] = {	---
2577	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---	2577	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---
2578	};	---	2578	};	---
2579		---	2579		---
2580	// MSA128D Bit set.	---	2580	// MSA128D Bit set.	---
2581	const uint8_t MSA128DBits[] = {	---	2581	const uint8_t MSA128DBits[] = {	---
2582	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	2582	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
2583	};	---	2583	};	---
2584		---	2584		---
2585	// MSA128H Register Class...	---	2585	// MSA128H Register Class...	---
2586	const MCPhysReg MSA128H[] = {	---	2586	const MCPhysReg MSA128H[] = {	---
2587	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---	2587	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---
2588	};	---	2588	};	---
2589		---	2589		---
2590	// MSA128H Bit set.	---	2590	// MSA128H Bit set.	---
2591	const uint8_t MSA128HBits[] = {	---	2591	const uint8_t MSA128HBits[] = {	---
2592	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	2592	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
2593	};	---	2593	};	---
2594		---	2594		---
2595	// MSA128W Register Class...	---	2595	// MSA128W Register Class...	---
2596	const MCPhysReg MSA128W[] = {	---	2596	const MCPhysReg MSA128W[] = {	---
2597	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---	2597	Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,	---
2598	};	---	2598	};	---
2599		---	2599		---
2600	// MSA128W Bit set.	---	2600	// MSA128W Bit set.	---
2601	const uint8_t MSA128WBits[] = {	---	2601	const uint8_t MSA128WBits[] = {	---
2602	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---	2602	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,	---
2603	};	---	2603	};	---
2604		---	2604		---
2605	// MSA128WEvens Register Class...	---	2605	// MSA128WEvens Register Class...	---
2606	const MCPhysReg MSA128WEvens[] = {	---	2606	const MCPhysReg MSA128WEvens[] = {	---
2607	Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,	---	2607	Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,	---
2608	};	---	2608	};	---
2609		---	2609		---
2610	// MSA128WEvens Bit set.	---	2610	// MSA128WEvens Bit set.	---
2611	const uint8_t MSA128WEvensBits[] = {	---	2611	const uint8_t MSA128WEvensBits[] = {	---
2612	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,	---	2612	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,	---
2613	};	---	2613	};	---
2614		---	2614		---
2615	// ACC128 Register Class...	---	2615	// ACC128 Register Class...	---
2616	const MCPhysReg ACC128[] = {	---	2616	const MCPhysReg ACC128[] = {	---
2617	Mips::AC0_64,	---	2617	Mips::AC0_64,	---
2618	};	---	2618	};	---
2619		---	2619		---
2620	// ACC128 Bit set.	---	2620	// ACC128 Bit set.	---
2621	const uint8_t ACC128Bits[] = {	---	2621	const uint8_t ACC128Bits[] = {	---
2622	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,	---	2622	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,	---
2623	};	---	2623	};	---
2624		---	2624		---
2625	} // end anonymous namespace	---	2625	} // end anonymous namespace	---
2626		---	2626		---
2627		---	2627		---
2628	#ifdef __GNUC__	---	2628	#ifdef __GNUC__	---
2629	#pragma GCC diagnostic push	---	2629	#pragma GCC diagnostic push	---
2630	#pragma GCC diagnostic ignored "-Woverlength-strings"	---	2630	#pragma GCC diagnostic ignored "-Woverlength-strings"	---
2631	#endif	---	2631	#endif	---
2632	extern const char MipsRegClassStrings[] = {	---	2632	extern const char MipsRegClassStrings[] = {	---
2633	/* 0 */ "COP0\0"	---	2633	/* 0 */ "COP0\0"	---
2634	/* 5 */ "HI32\0"	---	2634	/* 5 */ "HI32\0"	---
2635	/* 10 */ "LO32\0"	---	2635	/* 10 */ "LO32\0"	---
2636	/* 15 */ "GP32\0"	---	2636	/* 15 */ "GP32\0"	---
2637	/* 20 */ "SP32\0"	---	2637	/* 20 */ "SP32\0"	---
2638	/* 25 */ "FGR32\0"	---	2638	/* 25 */ "FGR32\0"	---
2639	/* 31 */ "GPR32\0"	---	2639	/* 31 */ "GPR32\0"	---
2640	/* 37 */ "COP2\0"	---	2640	/* 37 */ "COP2\0"	---
2641	/* 42 */ "COP3\0"	---	2641	/* 42 */ "COP3\0"	---
2642	/* 47 */ "ACC64\0"	---	2642	/* 47 */ "ACC64\0"	---
2643	/* 53 */ "HI64\0"	---	2643	/* 53 */ "HI64\0"	---
2644	/* 58 */ "LO64\0"	---	2644	/* 58 */ "LO64\0"	---
2645	/* 63 */ "GP64\0"	---	2645	/* 63 */ "GP64\0"	---
2646	/* 68 */ "SP64\0"	---	2646	/* 68 */ "SP64\0"	---
2647	/* 73 */ "AFGR64\0"	---	2647	/* 73 */ "AFGR64\0"	---
2648	/* 80 */ "GPR64\0"	---	2648	/* 80 */ "GPR64\0"	---
2649	/* 86 */ "MSA128F16\0"	---	2649	/* 86 */ "MSA128F16\0"	---
2650	/* 96 */ "GPRMM16\0"	---	2650	/* 96 */ "GPRMM16\0"	---
2651	/* 104 */ "ACC128\0"	---	2651	/* 104 */ "ACC128\0"	---
2652	/* 111 */ "MSA128B\0"	---	2652	/* 111 */ "MSA128B\0"	---
2653	/* 119 */ "FCC\0"	---	2653	/* 119 */ "FCC\0"	---
2654	/* 123 */ "DSPCC\0"	---	2654	/* 123 */ "DSPCC\0"	---
2655	/* 129 */ "FGRCC\0"	---	2655	/* 129 */ "FGRCC\0"	---
2656	/* 135 */ "MSA128D\0"	---	2656	/* 135 */ "MSA128D\0"	---
2657	/* 143 */ "MSA128H\0"	---	2657	/* 143 */ "MSA128H\0"	---
2658	/* 151 */ "OCTEON_MPL\0"	---	2658	/* 151 */ "OCTEON_MPL\0"	---
2659	/* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"	---	2659	/* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"	---
2660	/* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"	---	2660	/* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"	---
2661	/* 227 */ "HI32DSP\0"	---	2661	/* 227 */ "HI32DSP\0"	---
2662	/* 235 */ "LO32DSP\0"	---	2662	/* 235 */ "LO32DSP\0"	---
2663	/* 243 */ "ACC64DSP\0"	---	2663	/* 243 */ "ACC64DSP\0"	---
2664	/* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"	---	2664	/* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"	---
2665	/* 289 */ "OCTEON_P\0"	---	2665	/* 289 */ "OCTEON_P\0"	---
2666	/* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"	---	2666	/* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"	---
2667	/* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"	---	2667	/* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"	---
2668	/* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"	---	2668	/* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"	---
2669	/* 431 */ "CCR\0"	---	2669	/* 431 */ "CCR\0"	---
2670	/* 435 */ "DSPR\0"	---	2670	/* 435 */ "DSPR\0"	---
2671	/* 440 */ "MSA128W\0"	---	2671	/* 440 */ "MSA128W\0"	---
2672	/* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"	---	2672	/* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"	---
2673	/* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"	---	2673	/* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"	---
2674	/* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"	---	2674	/* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"	---
2675	/* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"	---	2675	/* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"	---
2676	/* 650 */ "CPUSPReg\0"	---	2676	/* 650 */ "CPUSPReg\0"	---
2677	/* 659 */ "MSACtrl\0"	---	2677	/* 659 */ "MSACtrl\0"	---
2678	/* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"	---	2678	/* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"	---
2679	/* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"	---	2679	/* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"	---
2680	/* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"	---	2680	/* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"	---
2681	/* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"	---	2681	/* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"	---
2682	/* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"	---	2682	/* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"	---
2683	/* 892 */ "HWRegs\0"	---	2683	/* 892 */ "HWRegs\0"	---
2684	/* 899 */ "MSA128WEvens\0"	---	2684	/* 899 */ "MSA128WEvens\0"	---
2685	/* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"	---	2685	/* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"	---
2686	};	---	2686	};	---
2687	#ifdef __GNUC__	---	2687	#ifdef __GNUC__	---
2688	#pragma GCC diagnostic pop	---	2688	#pragma GCC diagnostic pop	---
2689	#endif	---	2689	#endif	---
2690		---	2690		---
2691	extern const MCRegisterClass MipsMCRegisterClasses[] = {	---	2691	extern const MCRegisterClass MipsMCRegisterClasses[] = {	---
2692	{ MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },	---	2692	{ MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },	---
2693	{ CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },	---	2693	{ CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },	---
2694	{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },	---	2694	{ COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },	---
2695	{ COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },	---	2695	{ COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },	---
2696	{ COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },	---	2696	{ COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },	---
2697	{ DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },	---	2697	{ DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },	---
2698	{ FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },	---	2698	{ FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },	---
2699	{ FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },	---	2699	{ FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },	---
2700	{ GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },	---	2700	{ GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },	---
2701	{ HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },	---	2701	{ HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },	---
2702	{ MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },	---	2702	{ MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },	---
2703	{ GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },	---	2703	{ GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },	---
2704	{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },	---	2704	{ CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },	---
2705	{ CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },	---	2705	{ CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },	---
2706	{ FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },	---	2706	{ FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },	---
2707	{ GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },	---	2707	{ GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },	---
2708	{ GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },	---	2708	{ GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },	---
2709	{ GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },	---	2709	{ GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },	---
2710	{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	---	2710	{ CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	---
2711	{ GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },	---	2711	{ GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },	---
2712	{ GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---	2712	{ GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---
2713	{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },	---	2713	{ CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },	---
2714	{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },	---	2714	{ GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },	---
2715	{ HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },	---	2715	{ HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },	---
2716	{ LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },	---	2716	{ LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },	---
2717	{ CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---	2717	{ CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---
2718	{ GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },	---	2718	{ GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },	---
2719	{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	---	2719	{ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },	---
2720	{ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---	2720	{ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },	---
2721	{ CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },	---	2721	{ CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },	---
2722	{ CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },	---	2722	{ CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },	---
2723	{ DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },	---	2723	{ DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },	---
2724	{ GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },	---	2724	{ GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },	---
2725	{ GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },	---	2725	{ GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },	---
2726	{ HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },	---	2726	{ HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },	---
2727	{ LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },	---	2727	{ LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },	---
2728	{ SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },	---	2728	{ SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },	---
2729	{ FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },	---	2729	{ FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },	---
2730	{ GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },	---	2730	{ GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },	---
2731	{ GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },	---	2731	{ GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },	---
2732	{ AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },	---	2732	{ AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },	---
2733	{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },	---	2733	{ GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },	---
2734	{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },	---	2734	{ GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },	---
2735	{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },	---	2735	{ GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },	---
2736	{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },	---	2736	{ GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },	---
2737	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	---	2737	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	---
2738	{ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },	---	2738	{ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },	---
2739	{ GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---	2739	{ GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---
2740	{ ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },	---	2740	{ ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },	---
2741	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },	---	2741	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },	---
2742	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },	---	2742	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },	---
2743	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---	2743	{ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---
2744	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },	---	2744	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },	---
2745	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	---	2745	{ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },	---
2746	{ OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },	---	2746	{ OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },	---
2747	{ OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },	---	2747	{ OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },	---
2748	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---	2748	{ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },	---
2749	{ ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },	---	2749	{ ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },	---
2750	{ GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },	---	2750	{ GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },	---
2751	{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },	---	2751	{ GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },	---
2752	{ GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },	---	2752	{ GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },	---
2753	{ HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },	---	2753	{ HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },	---
2754	{ LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },	---	2754	{ LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },	---
2755	{ SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },	---	2755	{ SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },	---
2756	{ MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },	---	2756	{ MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },	---
2757	{ MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },	---	2757	{ MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },	---
2758	{ MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },	---	2758	{ MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },	---
2759	{ MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },	---	2759	{ MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },	---
2760	{ MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },	---	2760	{ MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },	---
2761	{ ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },	---	2761	{ ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },	---
2762	};	---	2762	};	---
2763		---	2763		---
2764	// Mips Dwarf<->LLVM register mappings.	---	2764	// Mips Dwarf<->LLVM register mappings.	---
2765	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {	---	2765	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {	---
2766	{ 0U, Mips::ZERO_64 },	---	2766	{ 0U, Mips::ZERO_64 },	---
2767	{ 1U, Mips::AT_64 },	---	2767	{ 1U, Mips::AT_64 },	---
2768	{ 2U, Mips::V0_64 },	---	2768	{ 2U, Mips::V0_64 },	---
2769	{ 3U, Mips::V1_64 },	---	2769	{ 3U, Mips::V1_64 },	---
2770	{ 4U, Mips::A0_64 },	---	2770	{ 4U, Mips::A0_64 },	---
2771	{ 5U, Mips::A1_64 },	---	2771	{ 5U, Mips::A1_64 },	---
2772	{ 6U, Mips::A2_64 },	---	2772	{ 6U, Mips::A2_64 },	---
2773	{ 7U, Mips::A3_64 },	---	2773	{ 7U, Mips::A3_64 },	---
2774	{ 8U, Mips::T0_64 },	---	2774	{ 8U, Mips::T0_64 },	---
2775	{ 9U, Mips::T1_64 },	---	2775	{ 9U, Mips::T1_64 },	---
2776	{ 10U, Mips::T2_64 },	---	2776	{ 10U, Mips::T2_64 },	---
2777	{ 11U, Mips::T3_64 },	---	2777	{ 11U, Mips::T3_64 },	---
2778	{ 12U, Mips::T4_64 },	---	2778	{ 12U, Mips::T4_64 },	---
2779	{ 13U, Mips::T5_64 },	---	2779	{ 13U, Mips::T5_64 },	---
2780	{ 14U, Mips::T6_64 },	---	2780	{ 14U, Mips::T6_64 },	---
2781	{ 15U, Mips::T7_64 },	---	2781	{ 15U, Mips::T7_64 },	---
2782	{ 16U, Mips::S0_64 },	---	2782	{ 16U, Mips::S0_64 },	---
2783	{ 17U, Mips::S1_64 },	---	2783	{ 17U, Mips::S1_64 },	---
2784	{ 18U, Mips::S2_64 },	---	2784	{ 18U, Mips::S2_64 },	---
2785	{ 19U, Mips::S3_64 },	---	2785	{ 19U, Mips::S3_64 },	---
2786	{ 20U, Mips::S4_64 },	---	2786	{ 20U, Mips::S4_64 },	---
2787	{ 21U, Mips::S5_64 },	---	2787	{ 21U, Mips::S5_64 },	---
2788	{ 22U, Mips::S6_64 },	---	2788	{ 22U, Mips::S6_64 },	---
2789	{ 23U, Mips::S7_64 },	---	2789	{ 23U, Mips::S7_64 },	---
2790	{ 24U, Mips::T8_64 },	---	2790	{ 24U, Mips::T8_64 },	---
2791	{ 25U, Mips::T9_64 },	---	2791	{ 25U, Mips::T9_64 },	---
2792	{ 26U, Mips::K0_64 },	---	2792	{ 26U, Mips::K0_64 },	---
2793	{ 27U, Mips::K1_64 },	---	2793	{ 27U, Mips::K1_64 },	---
2794	{ 28U, Mips::GP_64 },	---	2794	{ 28U, Mips::GP_64 },	---
2795	{ 29U, Mips::SP_64 },	---	2795	{ 29U, Mips::SP_64 },	---
2796	{ 30U, Mips::FP_64 },	---	2796	{ 30U, Mips::FP_64 },	---
2797	{ 31U, Mips::RA_64 },	---	2797	{ 31U, Mips::RA_64 },	---
2798	{ 32U, Mips::D0_64 },	---	2798	{ 32U, Mips::D0_64 },	---
2799	{ 33U, Mips::D1_64 },	---	2799	{ 33U, Mips::D1_64 },	---
2800	{ 34U, Mips::D2_64 },	---	2800	{ 34U, Mips::D2_64 },	---
2801	{ 35U, Mips::D3_64 },	---	2801	{ 35U, Mips::D3_64 },	---
2802	{ 36U, Mips::D4_64 },	---	2802	{ 36U, Mips::D4_64 },	---
2803	{ 37U, Mips::D5_64 },	---	2803	{ 37U, Mips::D5_64 },	---
2804	{ 38U, Mips::D6_64 },	---	2804	{ 38U, Mips::D6_64 },	---
2805	{ 39U, Mips::D7_64 },	---	2805	{ 39U, Mips::D7_64 },	---
2806	{ 40U, Mips::D8_64 },	---	2806	{ 40U, Mips::D8_64 },	---
2807	{ 41U, Mips::D9_64 },	---	2807	{ 41U, Mips::D9_64 },	---
2808	{ 42U, Mips::D10_64 },	---	2808	{ 42U, Mips::D10_64 },	---
2809	{ 43U, Mips::D11_64 },	---	2809	{ 43U, Mips::D11_64 },	---
2810	{ 44U, Mips::D12_64 },	---	2810	{ 44U, Mips::D12_64 },	---
2811	{ 45U, Mips::D13_64 },	---	2811	{ 45U, Mips::D13_64 },	---
2812	{ 46U, Mips::D14_64 },	---	2812	{ 46U, Mips::D14_64 },	---
2813	{ 47U, Mips::D15_64 },	---	2813	{ 47U, Mips::D15_64 },	---
2814	{ 48U, Mips::D16_64 },	---	2814	{ 48U, Mips::D16_64 },	---
2815	{ 49U, Mips::D17_64 },	---	2815	{ 49U, Mips::D17_64 },	---
2816	{ 50U, Mips::D18_64 },	---	2816	{ 50U, Mips::D18_64 },	---
2817	{ 51U, Mips::D19_64 },	---	2817	{ 51U, Mips::D19_64 },	---
2818	{ 52U, Mips::D20_64 },	---	2818	{ 52U, Mips::D20_64 },	---
2819	{ 53U, Mips::D21_64 },	---	2819	{ 53U, Mips::D21_64 },	---
2820	{ 54U, Mips::D22_64 },	---	2820	{ 54U, Mips::D22_64 },	---
2821	{ 55U, Mips::D23_64 },	---	2821	{ 55U, Mips::D23_64 },	---
2822	{ 56U, Mips::D24_64 },	---	2822	{ 56U, Mips::D24_64 },	---
2823	{ 57U, Mips::D25_64 },	---	2823	{ 57U, Mips::D25_64 },	---
2824	{ 58U, Mips::D26_64 },	---	2824	{ 58U, Mips::D26_64 },	---
2825	{ 59U, Mips::D27_64 },	---	2825	{ 59U, Mips::D27_64 },	---
2826	{ 60U, Mips::D28_64 },	---	2826	{ 60U, Mips::D28_64 },	---
2827	{ 61U, Mips::D29_64 },	---	2827	{ 61U, Mips::D29_64 },	---
2828	{ 62U, Mips::D30_64 },	---	2828	{ 62U, Mips::D30_64 },	---
2829	{ 63U, Mips::D31_64 },	---	2829	{ 63U, Mips::D31_64 },	---
2830	{ 64U, Mips::HI0 },	---	2830	{ 64U, Mips::HI0 },	---
2831	{ 65U, Mips::LO0 },	---	2831	{ 65U, Mips::LO0 },	---
2832	{ 176U, Mips::HI1 },	---	2832	{ 176U, Mips::HI1 },	---
2833	{ 177U, Mips::LO1 },	---	2833	{ 177U, Mips::LO1 },	---
2834	{ 178U, Mips::HI2 },	---	2834	{ 178U, Mips::HI2 },	---
2835	{ 179U, Mips::LO2 },	---	2835	{ 179U, Mips::LO2 },	---
2836	{ 180U, Mips::HI3 },	---	2836	{ 180U, Mips::HI3 },	---
2837	{ 181U, Mips::LO3 },	---	2837	{ 181U, Mips::LO3 },	---
2838	};	---	2838	};	---
2839	extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);	---	2839	extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);	---
2840		---	2840		---
2841	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {	---	2841	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {	---
2842	{ 0U, Mips::ZERO_64 },	---	2842	{ 0U, Mips::ZERO_64 },	---
2843	{ 1U, Mips::AT_64 },	---	2843	{ 1U, Mips::AT_64 },	---
2844	{ 2U, Mips::V0_64 },	---	2844	{ 2U, Mips::V0_64 },	---
2845	{ 3U, Mips::V1_64 },	---	2845	{ 3U, Mips::V1_64 },	---
2846	{ 4U, Mips::A0_64 },	---	2846	{ 4U, Mips::A0_64 },	---
2847	{ 5U, Mips::A1_64 },	---	2847	{ 5U, Mips::A1_64 },	---
2848	{ 6U, Mips::A2_64 },	---	2848	{ 6U, Mips::A2_64 },	---
2849	{ 7U, Mips::A3_64 },	---	2849	{ 7U, Mips::A3_64 },	---
2850	{ 8U, Mips::T0_64 },	---	2850	{ 8U, Mips::T0_64 },	---
2851	{ 9U, Mips::T1_64 },	---	2851	{ 9U, Mips::T1_64 },	---
2852	{ 10U, Mips::T2_64 },	---	2852	{ 10U, Mips::T2_64 },	---
2853	{ 11U, Mips::T3_64 },	---	2853	{ 11U, Mips::T3_64 },	---
2854	{ 12U, Mips::T4_64 },	---	2854	{ 12U, Mips::T4_64 },	---
2855	{ 13U, Mips::T5_64 },	---	2855	{ 13U, Mips::T5_64 },	---
2856	{ 14U, Mips::T6_64 },	---	2856	{ 14U, Mips::T6_64 },	---
2857	{ 15U, Mips::T7_64 },	---	2857	{ 15U, Mips::T7_64 },	---
2858	{ 16U, Mips::S0_64 },	---	2858	{ 16U, Mips::S0_64 },	---
2859	{ 17U, Mips::S1_64 },	---	2859	{ 17U, Mips::S1_64 },	---
2860	{ 18U, Mips::S2_64 },	---	2860	{ 18U, Mips::S2_64 },	---
2861	{ 19U, Mips::S3_64 },	---	2861	{ 19U, Mips::S3_64 },	---
2862	{ 20U, Mips::S4_64 },	---	2862	{ 20U, Mips::S4_64 },	---
2863	{ 21U, Mips::S5_64 },	---	2863	{ 21U, Mips::S5_64 },	---
2864	{ 22U, Mips::S6_64 },	---	2864	{ 22U, Mips::S6_64 },	---
2865	{ 23U, Mips::S7_64 },	---	2865	{ 23U, Mips::S7_64 },	---
2866	{ 24U, Mips::T8_64 },	---	2866	{ 24U, Mips::T8_64 },	---
2867	{ 25U, Mips::T9_64 },	---	2867	{ 25U, Mips::T9_64 },	---
2868	{ 26U, Mips::K0_64 },	---	2868	{ 26U, Mips::K0_64 },	---
2869	{ 27U, Mips::K1_64 },	---	2869	{ 27U, Mips::K1_64 },	---
2870	{ 28U, Mips::GP_64 },	---	2870	{ 28U, Mips::GP_64 },	---
2871	{ 29U, Mips::SP_64 },	---	2871	{ 29U, Mips::SP_64 },	---
2872	{ 30U, Mips::FP_64 },	---	2872	{ 30U, Mips::FP_64 },	---
2873	{ 31U, Mips::RA_64 },	---	2873	{ 31U, Mips::RA_64 },	---
2874	{ 32U, Mips::D0_64 },	---	2874	{ 32U, Mips::D0_64 },	---
2875	{ 33U, Mips::D1_64 },	---	2875	{ 33U, Mips::D1_64 },	---
2876	{ 34U, Mips::D2_64 },	---	2876	{ 34U, Mips::D2_64 },	---
2877	{ 35U, Mips::D3_64 },	---	2877	{ 35U, Mips::D3_64 },	---
2878	{ 36U, Mips::D4_64 },	---	2878	{ 36U, Mips::D4_64 },	---
2879	{ 37U, Mips::D5_64 },	---	2879	{ 37U, Mips::D5_64 },	---
2880	{ 38U, Mips::D6_64 },	---	2880	{ 38U, Mips::D6_64 },	---
2881	{ 39U, Mips::D7_64 },	---	2881	{ 39U, Mips::D7_64 },	---
2882	{ 40U, Mips::D8_64 },	---	2882	{ 40U, Mips::D8_64 },	---
2883	{ 41U, Mips::D9_64 },	---	2883	{ 41U, Mips::D9_64 },	---
2884	{ 42U, Mips::D10_64 },	---	2884	{ 42U, Mips::D10_64 },	---
2885	{ 43U, Mips::D11_64 },	---	2885	{ 43U, Mips::D11_64 },	---
2886	{ 44U, Mips::D12_64 },	---	2886	{ 44U, Mips::D12_64 },	---
2887	{ 45U, Mips::D13_64 },	---	2887	{ 45U, Mips::D13_64 },	---
2888	{ 46U, Mips::D14_64 },	---	2888	{ 46U, Mips::D14_64 },	---
2889	{ 47U, Mips::D15_64 },	---	2889	{ 47U, Mips::D15_64 },	---
2890	{ 48U, Mips::D16_64 },	---	2890	{ 48U, Mips::D16_64 },	---
2891	{ 49U, Mips::D17_64 },	---	2891	{ 49U, Mips::D17_64 },	---
2892	{ 50U, Mips::D18_64 },	---	2892	{ 50U, Mips::D18_64 },	---
2893	{ 51U, Mips::D19_64 },	---	2893	{ 51U, Mips::D19_64 },	---
2894	{ 52U, Mips::D20_64 },	---	2894	{ 52U, Mips::D20_64 },	---
2895	{ 53U, Mips::D21_64 },	---	2895	{ 53U, Mips::D21_64 },	---
2896	{ 54U, Mips::D22_64 },	---	2896	{ 54U, Mips::D22_64 },	---
2897	{ 55U, Mips::D23_64 },	---	2897	{ 55U, Mips::D23_64 },	---
2898	{ 56U, Mips::D24_64 },	---	2898	{ 56U, Mips::D24_64 },	---
2899	{ 57U, Mips::D25_64 },	---	2899	{ 57U, Mips::D25_64 },	---
2900	{ 58U, Mips::D26_64 },	---	2900	{ 58U, Mips::D26_64 },	---
2901	{ 59U, Mips::D27_64 },	---	2901	{ 59U, Mips::D27_64 },	---
2902	{ 60U, Mips::D28_64 },	---	2902	{ 60U, Mips::D28_64 },	---
2903	{ 61U, Mips::D29_64 },	---	2903	{ 61U, Mips::D29_64 },	---
2904	{ 62U, Mips::D30_64 },	---	2904	{ 62U, Mips::D30_64 },	---
2905	{ 63U, Mips::D31_64 },	---	2905	{ 63U, Mips::D31_64 },	---
2906	{ 64U, Mips::HI0 },	---	2906	{ 64U, Mips::HI0 },	---
2907	{ 65U, Mips::LO0 },	---	2907	{ 65U, Mips::LO0 },	---
2908	{ 176U, Mips::HI1 },	---	2908	{ 176U, Mips::HI1 },	---
2909	{ 177U, Mips::LO1 },	---	2909	{ 177U, Mips::LO1 },	---
2910	{ 178U, Mips::HI2 },	---	2910	{ 178U, Mips::HI2 },	---
2911	{ 179U, Mips::LO2 },	---	2911	{ 179U, Mips::LO2 },	---
2912	{ 180U, Mips::HI3 },	---	2912	{ 180U, Mips::HI3 },	---
2913	{ 181U, Mips::LO3 },	---	2913	{ 181U, Mips::LO3 },	---
2914	};	---	2914	};	---
2915	extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);	---	2915	extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);	---
2916		---	2916		---
2917	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {	---	2917	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {	---
2918	{ Mips::AT, 1U },	---	2918	{ Mips::AT, 1U },	---
2919	{ Mips::FP, 30U },	---	2919	{ Mips::FP, 30U },	---
2920	{ Mips::GP, 28U },	---	2920	{ Mips::GP, 28U },	---
2921	{ Mips::RA, 31U },	---	2921	{ Mips::RA, 31U },	---
2922	{ Mips::SP, 29U },	---	2922	{ Mips::SP, 29U },	---
2923	{ Mips::ZERO, 0U },	---	2923	{ Mips::ZERO, 0U },	---
2924	{ Mips::A0, 4U },	---	2924	{ Mips::A0, 4U },	---
2925	{ Mips::A1, 5U },	---	2925	{ Mips::A1, 5U },	---
2926	{ Mips::A2, 6U },	---	2926	{ Mips::A2, 6U },	---
2927	{ Mips::A3, 7U },	---	2927	{ Mips::A3, 7U },	---
2928	{ Mips::AT_64, 1U },	---	2928	{ Mips::AT_64, 1U },	---
2929	{ Mips::F0, 32U },	---	2929	{ Mips::F0, 32U },	---
2930	{ Mips::F1, 33U },	---	2930	{ Mips::F1, 33U },	---
2931	{ Mips::F2, 34U },	---	2931	{ Mips::F2, 34U },	---
2932	{ Mips::F3, 35U },	---	2932	{ Mips::F3, 35U },	---
2933	{ Mips::F4, 36U },	---	2933	{ Mips::F4, 36U },	---
2934	{ Mips::F5, 37U },	---	2934	{ Mips::F5, 37U },	---
2935	{ Mips::F6, 38U },	---	2935	{ Mips::F6, 38U },	---
2936	{ Mips::F7, 39U },	---	2936	{ Mips::F7, 39U },	---
2937	{ Mips::F8, 40U },	---	2937	{ Mips::F8, 40U },	---
2938	{ Mips::F9, 41U },	---	2938	{ Mips::F9, 41U },	---
2939	{ Mips::F10, 42U },	---	2939	{ Mips::F10, 42U },	---
2940	{ Mips::F11, 43U },	---	2940	{ Mips::F11, 43U },	---
2941	{ Mips::F12, 44U },	---	2941	{ Mips::F12, 44U },	---
2942	{ Mips::F13, 45U },	---	2942	{ Mips::F13, 45U },	---
2943	{ Mips::F14, 46U },	---	2943	{ Mips::F14, 46U },	---
2944	{ Mips::F15, 47U },	---	2944	{ Mips::F15, 47U },	---
2945	{ Mips::F16, 48U },	---	2945	{ Mips::F16, 48U },	---
2946	{ Mips::F17, 49U },	---	2946	{ Mips::F17, 49U },	---
2947	{ Mips::F18, 50U },	---	2947	{ Mips::F18, 50U },	---
2948	{ Mips::F19, 51U },	---	2948	{ Mips::F19, 51U },	---
2949	{ Mips::F20, 52U },	---	2949	{ Mips::F20, 52U },	---
2950	{ Mips::F21, 53U },	---	2950	{ Mips::F21, 53U },	---
2951	{ Mips::F22, 54U },	---	2951	{ Mips::F22, 54U },	---
2952	{ Mips::F23, 55U },	---	2952	{ Mips::F23, 55U },	---
2953	{ Mips::F24, 56U },	---	2953	{ Mips::F24, 56U },	---
2954	{ Mips::F25, 57U },	---	2954	{ Mips::F25, 57U },	---
2955	{ Mips::F26, 58U },	---	2955	{ Mips::F26, 58U },	---
2956	{ Mips::F27, 59U },	---	2956	{ Mips::F27, 59U },	---
2957	{ Mips::F28, 60U },	---	2957	{ Mips::F28, 60U },	---
2958	{ Mips::F29, 61U },	---	2958	{ Mips::F29, 61U },	---
2959	{ Mips::F30, 62U },	---	2959	{ Mips::F30, 62U },	---
2960	{ Mips::F31, 63U },	---	2960	{ Mips::F31, 63U },	---
2961	{ Mips::FP_64, 30U },	---	2961	{ Mips::FP_64, 30U },	---
2962	{ Mips::F_HI0, 32U },	---	2962	{ Mips::F_HI0, 32U },	---
2963	{ Mips::F_HI1, 33U },	---	2963	{ Mips::F_HI1, 33U },	---
2964	{ Mips::F_HI2, 34U },	---	2964	{ Mips::F_HI2, 34U },	---
2965	{ Mips::F_HI3, 35U },	---	2965	{ Mips::F_HI3, 35U },	---
2966	{ Mips::F_HI4, 36U },	---	2966	{ Mips::F_HI4, 36U },	---
2967	{ Mips::F_HI5, 37U },	---	2967	{ Mips::F_HI5, 37U },	---
2968	{ Mips::F_HI6, 38U },	---	2968	{ Mips::F_HI6, 38U },	---
2969	{ Mips::F_HI7, 39U },	---	2969	{ Mips::F_HI7, 39U },	---
2970	{ Mips::F_HI8, 40U },	---	2970	{ Mips::F_HI8, 40U },	---
2971	{ Mips::F_HI9, 41U },	---	2971	{ Mips::F_HI9, 41U },	---
2972	{ Mips::F_HI10, 42U },	---	2972	{ Mips::F_HI10, 42U },	---
2973	{ Mips::F_HI11, 43U },	---	2973	{ Mips::F_HI11, 43U },	---
2974	{ Mips::F_HI12, 44U },	---	2974	{ Mips::F_HI12, 44U },	---
2975	{ Mips::F_HI13, 45U },	---	2975	{ Mips::F_HI13, 45U },	---
2976	{ Mips::F_HI14, 46U },	---	2976	{ Mips::F_HI14, 46U },	---
2977	{ Mips::F_HI15, 47U },	---	2977	{ Mips::F_HI15, 47U },	---
2978	{ Mips::F_HI16, 48U },	---	2978	{ Mips::F_HI16, 48U },	---
2979	{ Mips::F_HI17, 49U },	---	2979	{ Mips::F_HI17, 49U },	---
2980	{ Mips::F_HI18, 50U },	---	2980	{ Mips::F_HI18, 50U },	---
2981	{ Mips::F_HI19, 51U },	---	2981	{ Mips::F_HI19, 51U },	---
2982	{ Mips::F_HI20, 52U },	---	2982	{ Mips::F_HI20, 52U },	---
2983	{ Mips::F_HI21, 53U },	---	2983	{ Mips::F_HI21, 53U },	---
2984	{ Mips::F_HI22, 54U },	---	2984	{ Mips::F_HI22, 54U },	---
2985	{ Mips::F_HI23, 55U },	---	2985	{ Mips::F_HI23, 55U },	---
2986	{ Mips::F_HI24, 56U },	---	2986	{ Mips::F_HI24, 56U },	---
2987	{ Mips::F_HI25, 57U },	---	2987	{ Mips::F_HI25, 57U },	---
2988	{ Mips::F_HI26, 58U },	---	2988	{ Mips::F_HI26, 58U },	---
2989	{ Mips::F_HI27, 59U },	---	2989	{ Mips::F_HI27, 59U },	---
2990	{ Mips::F_HI28, 60U },	---	2990	{ Mips::F_HI28, 60U },	---
2991	{ Mips::F_HI29, 61U },	---	2991	{ Mips::F_HI29, 61U },	---
2992	{ Mips::F_HI30, 62U },	---	2992	{ Mips::F_HI30, 62U },	---
2993	{ Mips::F_HI31, 63U },	---	2993	{ Mips::F_HI31, 63U },	---
2994	{ Mips::GP_64, 28U },	---	2994	{ Mips::GP_64, 28U },	---
2995	{ Mips::HI0, 64U },	---	2995	{ Mips::HI0, 64U },	---
2996	{ Mips::HI1, 176U },	---	2996	{ Mips::HI1, 176U },	---
2997	{ Mips::HI2, 178U },	---	2997	{ Mips::HI2, 178U },	---
2998	{ Mips::HI3, 180U },	---	2998	{ Mips::HI3, 180U },	---
2999	{ Mips::K0, 26U },	---	2999	{ Mips::K0, 26U },	---
3000	{ Mips::K1, 27U },	---	3000	{ Mips::K1, 27U },	---
3001	{ Mips::LO0, 65U },	---	3001	{ Mips::LO0, 65U },	---
3002	{ Mips::LO1, 177U },	---	3002	{ Mips::LO1, 177U },	---
3003	{ Mips::LO2, 179U },	---	3003	{ Mips::LO2, 179U },	---
3004	{ Mips::LO3, 181U },	---	3004	{ Mips::LO3, 181U },	---
3005	{ Mips::RA_64, 31U },	---	3005	{ Mips::RA_64, 31U },	---
3006	{ Mips::S0, 16U },	---	3006	{ Mips::S0, 16U },	---
3007	{ Mips::S1, 17U },	---	3007	{ Mips::S1, 17U },	---
3008	{ Mips::S2, 18U },	---	3008	{ Mips::S2, 18U },	---
3009	{ Mips::S3, 19U },	---	3009	{ Mips::S3, 19U },	---
3010	{ Mips::S4, 20U },	---	3010	{ Mips::S4, 20U },	---
3011	{ Mips::S5, 21U },	---	3011	{ Mips::S5, 21U },	---
3012	{ Mips::S6, 22U },	---	3012	{ Mips::S6, 22U },	---
3013	{ Mips::S7, 23U },	---	3013	{ Mips::S7, 23U },	---
3014	{ Mips::SP_64, 29U },	---	3014	{ Mips::SP_64, 29U },	---
3015	{ Mips::T0, 8U },	---	3015	{ Mips::T0, 8U },	---
3016	{ Mips::T1, 9U },	---	3016	{ Mips::T1, 9U },	---
3017	{ Mips::T2, 10U },	---	3017	{ Mips::T2, 10U },	---
3018	{ Mips::T3, 11U },	---	3018	{ Mips::T3, 11U },	---
3019	{ Mips::T4, 12U },	---	3019	{ Mips::T4, 12U },	---
3020	{ Mips::T5, 13U },	---	3020	{ Mips::T5, 13U },	---
3021	{ Mips::T6, 14U },	---	3021	{ Mips::T6, 14U },	---
3022	{ Mips::T7, 15U },	---	3022	{ Mips::T7, 15U },	---
3023	{ Mips::T8, 24U },	---	3023	{ Mips::T8, 24U },	---
3024	{ Mips::T9, 25U },	---	3024	{ Mips::T9, 25U },	---
3025	{ Mips::V0, 2U },	---	3025	{ Mips::V0, 2U },	---
3026	{ Mips::V1, 3U },	---	3026	{ Mips::V1, 3U },	---
3027	{ Mips::W0, 32U },	---	3027	{ Mips::W0, 32U },	---
3028	{ Mips::W1, 33U },	---	3028	{ Mips::W1, 33U },	---
3029	{ Mips::W2, 34U },	---	3029	{ Mips::W2, 34U },	---
3030	{ Mips::W3, 35U },	---	3030	{ Mips::W3, 35U },	---
3031	{ Mips::W4, 36U },	---	3031	{ Mips::W4, 36U },	---
3032	{ Mips::W5, 37U },	---	3032	{ Mips::W5, 37U },	---
3033	{ Mips::W6, 38U },	---	3033	{ Mips::W6, 38U },	---
3034	{ Mips::W7, 39U },	---	3034	{ Mips::W7, 39U },	---
3035	{ Mips::W8, 40U },	---	3035	{ Mips::W8, 40U },	---
3036	{ Mips::W9, 41U },	---	3036	{ Mips::W9, 41U },	---
3037	{ Mips::W10, 42U },	---	3037	{ Mips::W10, 42U },	---
3038	{ Mips::W11, 43U },	---	3038	{ Mips::W11, 43U },	---
3039	{ Mips::W12, 44U },	---	3039	{ Mips::W12, 44U },	---
3040	{ Mips::W13, 45U },	---	3040	{ Mips::W13, 45U },	---
3041	{ Mips::W14, 46U },	---	3041	{ Mips::W14, 46U },	---
3042	{ Mips::W15, 47U },	---	3042	{ Mips::W15, 47U },	---
3043	{ Mips::W16, 48U },	---	3043	{ Mips::W16, 48U },	---
3044	{ Mips::W17, 49U },	---	3044	{ Mips::W17, 49U },	---
3045	{ Mips::W18, 50U },	---	3045	{ Mips::W18, 50U },	---
3046	{ Mips::W19, 51U },	---	3046	{ Mips::W19, 51U },	---
3047	{ Mips::W20, 52U },	---	3047	{ Mips::W20, 52U },	---
3048	{ Mips::W21, 53U },	---	3048	{ Mips::W21, 53U },	---
3049	{ Mips::W22, 54U },	---	3049	{ Mips::W22, 54U },	---
3050	{ Mips::W23, 55U },	---	3050	{ Mips::W23, 55U },	---
3051	{ Mips::W24, 56U },	---	3051	{ Mips::W24, 56U },	---
3052	{ Mips::W25, 57U },	---	3052	{ Mips::W25, 57U },	---
3053	{ Mips::W26, 58U },	---	3053	{ Mips::W26, 58U },	---
3054	{ Mips::W27, 59U },	---	3054	{ Mips::W27, 59U },	---
3055	{ Mips::W28, 60U },	---	3055	{ Mips::W28, 60U },	---
3056	{ Mips::W29, 61U },	---	3056	{ Mips::W29, 61U },	---
3057	{ Mips::W30, 62U },	---	3057	{ Mips::W30, 62U },	---
3058	{ Mips::W31, 63U },	---	3058	{ Mips::W31, 63U },	---
3059	{ Mips::ZERO_64, 0U },	---	3059	{ Mips::ZERO_64, 0U },	---
3060	{ Mips::A0_64, 4U },	---	3060	{ Mips::A0_64, 4U },	---
3061	{ Mips::A1_64, 5U },	---	3061	{ Mips::A1_64, 5U },	---
3062	{ Mips::A2_64, 6U },	---	3062	{ Mips::A2_64, 6U },	---
3063	{ Mips::A3_64, 7U },	---	3063	{ Mips::A3_64, 7U },	---
3064	{ Mips::D0_64, 32U },	---	3064	{ Mips::D0_64, 32U },	---
3065	{ Mips::D1_64, 33U },	---	3065	{ Mips::D1_64, 33U },	---
3066	{ Mips::D2_64, 34U },	---	3066	{ Mips::D2_64, 34U },	---
3067	{ Mips::D3_64, 35U },	---	3067	{ Mips::D3_64, 35U },	---
3068	{ Mips::D4_64, 36U },	---	3068	{ Mips::D4_64, 36U },	---
3069	{ Mips::D5_64, 37U },	---	3069	{ Mips::D5_64, 37U },	---
3070	{ Mips::D6_64, 38U },	---	3070	{ Mips::D6_64, 38U },	---
3071	{ Mips::D7_64, 39U },	---	3071	{ Mips::D7_64, 39U },	---
3072	{ Mips::D8_64, 40U },	---	3072	{ Mips::D8_64, 40U },	---
3073	{ Mips::D9_64, 41U },	---	3073	{ Mips::D9_64, 41U },	---
3074	{ Mips::D10_64, 42U },	---	3074	{ Mips::D10_64, 42U },	---
3075	{ Mips::D11_64, 43U },	---	3075	{ Mips::D11_64, 43U },	---
3076	{ Mips::D12_64, 44U },	---	3076	{ Mips::D12_64, 44U },	---
3077	{ Mips::D13_64, 45U },	---	3077	{ Mips::D13_64, 45U },	---
3078	{ Mips::D14_64, 46U },	---	3078	{ Mips::D14_64, 46U },	---
3079	{ Mips::D15_64, 47U },	---	3079	{ Mips::D15_64, 47U },	---
3080	{ Mips::D16_64, 48U },	---	3080	{ Mips::D16_64, 48U },	---
3081	{ Mips::D17_64, 49U },	---	3081	{ Mips::D17_64, 49U },	---
3082	{ Mips::D18_64, 50U },	---	3082	{ Mips::D18_64, 50U },	---
3083	{ Mips::D19_64, 51U },	---	3083	{ Mips::D19_64, 51U },	---
3084	{ Mips::D20_64, 52U },	---	3084	{ Mips::D20_64, 52U },	---
3085	{ Mips::D21_64, 53U },	---	3085	{ Mips::D21_64, 53U },	---
3086	{ Mips::D22_64, 54U },	---	3086	{ Mips::D22_64, 54U },	---
3087	{ Mips::D23_64, 55U },	---	3087	{ Mips::D23_64, 55U },	---
3088	{ Mips::D24_64, 56U },	---	3088	{ Mips::D24_64, 56U },	---
3089	{ Mips::D25_64, 57U },	---	3089	{ Mips::D25_64, 57U },	---
3090	{ Mips::D26_64, 58U },	---	3090	{ Mips::D26_64, 58U },	---
3091	{ Mips::D27_64, 59U },	---	3091	{ Mips::D27_64, 59U },	---
3092	{ Mips::D28_64, 60U },	---	3092	{ Mips::D28_64, 60U },	---
3093	{ Mips::D29_64, 61U },	---	3093	{ Mips::D29_64, 61U },	---
3094	{ Mips::D30_64, 62U },	---	3094	{ Mips::D30_64, 62U },	---
3095	{ Mips::D31_64, 63U },	---	3095	{ Mips::D31_64, 63U },	---
3096	{ Mips::K0_64, 26U },	---	3096	{ Mips::K0_64, 26U },	---
3097	{ Mips::K1_64, 27U },	---	3097	{ Mips::K1_64, 27U },	---
3098	{ Mips::S0_64, 16U },	---	3098	{ Mips::S0_64, 16U },	---
3099	{ Mips::S1_64, 17U },	---	3099	{ Mips::S1_64, 17U },	---
3100	{ Mips::S2_64, 18U },	---	3100	{ Mips::S2_64, 18U },	---
3101	{ Mips::S3_64, 19U },	---	3101	{ Mips::S3_64, 19U },	---
3102	{ Mips::S4_64, 20U },	---	3102	{ Mips::S4_64, 20U },	---
3103	{ Mips::S5_64, 21U },	---	3103	{ Mips::S5_64, 21U },	---
3104	{ Mips::S6_64, 22U },	---	3104	{ Mips::S6_64, 22U },	---
3105	{ Mips::S7_64, 23U },	---	3105	{ Mips::S7_64, 23U },	---
3106	{ Mips::T0_64, 8U },	---	3106	{ Mips::T0_64, 8U },	---
3107	{ Mips::T1_64, 9U },	---	3107	{ Mips::T1_64, 9U },	---
3108	{ Mips::T2_64, 10U },	---	3108	{ Mips::T2_64, 10U },	---
3109	{ Mips::T3_64, 11U },	---	3109	{ Mips::T3_64, 11U },	---
3110	{ Mips::T4_64, 12U },	---	3110	{ Mips::T4_64, 12U },	---
3111	{ Mips::T5_64, 13U },	---	3111	{ Mips::T5_64, 13U },	---
3112	{ Mips::T6_64, 14U },	---	3112	{ Mips::T6_64, 14U },	---
3113	{ Mips::T7_64, 15U },	---	3113	{ Mips::T7_64, 15U },	---
3114	{ Mips::T8_64, 24U },	---	3114	{ Mips::T8_64, 24U },	---
3115	{ Mips::T9_64, 25U },	---	3115	{ Mips::T9_64, 25U },	---
3116	{ Mips::V0_64, 2U },	---	3116	{ Mips::V0_64, 2U },	---
3117	{ Mips::V1_64, 3U },	---	3117	{ Mips::V1_64, 3U },	---
3118	};	---	3118	};	---
3119	extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);	---	3119	extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);	---
3120		---	3120		---
3121	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {	---	3121	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {	---
3122	{ Mips::AT, 1U },	---	3122	{ Mips::AT, 1U },	---
3123	{ Mips::FP, 30U },	---	3123	{ Mips::FP, 30U },	---
3124	{ Mips::GP, 28U },	---	3124	{ Mips::GP, 28U },	---
3125	{ Mips::RA, 31U },	---	3125	{ Mips::RA, 31U },	---
3126	{ Mips::SP, 29U },	---	3126	{ Mips::SP, 29U },	---
3127	{ Mips::ZERO, 0U },	---	3127	{ Mips::ZERO, 0U },	---
3128	{ Mips::A0, 4U },	---	3128	{ Mips::A0, 4U },	---
3129	{ Mips::A1, 5U },	---	3129	{ Mips::A1, 5U },	---
3130	{ Mips::A2, 6U },	---	3130	{ Mips::A2, 6U },	---
3131	{ Mips::A3, 7U },	---	3131	{ Mips::A3, 7U },	---
3132	{ Mips::AT_64, 1U },	---	3132	{ Mips::AT_64, 1U },	---
3133	{ Mips::F0, 32U },	---	3133	{ Mips::F0, 32U },	---
3134	{ Mips::F1, 33U },	---	3134	{ Mips::F1, 33U },	---
3135	{ Mips::F2, 34U },	---	3135	{ Mips::F2, 34U },	---
3136	{ Mips::F3, 35U },	---	3136	{ Mips::F3, 35U },	---
3137	{ Mips::F4, 36U },	---	3137	{ Mips::F4, 36U },	---
3138	{ Mips::F5, 37U },	---	3138	{ Mips::F5, 37U },	---
3139	{ Mips::F6, 38U },	---	3139	{ Mips::F6, 38U },	---
3140	{ Mips::F7, 39U },	---	3140	{ Mips::F7, 39U },	---
3141	{ Mips::F8, 40U },	---	3141	{ Mips::F8, 40U },	---
3142	{ Mips::F9, 41U },	---	3142	{ Mips::F9, 41U },	---
3143	{ Mips::F10, 42U },	---	3143	{ Mips::F10, 42U },	---
3144	{ Mips::F11, 43U },	---	3144	{ Mips::F11, 43U },	---
3145	{ Mips::F12, 44U },	---	3145	{ Mips::F12, 44U },	---
3146	{ Mips::F13, 45U },	---	3146	{ Mips::F13, 45U },	---
3147	{ Mips::F14, 46U },	---	3147	{ Mips::F14, 46U },	---
3148	{ Mips::F15, 47U },	---	3148	{ Mips::F15, 47U },	---
3149	{ Mips::F16, 48U },	---	3149	{ Mips::F16, 48U },	---
3150	{ Mips::F17, 49U },	---	3150	{ Mips::F17, 49U },	---
3151	{ Mips::F18, 50U },	---	3151	{ Mips::F18, 50U },	---
3152	{ Mips::F19, 51U },	---	3152	{ Mips::F19, 51U },	---
3153	{ Mips::F20, 52U },	---	3153	{ Mips::F20, 52U },	---
3154	{ Mips::F21, 53U },	---	3154	{ Mips::F21, 53U },	---
3155	{ Mips::F22, 54U },	---	3155	{ Mips::F22, 54U },	---
3156	{ Mips::F23, 55U },	---	3156	{ Mips::F23, 55U },	---
3157	{ Mips::F24, 56U },	---	3157	{ Mips::F24, 56U },	---
3158	{ Mips::F25, 57U },	---	3158	{ Mips::F25, 57U },	---
3159	{ Mips::F26, 58U },	---	3159	{ Mips::F26, 58U },	---
3160	{ Mips::F27, 59U },	---	3160	{ Mips::F27, 59U },	---
3161	{ Mips::F28, 60U },	---	3161	{ Mips::F28, 60U },	---
3162	{ Mips::F29, 61U },	---	3162	{ Mips::F29, 61U },	---
3163	{ Mips::F30, 62U },	---	3163	{ Mips::F30, 62U },	---
3164	{ Mips::F31, 63U },	---	3164	{ Mips::F31, 63U },	---
3165	{ Mips::FP_64, 30U },	---	3165	{ Mips::FP_64, 30U },	---
3166	{ Mips::F_HI0, 32U },	---	3166	{ Mips::F_HI0, 32U },	---
3167	{ Mips::F_HI1, 33U },	---	3167	{ Mips::F_HI1, 33U },	---
3168	{ Mips::F_HI2, 34U },	---	3168	{ Mips::F_HI2, 34U },	---
3169	{ Mips::F_HI3, 35U },	---	3169	{ Mips::F_HI3, 35U },	---
3170	{ Mips::F_HI4, 36U },	---	3170	{ Mips::F_HI4, 36U },	---
3171	{ Mips::F_HI5, 37U },	---	3171	{ Mips::F_HI5, 37U },	---
3172	{ Mips::F_HI6, 38U },	---	3172	{ Mips::F_HI6, 38U },	---
3173	{ Mips::F_HI7, 39U },	---	3173	{ Mips::F_HI7, 39U },	---
3174	{ Mips::F_HI8, 40U },	---	3174	{ Mips::F_HI8, 40U },	---
3175	{ Mips::F_HI9, 41U },	---	3175	{ Mips::F_HI9, 41U },	---
3176	{ Mips::F_HI10, 42U },	---	3176	{ Mips::F_HI10, 42U },	---
3177	{ Mips::F_HI11, 43U },	---	3177	{ Mips::F_HI11, 43U },	---
3178	{ Mips::F_HI12, 44U },	---	3178	{ Mips::F_HI12, 44U },	---
3179	{ Mips::F_HI13, 45U },	---	3179	{ Mips::F_HI13, 45U },	---
3180	{ Mips::F_HI14, 46U },	---	3180	{ Mips::F_HI14, 46U },	---
3181	{ Mips::F_HI15, 47U },	---	3181	{ Mips::F_HI15, 47U },	---
3182	{ Mips::F_HI16, 48U },	---	3182	{ Mips::F_HI16, 48U },	---
3183	{ Mips::F_HI17, 49U },	---	3183	{ Mips::F_HI17, 49U },	---
3184	{ Mips::F_HI18, 50U },	---	3184	{ Mips::F_HI18, 50U },	---
3185	{ Mips::F_HI19, 51U },	---	3185	{ Mips::F_HI19, 51U },	---
3186	{ Mips::F_HI20, 52U },	---	3186	{ Mips::F_HI20, 52U },	---
3187	{ Mips::F_HI21, 53U },	---	3187	{ Mips::F_HI21, 53U },	---
3188	{ Mips::F_HI22, 54U },	---	3188	{ Mips::F_HI22, 54U },	---
3189	{ Mips::F_HI23, 55U },	---	3189	{ Mips::F_HI23, 55U },	---
3190	{ Mips::F_HI24, 56U },	---	3190	{ Mips::F_HI24, 56U },	---
3191	{ Mips::F_HI25, 57U },	---	3191	{ Mips::F_HI25, 57U },	---
3192	{ Mips::F_HI26, 58U },	---	3192	{ Mips::F_HI26, 58U },	---
3193	{ Mips::F_HI27, 59U },	---	3193	{ Mips::F_HI27, 59U },	---
3194	{ Mips::F_HI28, 60U },	---	3194	{ Mips::F_HI28, 60U },	---
3195	{ Mips::F_HI29, 61U },	---	3195	{ Mips::F_HI29, 61U },	---
3196	{ Mips::F_HI30, 62U },	---	3196	{ Mips::F_HI30, 62U },	---
3197	{ Mips::F_HI31, 63U },	---	3197	{ Mips::F_HI31, 63U },	---
3198	{ Mips::GP_64, 28U },	---	3198	{ Mips::GP_64, 28U },	---
3199	{ Mips::HI0, 64U },	---	3199	{ Mips::HI0, 64U },	---
3200	{ Mips::HI1, 176U },	---	3200	{ Mips::HI1, 176U },	---
3201	{ Mips::HI2, 178U },	---	3201	{ Mips::HI2, 178U },	---
3202	{ Mips::HI3, 180U },	---	3202	{ Mips::HI3, 180U },	---
3203	{ Mips::K0, 26U },	---	3203	{ Mips::K0, 26U },	---
3204	{ Mips::K1, 27U },	---	3204	{ Mips::K1, 27U },	---
3205	{ Mips::LO0, 65U },	---	3205	{ Mips::LO0, 65U },	---
3206	{ Mips::LO1, 177U },	---	3206	{ Mips::LO1, 177U },	---
3207	{ Mips::LO2, 179U },	---	3207	{ Mips::LO2, 179U },	---
3208	{ Mips::LO3, 181U },	---	3208	{ Mips::LO3, 181U },	---
3209	{ Mips::RA_64, 31U },	---	3209	{ Mips::RA_64, 31U },	---
3210	{ Mips::S0, 16U },	---	3210	{ Mips::S0, 16U },	---
3211	{ Mips::S1, 17U },	---	3211	{ Mips::S1, 17U },	---
3212	{ Mips::S2, 18U },	---	3212	{ Mips::S2, 18U },	---
3213	{ Mips::S3, 19U },	---	3213	{ Mips::S3, 19U },	---
3214	{ Mips::S4, 20U },	---	3214	{ Mips::S4, 20U },	---
3215	{ Mips::S5, 21U },	---	3215	{ Mips::S5, 21U },	---
3216	{ Mips::S6, 22U },	---	3216	{ Mips::S6, 22U },	---
3217	{ Mips::S7, 23U },	---	3217	{ Mips::S7, 23U },	---
3218	{ Mips::SP_64, 29U },	---	3218	{ Mips::SP_64, 29U },	---
3219	{ Mips::T0, 8U },	---	3219	{ Mips::T0, 8U },	---
3220	{ Mips::T1, 9U },	---	3220	{ Mips::T1, 9U },	---
3221	{ Mips::T2, 10U },	---	3221	{ Mips::T2, 10U },	---
3222	{ Mips::T3, 11U },	---	3222	{ Mips::T3, 11U },	---
3223	{ Mips::T4, 12U },	---	3223	{ Mips::T4, 12U },	---
3224	{ Mips::T5, 13U },	---	3224	{ Mips::T5, 13U },	---
3225	{ Mips::T6, 14U },	---	3225	{ Mips::T6, 14U },	---
3226	{ Mips::T7, 15U },	---	3226	{ Mips::T7, 15U },	---
3227	{ Mips::T8, 24U },	---	3227	{ Mips::T8, 24U },	---
3228	{ Mips::T9, 25U },	---	3228	{ Mips::T9, 25U },	---
3229	{ Mips::V0, 2U },	---	3229	{ Mips::V0, 2U },	---
3230	{ Mips::V1, 3U },	---	3230	{ Mips::V1, 3U },	---
3231	{ Mips::W0, 32U },	---	3231	{ Mips::W0, 32U },	---
3232	{ Mips::W1, 33U },	---	3232	{ Mips::W1, 33U },	---
3233	{ Mips::W2, 34U },	---	3233	{ Mips::W2, 34U },	---
3234	{ Mips::W3, 35U },	---	3234	{ Mips::W3, 35U },	---
3235	{ Mips::W4, 36U },	---	3235	{ Mips::W4, 36U },	---
3236	{ Mips::W5, 37U },	---	3236	{ Mips::W5, 37U },	---
3237	{ Mips::W6, 38U },	---	3237	{ Mips::W6, 38U },	---
3238	{ Mips::W7, 39U },	---	3238	{ Mips::W7, 39U },	---
3239	{ Mips::W8, 40U },	---	3239	{ Mips::W8, 40U },	---
3240	{ Mips::W9, 41U },	---	3240	{ Mips::W9, 41U },	---
3241	{ Mips::W10, 42U },	---	3241	{ Mips::W10, 42U },	---
3242	{ Mips::W11, 43U },	---	3242	{ Mips::W11, 43U },	---
3243	{ Mips::W12, 44U },	---	3243	{ Mips::W12, 44U },	---
3244	{ Mips::W13, 45U },	---	3244	{ Mips::W13, 45U },	---
3245	{ Mips::W14, 46U },	---	3245	{ Mips::W14, 46U },	---
3246	{ Mips::W15, 47U },	---	3246	{ Mips::W15, 47U },	---
3247	{ Mips::W16, 48U },	---	3247	{ Mips::W16, 48U },	---
3248	{ Mips::W17, 49U },	---	3248	{ Mips::W17, 49U },	---
3249	{ Mips::W18, 50U },	---	3249	{ Mips::W18, 50U },	---
3250	{ Mips::W19, 51U },	---	3250	{ Mips::W19, 51U },	---
3251	{ Mips::W20, 52U },	---	3251	{ Mips::W20, 52U },	---
3252	{ Mips::W21, 53U },	---	3252	{ Mips::W21, 53U },	---
3253	{ Mips::W22, 54U },	---	3253	{ Mips::W22, 54U },	---
3254	{ Mips::W23, 55U },	---	3254	{ Mips::W23, 55U },	---
3255	{ Mips::W24, 56U },	---	3255	{ Mips::W24, 56U },	---
3256	{ Mips::W25, 57U },	---	3256	{ Mips::W25, 57U },	---
3257	{ Mips::W26, 58U },	---	3257	{ Mips::W26, 58U },	---
3258	{ Mips::W27, 59U },	---	3258	{ Mips::W27, 59U },	---
3259	{ Mips::W28, 60U },	---	3259	{ Mips::W28, 60U },	---
3260	{ Mips::W29, 61U },	---	3260	{ Mips::W29, 61U },	---
3261	{ Mips::W30, 62U },	---	3261	{ Mips::W30, 62U },	---
3262	{ Mips::W31, 63U },	---	3262	{ Mips::W31, 63U },	---
3263	{ Mips::ZERO_64, 0U },	---	3263	{ Mips::ZERO_64, 0U },	---
3264	{ Mips::A0_64, 4U },	---	3264	{ Mips::A0_64, 4U },	---
3265	{ Mips::A1_64, 5U },	---	3265	{ Mips::A1_64, 5U },	---
3266	{ Mips::A2_64, 6U },	---	3266	{ Mips::A2_64, 6U },	---
3267	{ Mips::A3_64, 7U },	---	3267	{ Mips::A3_64, 7U },	---
3268	{ Mips::D0_64, 32U },	---	3268	{ Mips::D0_64, 32U },	---
3269	{ Mips::D1_64, 33U },	---	3269	{ Mips::D1_64, 33U },	---
3270	{ Mips::D2_64, 34U },	---	3270	{ Mips::D2_64, 34U },	---
3271	{ Mips::D3_64, 35U },	---	3271	{ Mips::D3_64, 35U },	---
3272	{ Mips::D4_64, 36U },	---	3272	{ Mips::D4_64, 36U },	---
3273	{ Mips::D5_64, 37U },	---	3273	{ Mips::D5_64, 37U },	---
3274	{ Mips::D6_64, 38U },	---	3274	{ Mips::D6_64, 38U },	---
3275	{ Mips::D7_64, 39U },	---	3275	{ Mips::D7_64, 39U },	---
3276	{ Mips::D8_64, 40U },	---	3276	{ Mips::D8_64, 40U },	---
3277	{ Mips::D9_64, 41U },	---	3277	{ Mips::D9_64, 41U },	---
3278	{ Mips::D10_64, 42U },	---	3278	{ Mips::D10_64, 42U },	---
3279	{ Mips::D11_64, 43U },	---	3279	{ Mips::D11_64, 43U },	---
3280	{ Mips::D12_64, 44U },	---	3280	{ Mips::D12_64, 44U },	---
3281	{ Mips::D13_64, 45U },	---	3281	{ Mips::D13_64, 45U },	---
3282	{ Mips::D14_64, 46U },	---	3282	{ Mips::D14_64, 46U },	---
3283	{ Mips::D15_64, 47U },	---	3283	{ Mips::D15_64, 47U },	---
3284	{ Mips::D16_64, 48U },	---	3284	{ Mips::D16_64, 48U },	---
3285	{ Mips::D17_64, 49U },	---	3285	{ Mips::D17_64, 49U },	---
3286	{ Mips::D18_64, 50U },	---	3286	{ Mips::D18_64, 50U },	---
3287	{ Mips::D19_64, 51U },	---	3287	{ Mips::D19_64, 51U },	---
3288	{ Mips::D20_64, 52U },	---	3288	{ Mips::D20_64, 52U },	---
3289	{ Mips::D21_64, 53U },	---	3289	{ Mips::D21_64, 53U },	---
3290	{ Mips::D22_64, 54U },	---	3290	{ Mips::D22_64, 54U },	---
3291	{ Mips::D23_64, 55U },	---	3291	{ Mips::D23_64, 55U },	---
3292	{ Mips::D24_64, 56U },	---	3292	{ Mips::D24_64, 56U },	---
3293	{ Mips::D25_64, 57U },	---	3293	{ Mips::D25_64, 57U },	---
3294	{ Mips::D26_64, 58U },	---	3294	{ Mips::D26_64, 58U },	---
3295	{ Mips::D27_64, 59U },	---	3295	{ Mips::D27_64, 59U },	---
3296	{ Mips::D28_64, 60U },	---	3296	{ Mips::D28_64, 60U },	---
3297	{ Mips::D29_64, 61U },	---	3297	{ Mips::D29_64, 61U },	---
3298	{ Mips::D30_64, 62U },	---	3298	{ Mips::D30_64, 62U },	---
3299	{ Mips::D31_64, 63U },	---	3299	{ Mips::D31_64, 63U },	---
3300	{ Mips::K0_64, 26U },	---	3300	{ Mips::K0_64, 26U },	---
3301	{ Mips::K1_64, 27U },	---	3301	{ Mips::K1_64, 27U },	---
3302	{ Mips::S0_64, 16U },	---	3302	{ Mips::S0_64, 16U },	---
3303	{ Mips::S1_64, 17U },	---	3303	{ Mips::S1_64, 17U },	---
3304	{ Mips::S2_64, 18U },	---	3304	{ Mips::S2_64, 18U },	---
3305	{ Mips::S3_64, 19U },	---	3305	{ Mips::S3_64, 19U },	---
3306	{ Mips::S4_64, 20U },	---	3306	{ Mips::S4_64, 20U },	---
3307	{ Mips::S5_64, 21U },	---	3307	{ Mips::S5_64, 21U },	---
3308	{ Mips::S6_64, 22U },	---	3308	{ Mips::S6_64, 22U },	---
3309	{ Mips::S7_64, 23U },	---	3309	{ Mips::S7_64, 23U },	---
3310	{ Mips::T0_64, 8U },	---	3310	{ Mips::T0_64, 8U },	---
3311	{ Mips::T1_64, 9U },	---	3311	{ Mips::T1_64, 9U },	---
3312	{ Mips::T2_64, 10U },	---	3312	{ Mips::T2_64, 10U },	---
3313	{ Mips::T3_64, 11U },	---	3313	{ Mips::T3_64, 11U },	---
3314	{ Mips::T4_64, 12U },	---	3314	{ Mips::T4_64, 12U },	---
3315	{ Mips::T5_64, 13U },	---	3315	{ Mips::T5_64, 13U },	---
3316	{ Mips::T6_64, 14U },	---	3316	{ Mips::T6_64, 14U },	---
3317	{ Mips::T7_64, 15U },	---	3317	{ Mips::T7_64, 15U },	---
3318	{ Mips::T8_64, 24U },	---	3318	{ Mips::T8_64, 24U },	---
3319	{ Mips::T9_64, 25U },	---	3319	{ Mips::T9_64, 25U },	---
3320	{ Mips::V0_64, 2U },	---	3320	{ Mips::V0_64, 2U },	---
3321	{ Mips::V1_64, 3U },	---	3321	{ Mips::V1_64, 3U },	---
3322	};	---	3322	};	---
3323	extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);	---	3323	extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);	---
3324		---	3324		---
3325	extern const uint16_t MipsRegEncodingTable[] = {	---	3325	extern const uint16_t MipsRegEncodingTable[] = {	---
3326	0,	---	3326	0,	---
3327	1,	---	3327	1,	---
3328	0,	---	3328	0,	---
3329	0,	---	3329	0,	---
3330	0,	---	3330	0,	---
3331	0,	---	3331	0,	---
3332	0,	---	3332	0,	---
3333	0,	---	3333	0,	---
3334	30,	---	3334	30,	---
3335	28,	---	3335	28,	---
3336	2,	---	3336	2,	---
3337	1,	---	3337	1,	---
3338	0,	---	3338	0,	---
3339	6,	---	3339	6,	---
3340	4,	---	3340	4,	---
3341	5,	---	3341	5,	---
3342	3,	---	3342	3,	---
3343	7,	---	3343	7,	---
3344	0,	---	3344	0,	---
3345	31,	---	3345	31,	---
3346	29,	---	3346	29,	---
3347	0,	---	3347	0,	---
3348	4,	---	3348	4,	---
3349	5,	---	3349	5,	---
3350	6,	---	3350	6,	---
3351	7,	---	3351	7,	---
3352	0,	---	3352	0,	---
3353	1,	---	3353	1,	---
3354	2,	---	3354	2,	---
3355	3,	---	3355	3,	---
3356	1,	---	3356	1,	---
3357	0,	---	3357	0,	---
3358	1,	---	3358	1,	---
3359	2,	---	3359	2,	---
3360	3,	---	3360	3,	---
3361	4,	---	3361	4,	---
3362	5,	---	3362	5,	---
3363	6,	---	3363	6,	---
3364	7,	---	3364	7,	---
3365	8,	---	3365	8,	---
3366	9,	---	3366	9,	---
3367	0,	---	3367	0,	---
3368	1,	---	3368	1,	---
3369	2,	---	3369	2,	---
3370	3,	---	3370	3,	---
3371	4,	---	3371	4,	---
3372	5,	---	3372	5,	---
3373	6,	---	3373	6,	---
3374	7,	---	3374	7,	---
3375	8,	---	3375	8,	---
3376	9,	---	3376	9,	---
3377	0,	---	3377	0,	---
3378	1,	---	3378	1,	---
3379	2,	---	3379	2,	---
3380	3,	---	3380	3,	---
3381	4,	---	3381	4,	---
3382	5,	---	3382	5,	---
3383	6,	---	3383	6,	---
3384	7,	---	3384	7,	---
3385	8,	---	3385	8,	---
3386	9,	---	3386	9,	---
3387	10,	---	3387	10,	---
3388	11,	---	3388	11,	---
3389	12,	---	3389	12,	---
3390	13,	---	3390	13,	---
3391	14,	---	3391	14,	---
3392	15,	---	3392	15,	---
3393	16,	---	3393	16,	---
3394	17,	---	3394	17,	---
3395	18,	---	3395	18,	---
3396	19,	---	3396	19,	---
3397	20,	---	3397	20,	---
3398	21,	---	3398	21,	---
3399	22,	---	3399	22,	---
3400	23,	---	3400	23,	---
3401	24,	---	3401	24,	---
3402	25,	---	3402	25,	---
3403	26,	---	3403	26,	---
3404	27,	---	3404	27,	---
3405	28,	---	3405	28,	---
3406	29,	---	3406	29,	---
3407	30,	---	3407	30,	---
3408	31,	---	3408	31,	---
3409	10,	---	3409	10,	---
3410	11,	---	3410	11,	---
3411	12,	---	3411	12,	---
3412	13,	---	3412	13,	---
3413	14,	---	3413	14,	---
3414	15,	---	3414	15,	---
3415	16,	---	3415	16,	---
3416	17,	---	3416	17,	---
3417	18,	---	3417	18,	---
3418	19,	---	3418	19,	---
3419	20,	---	3419	20,	---
3420	21,	---	3420	21,	---
3421	22,	---	3421	22,	---
3422	23,	---	3422	23,	---
3423	24,	---	3423	24,	---
3424	25,	---	3424	25,	---
3425	26,	---	3425	26,	---
3426	27,	---	3426	27,	---
3427	28,	---	3427	28,	---
3428	29,	---	3428	29,	---
3429	30,	---	3429	30,	---
3430	31,	---	3430	31,	---
3431	10,	---	3431	10,	---
3432	11,	---	3432	11,	---
3433	12,	---	3433	12,	---
3434	13,	---	3434	13,	---
3435	14,	---	3435	14,	---
3436	15,	---	3436	15,	---
3437	16,	---	3437	16,	---
3438	17,	---	3438	17,	---
3439	18,	---	3439	18,	---
3440	19,	---	3440	19,	---
3441	20,	---	3441	20,	---
3442	21,	---	3442	21,	---
3443	22,	---	3443	22,	---
3444	23,	---	3444	23,	---
3445	24,	---	3445	24,	---
3446	25,	---	3446	25,	---
3447	26,	---	3447	26,	---
3448	27,	---	3448	27,	---
3449	28,	---	3449	28,	---
3450	29,	---	3450	29,	---
3451	30,	---	3451	30,	---
3452	31,	---	3452	31,	---
3453	0,	---	3453	0,	---
3454	2,	---	3454	2,	---
3455	4,	---	3455	4,	---
3456	6,	---	3456	6,	---
3457	8,	---	3457	8,	---
3458	10,	---	3458	10,	---
3459	12,	---	3459	12,	---
3460	14,	---	3460	14,	---
3461	16,	---	3461	16,	---
3462	18,	---	3462	18,	---
3463	20,	---	3463	20,	---
3464	22,	---	3464	22,	---
3465	24,	---	3465	24,	---
3466	26,	---	3466	26,	---
3467	28,	---	3467	28,	---
3468	30,	---	3468	30,	---
3469	0,	---	3469	0,	---
3470	0,	---	3470	0,	---
3471	0,	---	3471	0,	---
3472	0,	---	3472	0,	---
3473	0,	---	3473	0,	---
3474	1,	---	3474	1,	---
3475	2,	---	3475	2,	---
3476	3,	---	3476	3,	---
3477	4,	---	3477	4,	---
3478	5,	---	3478	5,	---
3479	6,	---	3479	6,	---
3480	7,	---	3480	7,	---
3481	8,	---	3481	8,	---
3482	9,	---	3482	9,	---
3483	10,	---	3483	10,	---
3484	11,	---	3484	11,	---
3485	12,	---	3485	12,	---
3486	13,	---	3486	13,	---
3487	14,	---	3487	14,	---
3488	15,	---	3488	15,	---
3489	16,	---	3489	16,	---
3490	17,	---	3490	17,	---
3491	18,	---	3491	18,	---
3492	19,	---	3492	19,	---
3493	20,	---	3493	20,	---
3494	21,	---	3494	21,	---
3495	22,	---	3495	22,	---
3496	23,	---	3496	23,	---
3497	24,	---	3497	24,	---
3498	25,	---	3498	25,	---
3499	26,	---	3499	26,	---
3500	27,	---	3500	27,	---
3501	28,	---	3501	28,	---
3502	29,	---	3502	29,	---
3503	30,	---	3503	30,	---
3504	31,	---	3504	31,	---
3505	0,	---	3505	0,	---
3506	1,	---	3506	1,	---
3507	2,	---	3507	2,	---
3508	3,	---	3508	3,	---
3509	4,	---	3509	4,	---
3510	5,	---	3510	5,	---
3511	6,	---	3511	6,	---
3512	7,	---	3512	7,	---
3513	0,	---	3513	0,	---
3514	1,	---	3514	1,	---
3515	2,	---	3515	2,	---
3516	3,	---	3516	3,	---
3517	4,	---	3517	4,	---
3518	5,	---	3518	5,	---
3519	6,	---	3519	6,	---
3520	7,	---	3520	7,	---
3521	8,	---	3521	8,	---
3522	9,	---	3522	9,	---
3523	10,	---	3523	10,	---
3524	11,	---	3524	11,	---
3525	12,	---	3525	12,	---
3526	13,	---	3526	13,	---
3527	14,	---	3527	14,	---
3528	15,	---	3528	15,	---
3529	16,	---	3529	16,	---
3530	17,	---	3530	17,	---
3531	18,	---	3531	18,	---
3532	19,	---	3532	19,	---
3533	20,	---	3533	20,	---
3534	21,	---	3534	21,	---
3535	22,	---	3535	22,	---
3536	23,	---	3536	23,	---
3537	24,	---	3537	24,	---
3538	25,	---	3538	25,	---
3539	26,	---	3539	26,	---
3540	27,	---	3540	27,	---
3541	28,	---	3541	28,	---
3542	29,	---	3542	29,	---
3543	30,	---	3543	30,	---
3544	31,	---	3544	31,	---
3545	30,	---	3545	30,	---
3546	0,	---	3546	0,	---
3547	1,	---	3547	1,	---
3548	2,	---	3548	2,	---
3549	3,	---	3549	3,	---
3550	4,	---	3550	4,	---
3551	5,	---	3551	5,	---
3552	6,	---	3552	6,	---
3553	7,	---	3553	7,	---
3554	8,	---	3554	8,	---
3555	9,	---	3555	9,	---
3556	10,	---	3556	10,	---
3557	11,	---	3557	11,	---
3558	12,	---	3558	12,	---
3559	13,	---	3559	13,	---
3560	14,	---	3560	14,	---
3561	15,	---	3561	15,	---
3562	16,	---	3562	16,	---
3563	17,	---	3563	17,	---
3564	18,	---	3564	18,	---
3565	19,	---	3565	19,	---
3566	20,	---	3566	20,	---
3567	21,	---	3567	21,	---
3568	22,	---	3568	22,	---
3569	23,	---	3569	23,	---
3570	24,	---	3570	24,	---
3571	25,	---	3571	25,	---
3572	26,	---	3572	26,	---
3573	27,	---	3573	27,	---
3574	28,	---	3574	28,	---
3575	29,	---	3575	29,	---
3576	30,	---	3576	30,	---
3577	31,	---	3577	31,	---
3578	28,	---	3578	28,	---
3579	0,	---	3579	0,	---
3580	1,	---	3580	1,	---
3581	2,	---	3581	2,	---
3582	3,	---	3582	3,	---
3583	0,	---	3583	0,	---
3584	1,	---	3584	1,	---
3585	2,	---	3585	2,	---
3586	3,	---	3586	3,	---
3587	4,	---	3587	4,	---
3588	5,	---	3588	5,	---
3589	6,	---	3589	6,	---
3590	7,	---	3590	7,	---
3591	8,	---	3591	8,	---
3592	9,	---	3592	9,	---
3593	10,	---	3593	10,	---
3594	11,	---	3594	11,	---
3595	12,	---	3595	12,	---
3596	13,	---	3596	13,	---
3597	14,	---	3597	14,	---
3598	15,	---	3598	15,	---
3599	16,	---	3599	16,	---
3600	17,	---	3600	17,	---
3601	18,	---	3601	18,	---
3602	19,	---	3602	19,	---
3603	20,	---	3603	20,	---
3604	21,	---	3604	21,	---
3605	22,	---	3605	22,	---
3606	23,	---	3606	23,	---
3607	24,	---	3607	24,	---
3608	25,	---	3608	25,	---
3609	26,	---	3609	26,	---
3610	27,	---	3610	27,	---
3611	28,	---	3611	28,	---
3612	29,	---	3612	29,	---
3613	30,	---	3613	30,	---
3614	31,	---	3614	31,	---
3615	26,	---	3615	26,	---
3616	27,	---	3616	27,	---
3617	0,	---	3617	0,	---
3618	1,	---	3618	1,	---
3619	2,	---	3619	2,	---
3620	3,	---	3620	3,	---
3621	0,	---	3621	0,	---
3622	1,	---	3622	1,	---
3623	2,	---	3623	2,	---
3624	8,	---	3624	8,	---
3625	9,	---	3625	9,	---
3626	10,	---	3626	10,	---
3627	11,	---	3627	11,	---
3628	12,	---	3628	12,	---
3629	13,	---	3629	13,	---
3630	14,	---	3630	14,	---
3631	15,	---	3631	15,	---
3632	16,	---	3632	16,	---
3633	17,	---	3633	17,	---
3634	18,	---	3634	18,	---
3635	19,	---	3635	19,	---
3636	20,	---	3636	20,	---
3637	21,	---	3637	21,	---
3638	22,	---	3638	22,	---
3639	23,	---	3639	23,	---
3640	24,	---	3640	24,	---
3641	25,	---	3641	25,	---
3642	26,	---	3642	26,	---
3643	27,	---	3643	27,	---
3644	28,	---	3644	28,	---
3645	29,	---	3645	29,	---
3646	30,	---	3646	30,	---
3647	31,	---	3647	31,	---
3648	0,	---	3648	0,	---
3649	1,	---	3649	1,	---
3650	2,	---	3650	2,	---
3651	31,	---	3651	31,	---
3652	16,	---	3652	16,	---
3653	17,	---	3653	17,	---
3654	18,	---	3654	18,	---
3655	19,	---	3655	19,	---
3656	20,	---	3656	20,	---
3657	21,	---	3657	21,	---
3658	22,	---	3658	22,	---
3659	23,	---	3659	23,	---
3660	29,	---	3660	29,	---
3661	8,	---	3661	8,	---
3662	9,	---	3662	9,	---
3663	10,	---	3663	10,	---
3664	11,	---	3664	11,	---
3665	12,	---	3665	12,	---
3666	13,	---	3666	13,	---
3667	14,	---	3667	14,	---
3668	15,	---	3668	15,	---
3669	24,	---	3669	24,	---
3670	25,	---	3670	25,	---
3671	2,	---	3671	2,	---
3672	3,	---	3672	3,	---
3673	0,	---	3673	0,	---
3674	1,	---	3674	1,	---
3675	2,	---	3675	2,	---
3676	3,	---	3676	3,	---
3677	4,	---	3677	4,	---
3678	5,	---	3678	5,	---
3679	6,	---	3679	6,	---
3680	7,	---	3680	7,	---
3681	8,	---	3681	8,	---
3682	9,	---	3682	9,	---
3683	10,	---	3683	10,	---
3684	11,	---	3684	11,	---
3685	12,	---	3685	12,	---
3686	13,	---	3686	13,	---
3687	14,	---	3687	14,	---
3688	15,	---	3688	15,	---
3689	16,	---	3689	16,	---
3690	17,	---	3690	17,	---
3691	18,	---	3691	18,	---
3692	19,	---	3692	19,	---
3693	20,	---	3693	20,	---
3694	21,	---	3694	21,	---
3695	22,	---	3695	22,	---
3696	23,	---	3696	23,	---
3697	24,	---	3697	24,	---
3698	25,	---	3698	25,	---
3699	26,	---	3699	26,	---
3700	27,	---	3700	27,	---
3701	28,	---	3701	28,	---
3702	29,	---	3702	29,	---
3703	30,	---	3703	30,	---
3704	31,	---	3704	31,	---
3705	0,	---	3705	0,	---
3706	4,	---	3706	4,	---
3707	5,	---	3707	5,	---
3708	6,	---	3708	6,	---
3709	7,	---	3709	7,	---
3710	0,	---	3710	0,	---
3711	0,	---	3711	0,	---
3712	1,	---	3712	1,	---
3713	2,	---	3713	2,	---
3714	3,	---	3714	3,	---
3715	4,	---	3715	4,	---
3716	5,	---	3716	5,	---
3717	6,	---	3717	6,	---
3718	7,	---	3718	7,	---
3719	8,	---	3719	8,	---
3720	9,	---	3720	9,	---
3721	10,	---	3721	10,	---
3722	11,	---	3722	11,	---
3723	12,	---	3723	12,	---
3724	13,	---	3724	13,	---
3725	14,	---	3725	14,	---
3726	15,	---	3726	15,	---
3727	16,	---	3727	16,	---
3728	17,	---	3728	17,	---
3729	18,	---	3729	18,	---
3730	19,	---	3730	19,	---
3731	20,	---	3731	20,	---
3732	21,	---	3732	21,	---
3733	22,	---	3733	22,	---
3734	23,	---	3734	23,	---
3735	24,	---	3735	24,	---
3736	25,	---	3736	25,	---
3737	26,	---	3737	26,	---
3738	27,	---	3738	27,	---
3739	28,	---	3739	28,	---
3740	29,	---	3740	29,	---
3741	30,	---	3741	30,	---
3742	31,	---	3742	31,	---
3743	0,	---	3743	0,	---
3744	0,	---	3744	0,	---
3745	26,	---	3745	26,	---
3746	27,	---	3746	27,	---
3747	0,	---	3747	0,	---
3748	16,	---	3748	16,	---
3749	17,	---	3749	17,	---
3750	18,	---	3750	18,	---
3751	19,	---	3751	19,	---
3752	20,	---	3752	20,	---
3753	21,	---	3753	21,	---
3754	22,	---	3754	22,	---
3755	23,	---	3755	23,	---
3756	8,	---	3756	8,	---
3757	9,	---	3757	9,	---
3758	10,	---	3758	10,	---
3759	11,	---	3759	11,	---
3760	12,	---	3760	12,	---
3761	13,	---	3761	13,	---
3762	14,	---	3762	14,	---
3763	15,	---	3763	15,	---
3764	24,	---	3764	24,	---
3765	25,	---	3765	25,	---
3766	2,	---	3766	2,	---
3767	3,	---	3767	3,	---
3768	};	---	3768	};	---
3769	static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {	1	3769	static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {	1
3770	RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,	1	3770	RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,	1
3771	MipsSubRegIdxRanges, MipsRegEncodingTable);	---	3771	MipsSubRegIdxRanges, MipsRegEncodingTable);	---
3772		---	3772		---
3773	switch (DwarfFlavour) {	1	3773	switch (DwarfFlavour) {	1
3774	default:	0	3774	default:	0
3775	llvm_unreachable("Unknown DWARF flavour");	0	3775	llvm_unreachable("Unknown DWARF flavour");	0
3776	case 0:	1	3776	case 0:	1
3777	RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	1	3777	RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	1
3778	break;	1	3778	break;	1
3779	}	---	3779	}	---
3780	switch (EHFlavour) {	1	3780	switch (EHFlavour) {	1
3781	default:	0	3781	default:	0
3782	llvm_unreachable("Unknown DWARF flavour");	0	3782	llvm_unreachable("Unknown DWARF flavour");	0
3783	case 0:	1	3783	case 0:	1
3784	RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	1	3784	RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	1
3785	break;	1	3785	break;	1
3786	}	---	3786	}	---
3787	switch (DwarfFlavour) {	1	3787	switch (DwarfFlavour) {	1
3788	default:	0	3788	default:	0
3789	llvm_unreachable("Unknown DWARF flavour");	0	3789	llvm_unreachable("Unknown DWARF flavour");	0
3790	case 0:	1	3790	case 0:	1
3791	RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	1	3791	RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	1
3792	break;	1	3792	break;	1
3793	}	---	3793	}	---
3794	switch (EHFlavour) {	1	3794	switch (EHFlavour) {	1
3795	default:	0	3795	default:	0
3796	llvm_unreachable("Unknown DWARF flavour");	0	3796	llvm_unreachable("Unknown DWARF flavour");	0
3797	case 0:	1	3797	case 0:	1
3798	RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	1	3798	RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	1
3799	break;	1	3799	break;	1
3800	}	---	3800	}	---
3801	}	1	3801	}	1
3802		---	3802		---
3803	} // end namespace llvm	---	3803	} // end namespace llvm	---
3804		---	3804		---
3805	#endif // GET_REGINFO_MC_DESC	---	3805	#endif // GET_REGINFO_MC_DESC	---
3806		---	3806		---
3807	/===- TableGen'erated file -------------------------------------- C++ --===\	---	3807	/===- TableGen'erated file -------------------------------------- C++ --===\	---
3808	\|* *\|	---	3808	\|* *\|	---
3809	\|* Register Information Header Fragment *\|	---	3809	\|* Register Information Header Fragment *\|	---
3810	\|* *\|	---	3810	\|* *\|	---
3811	\|* Automatically generated file, do not edit! *\|	---	3811	\|* Automatically generated file, do not edit! *\|	---
3812	\|* *\|	---	3812	\|* *\|	---
3813	\===----------------------------------------------------------------------===/	---	3813	\===----------------------------------------------------------------------===/	---
3814		---	3814		---
3815		---	3815		---
3816	#ifdef GET_REGINFO_HEADER	---	3816	#ifdef GET_REGINFO_HEADER	---
3817	#undef GET_REGINFO_HEADER	---	3817	#undef GET_REGINFO_HEADER	---
3818		---	3818		---
3819	#include "llvm/CodeGen/TargetRegisterInfo.h"	---	3819	#include "llvm/CodeGen/TargetRegisterInfo.h"	---
3820		---	3820		---
3821	namespace llvm {	---	3821	namespace llvm {	---
3822		---	3822		---
3823	class MipsFrameLowering;	---	3823	class MipsFrameLowering;	---
3824		---	3824		---
3825	struct MipsGenRegisterInfo : public TargetRegisterInfo {	---	3825	struct MipsGenRegisterInfo : public TargetRegisterInfo {	---
3826	explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,	---	3826	explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,	---
3827	unsigned PC = 0, unsigned HwMode = 0);	---	3827	unsigned PC = 0, unsigned HwMode = 0);	---
3828	unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;	---	3828	unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;	---
3829	LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	---	3829	LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	---
3830	LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	---	3830	LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;	---
3831	const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;	---	3831	const TargetRegisterClass getSubClassWithSubReg(const TargetRegisterClass , unsigned) const override;	---
3832	const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;	---	3832	const TargetRegisterClass getSubRegisterClass(const TargetRegisterClass , unsigned) const override;	---
3833	const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;	---	3833	const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;	---
3834	unsigned getRegUnitWeight(unsigned RegUnit) const override;	---	3834	unsigned getRegUnitWeight(unsigned RegUnit) const override;	---
3835	unsigned getNumRegPressureSets() const override;	---	3835	unsigned getNumRegPressureSets() const override;	---
3836	const char *getRegPressureSetName(unsigned Idx) const override;	---	3836	const char *getRegPressureSetName(unsigned Idx) const override;	---
3837	unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;	---	3837	unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;	---
3838	const int getRegClassPressureSets(const TargetRegisterClass RC) const override;	---	3838	const int getRegClassPressureSets(const TargetRegisterClass RC) const override;	---
3839	const int *getRegUnitPressureSets(unsigned RegUnit) const override;	---	3839	const int *getRegUnitPressureSets(unsigned RegUnit) const override;	---
3840	ArrayRef getRegMaskNames() const override;	---	3840	ArrayRef getRegMaskNames() const override;	---
3841	ArrayRef getRegMasks() const override;	---	3841	ArrayRef getRegMasks() const override;	---
3842	bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;	---	3842	bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;	---
3843	bool isFixedRegister(const MachineFunction &, MCRegister) const override;	---	3843	bool isFixedRegister(const MachineFunction &, MCRegister) const override;	---
3844	bool isArgumentRegister(const MachineFunction &, MCRegister) const override;	---	3844	bool isArgumentRegister(const MachineFunction &, MCRegister) const override;	---
3845	bool isConstantPhysReg(MCRegister PhysReg) const override final;	---	3845	bool isConstantPhysReg(MCRegister PhysReg) const override final;	---
3846	/// Devirtualized TargetFrameLowering.	---	3846	/// Devirtualized TargetFrameLowering.	---
3847	static const MipsFrameLowering *getFrameLowering(	---	3847	static const MipsFrameLowering *getFrameLowering(	---
3848	const MachineFunction &MF);	---	3848	const MachineFunction &MF);	---
3849	};	---	3849	};	---
3850		---	3850		---
3851	namespace Mips { // Register classes	---	3851	namespace Mips { // Register classes	---
3852	extern const TargetRegisterClass MSA128F16RegClass;	---	3852	extern const TargetRegisterClass MSA128F16RegClass;	---
3853	extern const TargetRegisterClass CCRRegClass;	---	3853	extern const TargetRegisterClass CCRRegClass;	---
3854	extern const TargetRegisterClass COP0RegClass;	---	3854	extern const TargetRegisterClass COP0RegClass;	---
3855	extern const TargetRegisterClass COP2RegClass;	---	3855	extern const TargetRegisterClass COP2RegClass;	---
3856	extern const TargetRegisterClass COP3RegClass;	---	3856	extern const TargetRegisterClass COP3RegClass;	---
3857	extern const TargetRegisterClass DSPRRegClass;	---	3857	extern const TargetRegisterClass DSPRRegClass;	---
3858	extern const TargetRegisterClass FGR32RegClass;	---	3858	extern const TargetRegisterClass FGR32RegClass;	---
3859	extern const TargetRegisterClass FGRCCRegClass;	---	3859	extern const TargetRegisterClass FGRCCRegClass;	---
3860	extern const TargetRegisterClass GPR32RegClass;	---	3860	extern const TargetRegisterClass GPR32RegClass;	---
3861	extern const TargetRegisterClass HWRegsRegClass;	---	3861	extern const TargetRegisterClass HWRegsRegClass;	---
3862	extern const TargetRegisterClass MSACtrlRegClass;	---	3862	extern const TargetRegisterClass MSACtrlRegClass;	---
3863	extern const TargetRegisterClass GPR32NONZERORegClass;	---	3863	extern const TargetRegisterClass GPR32NONZERORegClass;	---
3864	extern const TargetRegisterClass CPU16RegsPlusSPRegClass;	---	3864	extern const TargetRegisterClass CPU16RegsPlusSPRegClass;	---
3865	extern const TargetRegisterClass CPU16RegsRegClass;	---	3865	extern const TargetRegisterClass CPU16RegsRegClass;	---
3866	extern const TargetRegisterClass FCCRegClass;	---	3866	extern const TargetRegisterClass FCCRegClass;	---
3867	extern const TargetRegisterClass GPRMM16RegClass;	---	3867	extern const TargetRegisterClass GPRMM16RegClass;	---
3868	extern const TargetRegisterClass GPRMM16MovePRegClass;	---	3868	extern const TargetRegisterClass GPRMM16MovePRegClass;	---
3869	extern const TargetRegisterClass GPRMM16ZeroRegClass;	---	3869	extern const TargetRegisterClass GPRMM16ZeroRegClass;	---
3870	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;	---	3870	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;	---
3871	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;	---	3871	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;	---
3872	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;	---	3872	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;	---
3873	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;	---	3873	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;	---
3874	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;	---	3874	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;	---
3875	extern const TargetRegisterClass HI32DSPRegClass;	---	3875	extern const TargetRegisterClass HI32DSPRegClass;	---
3876	extern const TargetRegisterClass LO32DSPRegClass;	---	3876	extern const TargetRegisterClass LO32DSPRegClass;	---
3877	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	---	3877	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	---
3878	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;	---	3878	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;	---
3879	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	---	3879	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	---
3880	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	---	3880	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	---
3881	extern const TargetRegisterClass CPURARegRegClass;	---	3881	extern const TargetRegisterClass CPURARegRegClass;	---
3882	extern const TargetRegisterClass CPUSPRegRegClass;	---	3882	extern const TargetRegisterClass CPUSPRegRegClass;	---
3883	extern const TargetRegisterClass DSPCCRegClass;	---	3883	extern const TargetRegisterClass DSPCCRegClass;	---
3884	extern const TargetRegisterClass GP32RegClass;	---	3884	extern const TargetRegisterClass GP32RegClass;	---
3885	extern const TargetRegisterClass GPR32ZERORegClass;	---	3885	extern const TargetRegisterClass GPR32ZERORegClass;	---
3886	extern const TargetRegisterClass HI32RegClass;	---	3886	extern const TargetRegisterClass HI32RegClass;	---
3887	extern const TargetRegisterClass LO32RegClass;	---	3887	extern const TargetRegisterClass LO32RegClass;	---
3888	extern const TargetRegisterClass SP32RegClass;	---	3888	extern const TargetRegisterClass SP32RegClass;	---
3889	extern const TargetRegisterClass FGR64RegClass;	---	3889	extern const TargetRegisterClass FGR64RegClass;	---
3890	extern const TargetRegisterClass GPR64RegClass;	---	3890	extern const TargetRegisterClass GPR64RegClass;	---
3891	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;	---	3891	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;	---
3892	extern const TargetRegisterClass AFGR64RegClass;	---	3892	extern const TargetRegisterClass AFGR64RegClass;	---
3893	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;	---	3893	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;	---
3894	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;	---	3894	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;	---
3895	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;	---	3895	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;	---
3896	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;	---	3896	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;	---
3897	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;	---	3897	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;	---
3898	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;	---	3898	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;	---
3899	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;	---	3899	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;	---
3900	extern const TargetRegisterClass ACC64DSPRegClass;	---	3900	extern const TargetRegisterClass ACC64DSPRegClass;	---
3901	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;	---	3901	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;	---
3902	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;	---	3902	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;	---
3903	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	---	3903	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;	---
3904	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;	---	3904	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;	---
3905	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	---	3905	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;	---
3906	extern const TargetRegisterClass OCTEON_MPLRegClass;	---	3906	extern const TargetRegisterClass OCTEON_MPLRegClass;	---
3907	extern const TargetRegisterClass OCTEON_PRegClass;	---	3907	extern const TargetRegisterClass OCTEON_PRegClass;	---
3908	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	---	3908	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;	---
3909	extern const TargetRegisterClass ACC64RegClass;	---	3909	extern const TargetRegisterClass ACC64RegClass;	---
3910	extern const TargetRegisterClass GP64RegClass;	---	3910	extern const TargetRegisterClass GP64RegClass;	---
3911	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;	---	3911	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;	---
3912	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;	---	3912	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;	---
3913	extern const TargetRegisterClass HI64RegClass;	---	3913	extern const TargetRegisterClass HI64RegClass;	---
3914	extern const TargetRegisterClass LO64RegClass;	---	3914	extern const TargetRegisterClass LO64RegClass;	---
3915	extern const TargetRegisterClass SP64RegClass;	---	3915	extern const TargetRegisterClass SP64RegClass;	---
3916	extern const TargetRegisterClass MSA128BRegClass;	---	3916	extern const TargetRegisterClass MSA128BRegClass;	---
3917	extern const TargetRegisterClass MSA128DRegClass;	---	3917	extern const TargetRegisterClass MSA128DRegClass;	---
3918	extern const TargetRegisterClass MSA128HRegClass;	---	3918	extern const TargetRegisterClass MSA128HRegClass;	---
3919	extern const TargetRegisterClass MSA128WRegClass;	---	3919	extern const TargetRegisterClass MSA128WRegClass;	---
3920	extern const TargetRegisterClass MSA128WEvensRegClass;	---	3920	extern const TargetRegisterClass MSA128WEvensRegClass;	---
3921	extern const TargetRegisterClass ACC128RegClass;	---	3921	extern const TargetRegisterClass ACC128RegClass;	---
3922	} // end namespace Mips	---	3922	} // end namespace Mips	---
3923		---	3923		---
3924	} // end namespace llvm	---	3924	} // end namespace llvm	---
3925		---	3925		---
3926	#endif // GET_REGINFO_HEADER	---	3926	#endif // GET_REGINFO_HEADER	---
3927		---	3927		---
3928	/===- TableGen'erated file -------------------------------------- C++ --===\	---	3928	/===- TableGen'erated file -------------------------------------- C++ --===\	---
3929	\|* *\|	---	3929	\|* *\|	---
3930	\|* Target Register and Register Classes Information *\|	---	3930	\|* Target Register and Register Classes Information *\|	---
3931	\|* *\|	---	3931	\|* *\|	---
3932	\|* Automatically generated file, do not edit! *\|	---	3932	\|* Automatically generated file, do not edit! *\|	---
3933	\|* *\|	---	3933	\|* *\|	---
3934	\===----------------------------------------------------------------------===/	---	3934	\===----------------------------------------------------------------------===/	---
3935		---	3935		---
3936		---	3936		---
3937	#ifdef GET_REGINFO_TARGET_DESC	---	3937	#ifdef GET_REGINFO_TARGET_DESC	---
3938	#undef GET_REGINFO_TARGET_DESC	---	3938	#undef GET_REGINFO_TARGET_DESC	---
3939		---	3939		---
3940	namespace llvm {	---	3940	namespace llvm {	---
3941		---	3941		---
3942	extern const MCRegisterClass MipsMCRegisterClasses[];	---	3942	extern const MCRegisterClass MipsMCRegisterClasses[];	---
3943		---	3943		---
3944	static const MVT::SimpleValueType VTLists[] = {	---	3944	static const MVT::SimpleValueType VTLists[] = {	---
3945	/* 0 */ MVT::i32, MVT::Other,	---	3945	/* 0 */ MVT::i32, MVT::Other,	---
3946	/* 2 */ MVT::i64, MVT::Other,	---	3946	/* 2 */ MVT::i64, MVT::Other,	---
3947	/* 4 */ MVT::f16, MVT::Other,	---	3947	/* 4 */ MVT::f16, MVT::Other,	---
3948	/* 6 */ MVT::f32, MVT::Other,	---	3948	/* 6 */ MVT::f32, MVT::Other,	---
3949	/* 8 */ MVT::f64, MVT::Other,	---	3949	/* 8 */ MVT::f64, MVT::Other,	---
3950	/* 10 */ MVT::v16i8, MVT::Other,	---	3950	/* 10 */ MVT::v16i8, MVT::Other,	---
3951	/* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,	---	3951	/* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,	---
3952	/* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,	---	3952	/* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,	---
3953	/* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,	---	3953	/* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,	---
3954	/* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,	---	3954	/* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,	---
3955	/* 24 */ MVT::Untyped, MVT::Other,	---	3955	/* 24 */ MVT::Untyped, MVT::Other,	---
3956	};	---	3956	};	---
3957		---	3957		---
3958	static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };	---	3958	static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };	---
3959		---	3959		---
3960		---	3960		---
3961	static const LaneBitmask SubRegIndexLaneMaskTable[] = {	---	3961	static const LaneBitmask SubRegIndexLaneMaskTable[] = {	---
3962	LaneBitmask::getAll(),	---	3962	LaneBitmask::getAll(),	---
3963	LaneBitmask(0x0000000000000001), // sub_32	---	3963	LaneBitmask(0x0000000000000001), // sub_32	---
3964	LaneBitmask(0x0000000000000041), // sub_64	---	3964	LaneBitmask(0x0000000000000041), // sub_64	---
3965	LaneBitmask(0x0000000000000002), // sub_dsp16_19	---	3965	LaneBitmask(0x0000000000000002), // sub_dsp16_19	---
3966	LaneBitmask(0x0000000000000004), // sub_dsp20	---	3966	LaneBitmask(0x0000000000000004), // sub_dsp20	---
3967	LaneBitmask(0x0000000000000008), // sub_dsp21	---	3967	LaneBitmask(0x0000000000000008), // sub_dsp21	---
3968	LaneBitmask(0x0000000000000010), // sub_dsp22	---	3968	LaneBitmask(0x0000000000000010), // sub_dsp22	---
3969	LaneBitmask(0x0000000000000020), // sub_dsp23	---	3969	LaneBitmask(0x0000000000000020), // sub_dsp23	---
3970	LaneBitmask(0x0000000000000040), // sub_hi	---	3970	LaneBitmask(0x0000000000000040), // sub_hi	---
3971	LaneBitmask(0x0000000000000001), // sub_lo	---	3971	LaneBitmask(0x0000000000000001), // sub_lo	---
3972	LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32	---	3972	LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32	---
3973	LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32	---	3973	LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32	---
3974	};	---	3974	};	---
3975		---	3975		---
3976		---	3976		---
3977		---	3977		---
3978	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {	---	3978	static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {	---
3979	// Mode = 0 (Default)	---	3979	// Mode = 0 (Default)	---
3980	{ 16, 16, 128, VTLists+4 }, // MSA128F16	---	3980	{ 16, 16, 128, VTLists+4 }, // MSA128F16	---
3981	{ 32, 32, 32, VTLists+0 }, // CCR	---	3981	{ 32, 32, 32, VTLists+0 }, // CCR	---
3982	{ 32, 32, 32, VTLists+0 }, // COP0	---	3982	{ 32, 32, 32, VTLists+0 }, // COP0	---
3983	{ 32, 32, 32, VTLists+0 }, // COP2	---	3983	{ 32, 32, 32, VTLists+0 }, // COP2	---
3984	{ 32, 32, 32, VTLists+0 }, // COP3	---	3984	{ 32, 32, 32, VTLists+0 }, // COP3	---
3985	{ 32, 32, 32, VTLists+12 }, // DSPR	---	3985	{ 32, 32, 32, VTLists+12 }, // DSPR	---
3986	{ 32, 32, 32, VTLists+6 }, // FGR32	---	3986	{ 32, 32, 32, VTLists+6 }, // FGR32	---
3987	{ 32, 32, 32, VTLists+0 }, // FGRCC	---	3987	{ 32, 32, 32, VTLists+0 }, // FGRCC	---
3988	{ 32, 32, 32, VTLists+0 }, // GPR32	---	3988	{ 32, 32, 32, VTLists+0 }, // GPR32	---
3989	{ 32, 32, 32, VTLists+0 }, // HWRegs	---	3989	{ 32, 32, 32, VTLists+0 }, // HWRegs	---
3990	{ 32, 32, 32, VTLists+0 }, // MSACtrl	---	3990	{ 32, 32, 32, VTLists+0 }, // MSACtrl	---
3991	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO	---	3991	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO	---
3992	{ 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP	---	3992	{ 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP	---
3993	{ 32, 32, 32, VTLists+0 }, // CPU16Regs	---	3993	{ 32, 32, 32, VTLists+0 }, // CPU16Regs	---
3994	{ 32, 32, 32, VTLists+0 }, // FCC	---	3994	{ 32, 32, 32, VTLists+0 }, // FCC	---
3995	{ 32, 32, 32, VTLists+0 }, // GPRMM16	---	3995	{ 32, 32, 32, VTLists+0 }, // GPRMM16	---
3996	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP	---	3996	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP	---
3997	{ 32, 32, 32, VTLists+0 }, // GPRMM16Zero	---	3997	{ 32, 32, 32, VTLists+0 }, // GPRMM16Zero	---
3998	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero	---	3998	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero	---
3999	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP	---	3999	{ 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP	---
4000	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond	---	4000	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond	---
4001	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP	---	4001	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP	---
4002	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero	---	4002	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero	---
4003	{ 32, 32, 32, VTLists+0 }, // HI32DSP	---	4003	{ 32, 32, 32, VTLists+0 }, // HI32DSP	---
4004	{ 32, 32, 32, VTLists+0 }, // LO32DSP	---	4004	{ 32, 32, 32, VTLists+0 }, // LO32DSP	---
4005	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond	---	4005	{ 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond	---
4006	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst	---	4006	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst	---
4007	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	4007	{ 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
4008	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	4008	{ 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
4009	{ 32, 32, 32, VTLists+0 }, // CPURAReg	---	4009	{ 32, 32, 32, VTLists+0 }, // CPURAReg	---
4010	{ 32, 32, 32, VTLists+0 }, // CPUSPReg	---	4010	{ 32, 32, 32, VTLists+0 }, // CPUSPReg	---
4011	{ 32, 32, 32, VTLists+12 }, // DSPCC	---	4011	{ 32, 32, 32, VTLists+12 }, // DSPCC	---
4012	{ 32, 32, 32, VTLists+0 }, // GP32	---	4012	{ 32, 32, 32, VTLists+0 }, // GP32	---
4013	{ 32, 32, 32, VTLists+0 }, // GPR32ZERO	---	4013	{ 32, 32, 32, VTLists+0 }, // GPR32ZERO	---
4014	{ 32, 32, 32, VTLists+0 }, // HI32	---	4014	{ 32, 32, 32, VTLists+0 }, // HI32	---
4015	{ 32, 32, 32, VTLists+0 }, // LO32	---	4015	{ 32, 32, 32, VTLists+0 }, // LO32	---
4016	{ 32, 32, 32, VTLists+0 }, // SP32	---	4016	{ 32, 32, 32, VTLists+0 }, // SP32	---
4017	{ 64, 64, 64, VTLists+8 }, // FGR64	---	4017	{ 64, 64, 64, VTLists+8 }, // FGR64	---
4018	{ 64, 64, 64, VTLists+2 }, // GPR64	---	4018	{ 64, 64, 64, VTLists+2 }, // GPR64	---
4019	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO	---	4019	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO	---
4020	{ 64, 64, 64, VTLists+8 }, // AFGR64	---	4020	{ 64, 64, 64, VTLists+8 }, // AFGR64	---
4021	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP	---	4021	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP	---
4022	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs	---	4022	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs	---
4023	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP	---	4023	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP	---
4024	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero	---	4024	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero	---
4025	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---	4025	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---
4026	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---	4026	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---
4027	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---	4027	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---
4028	{ 64, 64, 64, VTLists+24 }, // ACC64DSP	---	4028	{ 64, 64, 64, VTLists+24 }, // ACC64DSP	---
4029	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---	4029	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---
4030	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---	4030	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---
4031	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---	4031	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---
4032	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---	4032	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---
4033	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	4033	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
4034	{ 64, 64, 64, VTLists+2 }, // OCTEON_MPL	---	4034	{ 64, 64, 64, VTLists+2 }, // OCTEON_MPL	---
4035	{ 64, 64, 64, VTLists+2 }, // OCTEON_P	---	4035	{ 64, 64, 64, VTLists+2 }, // OCTEON_P	---
4036	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	4036	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
4037	{ 64, 64, 64, VTLists+24 }, // ACC64	---	4037	{ 64, 64, 64, VTLists+24 }, // ACC64	---
4038	{ 64, 64, 64, VTLists+2 }, // GP64	---	4038	{ 64, 64, 64, VTLists+2 }, // GP64	---
4039	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg	---	4039	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg	---
4040	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO	---	4040	{ 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO	---
4041	{ 64, 64, 64, VTLists+2 }, // HI64	---	4041	{ 64, 64, 64, VTLists+2 }, // HI64	---
4042	{ 64, 64, 64, VTLists+2 }, // LO64	---	4042	{ 64, 64, 64, VTLists+2 }, // LO64	---
4043	{ 64, 64, 64, VTLists+2 }, // SP64	---	4043	{ 64, 64, 64, VTLists+2 }, // SP64	---
4044	{ 128, 128, 128, VTLists+10 }, // MSA128B	---	4044	{ 128, 128, 128, VTLists+10 }, // MSA128B	---
4045	{ 128, 128, 128, VTLists+21 }, // MSA128D	---	4045	{ 128, 128, 128, VTLists+21 }, // MSA128D	---
4046	{ 128, 128, 128, VTLists+15 }, // MSA128H	---	4046	{ 128, 128, 128, VTLists+15 }, // MSA128H	---
4047	{ 128, 128, 128, VTLists+18 }, // MSA128W	---	4047	{ 128, 128, 128, VTLists+18 }, // MSA128W	---
4048	{ 128, 128, 128, VTLists+18 }, // MSA128WEvens	---	4048	{ 128, 128, 128, VTLists+18 }, // MSA128WEvens	---
4049	{ 128, 128, 128, VTLists+24 }, // ACC128	---	4049	{ 128, 128, 128, VTLists+24 }, // ACC128	---
4050	};	---	4050	};	---
4051		---	4051		---
4052	static const TargetRegisterClass *const NullRegClasses[] = { nullptr };	---	4052	static const TargetRegisterClass *const NullRegClasses[] = { nullptr };	---
4053		---	4053		---
4054	static const uint32_t MSA128F16SubClassMask[] = {	---	4054	static const uint32_t MSA128F16SubClassMask[] = {	---
4055	0x00000001, 0x00000000, 0x0000001f,	---	4055	0x00000001, 0x00000000, 0x0000001f,	---
4056	};	---	4056	};	---
4057		---	4057		---
4058	static const uint32_t CCRSubClassMask[] = {	---	4058	static const uint32_t CCRSubClassMask[] = {	---
4059	0x00000002, 0x00000000, 0x00000000,	---	4059	0x00000002, 0x00000000, 0x00000000,	---
4060	};	---	4060	};	---
4061		---	4061		---
4062	static const uint32_t COP0SubClassMask[] = {	---	4062	static const uint32_t COP0SubClassMask[] = {	---
4063	0x00000004, 0x00000000, 0x00000000,	---	4063	0x00000004, 0x00000000, 0x00000000,	---
4064	};	---	4064	};	---
4065		---	4065		---
4066	static const uint32_t COP2SubClassMask[] = {	---	4066	static const uint32_t COP2SubClassMask[] = {	---
4067	0x00000008, 0x00000000, 0x00000000,	---	4067	0x00000008, 0x00000000, 0x00000000,	---
4068	};	---	4068	};	---
4069		---	4069		---
4070	static const uint32_t COP3SubClassMask[] = {	---	4070	static const uint32_t COP3SubClassMask[] = {	---
4071	0x00000010, 0x00000000, 0x00000000,	---	4071	0x00000010, 0x00000000, 0x00000000,	---
4072	};	---	4072	};	---
4073		---	4073		---
4074	static const uint32_t DSPRSubClassMask[] = {	---	4074	static const uint32_t DSPRSubClassMask[] = {	---
4075	0x7e7fb920, 0x00000013, 0x00000000,	---	4075	0x7e7fb920, 0x00000013, 0x00000000,	---
4076	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	---	4076	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	---
4077	};	---	4077	};	---
4078		---	4078		---
4079	static const uint32_t FGR32SubClassMask[] = {	---	4079	static const uint32_t FGR32SubClassMask[] = {	---
4080	0x000000c0, 0x00000000, 0x00000000,	---	4080	0x000000c0, 0x00000000, 0x00000000,	---
4081	0x00000000, 0x00000100, 0x00000000, // sub_hi	---	4081	0x00000000, 0x00000100, 0x00000000, // sub_hi	---
4082	0x00000001, 0x00000120, 0x0000001f, // sub_lo	---	4082	0x00000001, 0x00000120, 0x0000001f, // sub_lo	---
4083	};	---	4083	};	---
4084		---	4084		---
4085	static const uint32_t FGRCCSubClassMask[] = {	---	4085	static const uint32_t FGRCCSubClassMask[] = {	---
4086	0x000000c0, 0x00000000, 0x00000000,	---	4086	0x000000c0, 0x00000000, 0x00000000,	---
4087	0x00000000, 0x00000100, 0x00000000, // sub_hi	---	4087	0x00000000, 0x00000100, 0x00000000, // sub_hi	---
4088	0x00000001, 0x00000120, 0x0000001f, // sub_lo	---	4088	0x00000001, 0x00000120, 0x0000001f, // sub_lo	---
4089	};	---	4089	};	---
4090		---	4090		---
4091	static const uint32_t GPR32SubClassMask[] = {	---	4091	static const uint32_t GPR32SubClassMask[] = {	---
4092	0x7e7fb900, 0x00000013, 0x00000000,	---	4092	0x7e7fb900, 0x00000013, 0x00000000,	---
4093	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	---	4093	0x00000000, 0x9d3efec0, 0x00000000, // sub_32	---
4094	};	---	4094	};	---
4095		---	4095		---
4096	static const uint32_t HWRegsSubClassMask[] = {	---	4096	static const uint32_t HWRegsSubClassMask[] = {	---
4097	0x00000200, 0x00000000, 0x00000000,	---	4097	0x00000200, 0x00000000, 0x00000000,	---
4098	};	---	4098	};	---
4099		---	4099		---
4100	static const uint32_t MSACtrlSubClassMask[] = {	---	4100	static const uint32_t MSACtrlSubClassMask[] = {	---
4101	0x00000400, 0x00000000, 0x00000000,	---	4101	0x00000400, 0x00000000, 0x00000000,	---
4102	};	---	4102	};	---
4103		---	4103		---
4104	static const uint32_t GPR32NONZEROSubClassMask[] = {	---	4104	static const uint32_t GPR32NONZEROSubClassMask[] = {	---
4105	0x7e3cb800, 0x00000011, 0x00000000,	---	4105	0x7e3cb800, 0x00000011, 0x00000000,	---
4106	0x00000000, 0x8d3ae680, 0x00000000, // sub_32	---	4106	0x00000000, 0x8d3ae680, 0x00000000, // sub_32	---
4107	};	---	4107	};	---
4108		---	4108		---
4109	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {	---	4109	static const uint32_t CPU16RegsPlusSPSubClassMask[] = {	---
4110	0x5e24b000, 0x00000010, 0x00000000,	---	4110	0x5e24b000, 0x00000010, 0x00000000,	---
4111	0x00000000, 0x813a2600, 0x00000000, // sub_32	---	4111	0x00000000, 0x813a2600, 0x00000000, // sub_32	---
4112	};	---	4112	};	---
4113		---	4113		---
4114	static const uint32_t CPU16RegsSubClassMask[] = {	---	4114	static const uint32_t CPU16RegsSubClassMask[] = {	---
4115	0x1e24a000, 0x00000000, 0x00000000,	---	4115	0x1e24a000, 0x00000000, 0x00000000,	---
4116	0x00000000, 0x013a2400, 0x00000000, // sub_32	---	4116	0x00000000, 0x013a2400, 0x00000000, // sub_32	---
4117	};	---	4117	};	---
4118		---	4118		---
4119	static const uint32_t FCCSubClassMask[] = {	---	4119	static const uint32_t FCCSubClassMask[] = {	---
4120	0x00004000, 0x00000000, 0x00000000,	---	4120	0x00004000, 0x00000000, 0x00000000,	---
4121	};	---	4121	};	---
4122		---	4122		---
4123	static const uint32_t GPRMM16SubClassMask[] = {	---	4123	static const uint32_t GPRMM16SubClassMask[] = {	---
4124	0x1e248000, 0x00000000, 0x00000000,	---	4124	0x1e248000, 0x00000000, 0x00000000,	---
4125	0x00000000, 0x013a2400, 0x00000000, // sub_32	---	4125	0x00000000, 0x013a2400, 0x00000000, // sub_32	---
4126	};	---	4126	};	---
4127		---	4127		---
4128	static const uint32_t GPRMM16MovePSubClassMask[] = {	---	4128	static const uint32_t GPRMM16MovePSubClassMask[] = {	---
4129	0x08690000, 0x00000002, 0x00000000,	---	4129	0x08690000, 0x00000002, 0x00000000,	---
4130	0x00000000, 0x10264800, 0x00000000, // sub_32	---	4130	0x00000000, 0x10264800, 0x00000000, // sub_32	---
4131	};	---	4131	};	---
4132		---	4132		---
4133	static const uint32_t GPRMM16ZeroSubClassMask[] = {	---	4133	static const uint32_t GPRMM16ZeroSubClassMask[] = {	---
4134	0x1e460000, 0x00000002, 0x00000000,	---	4134	0x1e460000, 0x00000002, 0x00000000,	---
4135	0x00000000, 0x113c3000, 0x00000000, // sub_32	---	4135	0x00000000, 0x113c3000, 0x00000000, // sub_32	---
4136	};	---	4136	};	---
4137		---	4137		---
4138	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---	4138	static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---
4139	0x1e040000, 0x00000000, 0x00000000,	---	4139	0x1e040000, 0x00000000, 0x00000000,	---
4140	0x00000000, 0x01382000, 0x00000000, // sub_32	---	4140	0x00000000, 0x01382000, 0x00000000, // sub_32	---
4141	};	---	4141	};	---
4142		---	4142		---
4143	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	---	4143	static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	---
4144	0x08280000, 0x00000000, 0x00000000,	---	4144	0x08280000, 0x00000000, 0x00000000,	---
4145	0x00000000, 0x00224000, 0x00000000, // sub_32	---	4145	0x00000000, 0x00224000, 0x00000000, // sub_32	---
4146	};	---	4146	};	---
4147		---	4147		---
4148	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {	---	4148	static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {	---
4149	0x12100000, 0x00000000, 0x00000000,	---	4149	0x12100000, 0x00000000, 0x00000000,	---
4150	0x00000000, 0x01088000, 0x00000000, // sub_32	---	4150	0x00000000, 0x01088000, 0x00000000, // sub_32	---
4151	};	---	4151	};	---
4152		---	4152		---
4153	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	---	4153	static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	---
4154	0x08200000, 0x00000000, 0x00000000,	---	4154	0x08200000, 0x00000000, 0x00000000,	---
4155	0x00000000, 0x00220000, 0x00000000, // sub_32	---	4155	0x00000000, 0x00220000, 0x00000000, // sub_32	---
4156	};	---	4156	};	---
4157		---	4157		---
4158	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	---	4158	static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	---
4159	0x08400000, 0x00000002, 0x00000000,	---	4159	0x08400000, 0x00000002, 0x00000000,	---
4160	0x00000000, 0x10240000, 0x00000000, // sub_32	---	4160	0x00000000, 0x10240000, 0x00000000, // sub_32	---
4161	};	---	4161	};	---
4162		---	4162		---
4163	static const uint32_t HI32DSPSubClassMask[] = {	---	4163	static const uint32_t HI32DSPSubClassMask[] = {	---
4164	0x00800000, 0x00000004, 0x00000000,	---	4164	0x00800000, 0x00000004, 0x00000000,	---
4165	0x00000000, 0x20000000, 0x00000000, // sub_32	---	4165	0x00000000, 0x20000000, 0x00000000, // sub_32	---
4166	0x00000000, 0x02010000, 0x00000000, // sub_hi	---	4166	0x00000000, 0x02010000, 0x00000000, // sub_hi	---
4167	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	---	4167	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	---
4168	};	---	4168	};	---
4169		---	4169		---
4170	static const uint32_t LO32DSPSubClassMask[] = {	---	4170	static const uint32_t LO32DSPSubClassMask[] = {	---
4171	0x01000000, 0x00000008, 0x00000000,	---	4171	0x01000000, 0x00000008, 0x00000000,	---
4172	0x00000000, 0x40000000, 0x00000020, // sub_32	---	4172	0x00000000, 0x40000000, 0x00000020, // sub_32	---
4173	0x00000000, 0x02010000, 0x00000000, // sub_lo	---	4173	0x00000000, 0x02010000, 0x00000000, // sub_lo	---
4174	};	---	4174	};	---
4175		---	4175		---
4176	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	---	4176	static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	---
4177	0x12000000, 0x00000000, 0x00000000,	---	4177	0x12000000, 0x00000000, 0x00000000,	---
4178	0x00000000, 0x01080000, 0x00000000, // sub_32	---	4178	0x00000000, 0x01080000, 0x00000000, // sub_32	---
4179	};	---	4179	};	---
4180		---	4180		---
4181	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {	---	4181	static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {	---
4182	0x14000000, 0x00000000, 0x00000000,	---	4182	0x14000000, 0x00000000, 0x00000000,	---
4183	0x00000000, 0x01100000, 0x00000000, // sub_32	---	4183	0x00000000, 0x01100000, 0x00000000, // sub_32	---
4184	};	---	4184	};	---
4185		---	4185		---
4186	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---	4186	static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---
4187	0x08000000, 0x00000000, 0x00000000,	---	4187	0x08000000, 0x00000000, 0x00000000,	---
4188	0x00000000, 0x00200000, 0x00000000, // sub_32	---	4188	0x00000000, 0x00200000, 0x00000000, // sub_32	---
4189	};	---	4189	};	---
4190		---	4190		---
4191	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	---	4191	static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	---
4192	0x10000000, 0x00000000, 0x00000000,	---	4192	0x10000000, 0x00000000, 0x00000000,	---
4193	0x00000000, 0x01000000, 0x00000000, // sub_32	---	4193	0x00000000, 0x01000000, 0x00000000, // sub_32	---
4194	};	---	4194	};	---
4195		---	4195		---
4196	static const uint32_t CPURARegSubClassMask[] = {	---	4196	static const uint32_t CPURARegSubClassMask[] = {	---
4197	0x20000000, 0x00000000, 0x00000000,	---	4197	0x20000000, 0x00000000, 0x00000000,	---
4198	0x00000000, 0x08000000, 0x00000000, // sub_32	---	4198	0x00000000, 0x08000000, 0x00000000, // sub_32	---
4199	};	---	4199	};	---
4200		---	4200		---
4201	static const uint32_t CPUSPRegSubClassMask[] = {	---	4201	static const uint32_t CPUSPRegSubClassMask[] = {	---
4202	0x40000000, 0x00000010, 0x00000000,	---	4202	0x40000000, 0x00000010, 0x00000000,	---
4203	0x00000000, 0x80000000, 0x00000000, // sub_32	---	4203	0x00000000, 0x80000000, 0x00000000, // sub_32	---
4204	};	---	4204	};	---
4205		---	4205		---
4206	static const uint32_t DSPCCSubClassMask[] = {	---	4206	static const uint32_t DSPCCSubClassMask[] = {	---
4207	0x80000000, 0x00000000, 0x00000000,	---	4207	0x80000000, 0x00000000, 0x00000000,	---
4208	};	---	4208	};	---
4209		---	4209		---
4210	static const uint32_t GP32SubClassMask[] = {	---	4210	static const uint32_t GP32SubClassMask[] = {	---
4211	0x00000000, 0x00000001, 0x00000000,	---	4211	0x00000000, 0x00000001, 0x00000000,	---
4212	0x00000000, 0x04000000, 0x00000000, // sub_32	---	4212	0x00000000, 0x04000000, 0x00000000, // sub_32	---
4213	};	---	4213	};	---
4214		---	4214		---
4215	static const uint32_t GPR32ZEROSubClassMask[] = {	---	4215	static const uint32_t GPR32ZEROSubClassMask[] = {	---
4216	0x00000000, 0x00000002, 0x00000000,	---	4216	0x00000000, 0x00000002, 0x00000000,	---
4217	0x00000000, 0x10000000, 0x00000000, // sub_32	---	4217	0x00000000, 0x10000000, 0x00000000, // sub_32	---
4218	};	---	4218	};	---
4219		---	4219		---
4220	static const uint32_t HI32SubClassMask[] = {	---	4220	static const uint32_t HI32SubClassMask[] = {	---
4221	0x00000000, 0x00000004, 0x00000000,	---	4221	0x00000000, 0x00000004, 0x00000000,	---
4222	0x00000000, 0x20000000, 0x00000000, // sub_32	---	4222	0x00000000, 0x20000000, 0x00000000, // sub_32	---
4223	0x00000000, 0x02000000, 0x00000000, // sub_hi	---	4223	0x00000000, 0x02000000, 0x00000000, // sub_hi	---
4224	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	---	4224	0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32	---
4225	};	---	4225	};	---
4226		---	4226		---
4227	static const uint32_t LO32SubClassMask[] = {	---	4227	static const uint32_t LO32SubClassMask[] = {	---
4228	0x00000000, 0x00000008, 0x00000000,	---	4228	0x00000000, 0x00000008, 0x00000000,	---
4229	0x00000000, 0x40000000, 0x00000020, // sub_32	---	4229	0x00000000, 0x40000000, 0x00000020, // sub_32	---
4230	0x00000000, 0x02000000, 0x00000000, // sub_lo	---	4230	0x00000000, 0x02000000, 0x00000000, // sub_lo	---
4231	};	---	4231	};	---
4232		---	4232		---
4233	static const uint32_t SP32SubClassMask[] = {	---	4233	static const uint32_t SP32SubClassMask[] = {	---
4234	0x00000000, 0x00000010, 0x00000000,	---	4234	0x00000000, 0x00000010, 0x00000000,	---
4235	0x00000000, 0x80000000, 0x00000000, // sub_32	---	4235	0x00000000, 0x80000000, 0x00000000, // sub_32	---
4236	};	---	4236	};	---
4237		---	4237		---
4238	static const uint32_t FGR64SubClassMask[] = {	---	4238	static const uint32_t FGR64SubClassMask[] = {	---
4239	0x00000000, 0x00000020, 0x00000000,	---	4239	0x00000000, 0x00000020, 0x00000000,	---
4240	0x00000001, 0x00000000, 0x0000001f, // sub_64	---	4240	0x00000001, 0x00000000, 0x0000001f, // sub_64	---
4241	};	---	4241	};	---
4242		---	4242		---
4243	static const uint32_t GPR64SubClassMask[] = {	---	4243	static const uint32_t GPR64SubClassMask[] = {	---
4244	0x00000000, 0x9d3efec0, 0x00000000,	---	4244	0x00000000, 0x9d3efec0, 0x00000000,	---
4245	};	---	4245	};	---
4246		---	4246		---
4247	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {	---	4247	static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {	---
4248	0x00000000, 0x8d3ae680, 0x00000000,	---	4248	0x00000000, 0x8d3ae680, 0x00000000,	---
4249	};	---	4249	};	---
4250		---	4250		---
4251	static const uint32_t AFGR64SubClassMask[] = {	---	4251	static const uint32_t AFGR64SubClassMask[] = {	---
4252	0x00000000, 0x00000100, 0x00000000,	---	4252	0x00000000, 0x00000100, 0x00000000,	---
4253	};	---	4253	};	---
4254		---	4254		---
4255	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {	---	4255	static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {	---
4256	0x00000000, 0x813a2600, 0x00000000,	---	4256	0x00000000, 0x813a2600, 0x00000000,	---
4257	};	---	4257	};	---
4258		---	4258		---
4259	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {	---	4259	static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {	---
4260	0x00000000, 0x013a2400, 0x00000000,	---	4260	0x00000000, 0x013a2400, 0x00000000,	---
4261	};	---	4261	};	---
4262		---	4262		---
4263	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {	---	4263	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {	---
4264	0x00000000, 0x10264800, 0x00000000,	---	4264	0x00000000, 0x10264800, 0x00000000,	---
4265	};	---	4265	};	---
4266		---	4266		---
4267	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {	---	4267	static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {	---
4268	0x00000000, 0x113c3000, 0x00000000,	---	4268	0x00000000, 0x113c3000, 0x00000000,	---
4269	};	---	4269	};	---
4270		---	4270		---
4271	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---	4271	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---
4272	0x00000000, 0x01382000, 0x00000000,	---	4272	0x00000000, 0x01382000, 0x00000000,	---
4273	};	---	4273	};	---
4274		---	4274		---
4275	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	---	4275	static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {	---
4276	0x00000000, 0x00224000, 0x00000000,	---	4276	0x00000000, 0x00224000, 0x00000000,	---
4277	};	---	4277	};	---
4278		---	4278		---
4279	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {	---	4279	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {	---
4280	0x00000000, 0x01088000, 0x00000000,	---	4280	0x00000000, 0x01088000, 0x00000000,	---
4281	};	---	4281	};	---
4282		---	4282		---
4283	static const uint32_t ACC64DSPSubClassMask[] = {	---	4283	static const uint32_t ACC64DSPSubClassMask[] = {	---
4284	0x00000000, 0x02010000, 0x00000000,	---	4284	0x00000000, 0x02010000, 0x00000000,	---
4285	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	---	4285	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	---
4286	};	---	4286	};	---
4287		---	4287		---
4288	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	---	4288	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {	---
4289	0x00000000, 0x00220000, 0x00000000,	---	4289	0x00000000, 0x00220000, 0x00000000,	---
4290	};	---	4290	};	---
4291		---	4291		---
4292	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	---	4292	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {	---
4293	0x00000000, 0x10240000, 0x00000000,	---	4293	0x00000000, 0x10240000, 0x00000000,	---
4294	};	---	4294	};	---
4295		---	4295		---
4296	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	---	4296	static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {	---
4297	0x00000000, 0x01080000, 0x00000000,	---	4297	0x00000000, 0x01080000, 0x00000000,	---
4298	};	---	4298	};	---
4299		---	4299		---
4300	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {	---	4300	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {	---
4301	0x00000000, 0x01100000, 0x00000000,	---	4301	0x00000000, 0x01100000, 0x00000000,	---
4302	};	---	4302	};	---
4303		---	4303		---
4304	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---	4304	static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {	---
4305	0x00000000, 0x00200000, 0x00000000,	---	4305	0x00000000, 0x00200000, 0x00000000,	---
4306	};	---	4306	};	---
4307		---	4307		---
4308	static const uint32_t OCTEON_MPLSubClassMask[] = {	---	4308	static const uint32_t OCTEON_MPLSubClassMask[] = {	---
4309	0x00000000, 0x00400000, 0x00000000,	---	4309	0x00000000, 0x00400000, 0x00000000,	---
4310	};	---	4310	};	---
4311		---	4311		---
4312	static const uint32_t OCTEON_PSubClassMask[] = {	---	4312	static const uint32_t OCTEON_PSubClassMask[] = {	---
4313	0x00000000, 0x00800000, 0x00000000,	---	4313	0x00000000, 0x00800000, 0x00000000,	---
4314	};	---	4314	};	---
4315		---	4315		---
4316	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	---	4316	static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {	---
4317	0x00000000, 0x01000000, 0x00000000,	---	4317	0x00000000, 0x01000000, 0x00000000,	---
4318	};	---	4318	};	---
4319		---	4319		---
4320	static const uint32_t ACC64SubClassMask[] = {	---	4320	static const uint32_t ACC64SubClassMask[] = {	---
4321	0x00000000, 0x02000000, 0x00000000,	---	4321	0x00000000, 0x02000000, 0x00000000,	---
4322	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	---	4322	0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32	---
4323	};	---	4323	};	---
4324		---	4324		---
4325	static const uint32_t GP64SubClassMask[] = {	---	4325	static const uint32_t GP64SubClassMask[] = {	---
4326	0x00000000, 0x04000000, 0x00000000,	---	4326	0x00000000, 0x04000000, 0x00000000,	---
4327	};	---	4327	};	---
4328		---	4328		---
4329	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {	---	4329	static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {	---
4330	0x00000000, 0x08000000, 0x00000000,	---	4330	0x00000000, 0x08000000, 0x00000000,	---
4331	};	---	4331	};	---
4332		---	4332		---
4333	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {	---	4333	static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {	---
4334	0x00000000, 0x10000000, 0x00000000,	---	4334	0x00000000, 0x10000000, 0x00000000,	---
4335	};	---	4335	};	---
4336		---	4336		---
4337	static const uint32_t HI64SubClassMask[] = {	---	4337	static const uint32_t HI64SubClassMask[] = {	---
4338	0x00000000, 0x20000000, 0x00000000,	---	4338	0x00000000, 0x20000000, 0x00000000,	---
4339	0x00000000, 0x00000000, 0x00000020, // sub_hi	---	4339	0x00000000, 0x00000000, 0x00000020, // sub_hi	---
4340	};	---	4340	};	---
4341		---	4341		---
4342	static const uint32_t LO64SubClassMask[] = {	---	4342	static const uint32_t LO64SubClassMask[] = {	---
4343	0x00000000, 0x40000000, 0x00000000,	---	4343	0x00000000, 0x40000000, 0x00000000,	---
4344	0x00000000, 0x00000000, 0x00000020, // sub_lo	---	4344	0x00000000, 0x00000000, 0x00000020, // sub_lo	---
4345	};	---	4345	};	---
4346		---	4346		---
4347	static const uint32_t SP64SubClassMask[] = {	---	4347	static const uint32_t SP64SubClassMask[] = {	---
4348	0x00000000, 0x80000000, 0x00000000,	---	4348	0x00000000, 0x80000000, 0x00000000,	---
4349	};	---	4349	};	---
4350		---	4350		---
4351	static const uint32_t MSA128BSubClassMask[] = {	---	4351	static const uint32_t MSA128BSubClassMask[] = {	---
4352	0x00000000, 0x00000000, 0x0000001f,	---	4352	0x00000000, 0x00000000, 0x0000001f,	---
4353	};	---	4353	};	---
4354		---	4354		---
4355	static const uint32_t MSA128DSubClassMask[] = {	---	4355	static const uint32_t MSA128DSubClassMask[] = {	---
4356	0x00000000, 0x00000000, 0x0000001f,	---	4356	0x00000000, 0x00000000, 0x0000001f,	---
4357	};	---	4357	};	---
4358		---	4358		---
4359	static const uint32_t MSA128HSubClassMask[] = {	---	4359	static const uint32_t MSA128HSubClassMask[] = {	---
4360	0x00000000, 0x00000000, 0x0000001f,	---	4360	0x00000000, 0x00000000, 0x0000001f,	---
4361	};	---	4361	};	---
4362		---	4362		---
4363	static const uint32_t MSA128WSubClassMask[] = {	---	4363	static const uint32_t MSA128WSubClassMask[] = {	---
4364	0x00000000, 0x00000000, 0x0000001f,	---	4364	0x00000000, 0x00000000, 0x0000001f,	---
4365	};	---	4365	};	---
4366		---	4366		---
4367	static const uint32_t MSA128WEvensSubClassMask[] = {	---	4367	static const uint32_t MSA128WEvensSubClassMask[] = {	---
4368	0x00000000, 0x00000000, 0x00000010,	---	4368	0x00000000, 0x00000000, 0x00000010,	---
4369	};	---	4369	};	---
4370		---	4370		---
4371	static const uint32_t ACC128SubClassMask[] = {	---	4371	static const uint32_t ACC128SubClassMask[] = {	---
4372	0x00000000, 0x00000000, 0x00000020,	---	4372	0x00000000, 0x00000000, 0x00000020,	---
4373	};	---	4373	};	---
4374		---	4374		---
4375	static const uint16_t SuperRegIdxSeqs[] = {	---	4375	static const uint16_t SuperRegIdxSeqs[] = {	---
4376	/* 0 */ 1, 0,	---	4376	/* 0 */ 1, 0,	---
4377	/* 2 */ 2, 0,	---	4377	/* 2 */ 2, 0,	---
4378	/* 4 */ 8, 0,	---	4378	/* 4 */ 8, 0,	---
4379	/* 6 */ 1, 9, 0,	---	4379	/* 6 */ 1, 9, 0,	---
4380	/* 9 */ 8, 9, 0,	---	4380	/* 9 */ 8, 9, 0,	---
4381	/* 12 */ 1, 8, 10, 0,	---	4381	/* 12 */ 1, 8, 10, 0,	---
4382	/* 16 */ 11, 0,	---	4382	/* 16 */ 11, 0,	---
4383	};	---	4383	};	---
4384		---	4384		---
4385	static const TargetRegisterClass *const FGR32Superclasses[] = {	---	4385	static const TargetRegisterClass *const FGR32Superclasses[] = {	---
4386	&Mips::FGRCCRegClass,	---	4386	&Mips::FGRCCRegClass,	---
4387	nullptr	---	4387	nullptr	---
4388	};	---	4388	};	---
4389		---	4389		---
4390	static const TargetRegisterClass *const FGRCCSuperclasses[] = {	---	4390	static const TargetRegisterClass *const FGRCCSuperclasses[] = {	---
4391	&Mips::FGR32RegClass,	---	4391	&Mips::FGR32RegClass,	---
4392	nullptr	---	4392	nullptr	---
4393	};	---	4393	};	---
4394		---	4394		---
4395	static const TargetRegisterClass *const GPR32Superclasses[] = {	---	4395	static const TargetRegisterClass *const GPR32Superclasses[] = {	---
4396	&Mips::DSPRRegClass,	---	4396	&Mips::DSPRRegClass,	---
4397	nullptr	---	4397	nullptr	---
4398	};	---	4398	};	---
4399		---	4399		---
4400	static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {	---	4400	static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {	---
4401	&Mips::DSPRRegClass,	---	4401	&Mips::DSPRRegClass,	---
4402	&Mips::GPR32RegClass,	---	4402	&Mips::GPR32RegClass,	---
4403	nullptr	---	4403	nullptr	---
4404	};	---	4404	};	---
4405		---	4405		---
4406	static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {	---	4406	static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {	---
4407	&Mips::DSPRRegClass,	---	4407	&Mips::DSPRRegClass,	---
4408	&Mips::GPR32RegClass,	---	4408	&Mips::GPR32RegClass,	---
4409	&Mips::GPR32NONZERORegClass,	---	4409	&Mips::GPR32NONZERORegClass,	---
4410	nullptr	---	4410	nullptr	---
4411	};	---	4411	};	---
4412		---	4412		---
4413	static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {	---	4413	static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {	---
4414	&Mips::DSPRRegClass,	---	4414	&Mips::DSPRRegClass,	---
4415	&Mips::GPR32RegClass,	---	4415	&Mips::GPR32RegClass,	---
4416	&Mips::GPR32NONZERORegClass,	---	4416	&Mips::GPR32NONZERORegClass,	---
4417	&Mips::CPU16RegsPlusSPRegClass,	---	4417	&Mips::CPU16RegsPlusSPRegClass,	---
4418	nullptr	---	4418	nullptr	---
4419	};	---	4419	};	---
4420		---	4420		---
4421	static const TargetRegisterClass *const GPRMM16Superclasses[] = {	---	4421	static const TargetRegisterClass *const GPRMM16Superclasses[] = {	---
4422	&Mips::DSPRRegClass,	---	4422	&Mips::DSPRRegClass,	---
4423	&Mips::GPR32RegClass,	---	4423	&Mips::GPR32RegClass,	---
4424	&Mips::GPR32NONZERORegClass,	---	4424	&Mips::GPR32NONZERORegClass,	---
4425	&Mips::CPU16RegsPlusSPRegClass,	---	4425	&Mips::CPU16RegsPlusSPRegClass,	---
4426	&Mips::CPU16RegsRegClass,	---	4426	&Mips::CPU16RegsRegClass,	---
4427	nullptr	---	4427	nullptr	---
4428	};	---	4428	};	---
4429		---	4429		---
4430	static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {	---	4430	static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {	---
4431	&Mips::DSPRRegClass,	---	4431	&Mips::DSPRRegClass,	---
4432	&Mips::GPR32RegClass,	---	4432	&Mips::GPR32RegClass,	---
4433	nullptr	---	4433	nullptr	---
4434	};	---	4434	};	---
4435		---	4435		---
4436	static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {	---	4436	static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {	---
4437	&Mips::DSPRRegClass,	---	4437	&Mips::DSPRRegClass,	---
4438	&Mips::GPR32RegClass,	---	4438	&Mips::GPR32RegClass,	---
4439	nullptr	---	4439	nullptr	---
4440	};	---	4440	};	---
4441		---	4441		---
4442	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---	4442	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---
4443	&Mips::DSPRRegClass,	---	4443	&Mips::DSPRRegClass,	---
4444	&Mips::GPR32RegClass,	---	4444	&Mips::GPR32RegClass,	---
4445	&Mips::GPR32NONZERORegClass,	---	4445	&Mips::GPR32NONZERORegClass,	---
4446	&Mips::CPU16RegsPlusSPRegClass,	---	4446	&Mips::CPU16RegsPlusSPRegClass,	---
4447	&Mips::CPU16RegsRegClass,	---	4447	&Mips::CPU16RegsRegClass,	---
4448	&Mips::GPRMM16RegClass,	---	4448	&Mips::GPRMM16RegClass,	---
4449	&Mips::GPRMM16ZeroRegClass,	---	4449	&Mips::GPRMM16ZeroRegClass,	---
4450	nullptr	---	4450	nullptr	---
4451	};	---	4451	};	---
4452		---	4452		---
4453	static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	---	4453	static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	---
4454	&Mips::DSPRRegClass,	---	4454	&Mips::DSPRRegClass,	---
4455	&Mips::GPR32RegClass,	---	4455	&Mips::GPR32RegClass,	---
4456	&Mips::GPR32NONZERORegClass,	---	4456	&Mips::GPR32NONZERORegClass,	---
4457	&Mips::GPRMM16MovePRegClass,	---	4457	&Mips::GPRMM16MovePRegClass,	---
4458	nullptr	---	4458	nullptr	---
4459	};	---	4459	};	---
4460		---	4460		---
4461	static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {	---	4461	static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {	---
4462	&Mips::DSPRRegClass,	---	4462	&Mips::DSPRRegClass,	---
4463	&Mips::GPR32RegClass,	---	4463	&Mips::GPR32RegClass,	---
4464	&Mips::GPR32NONZERORegClass,	---	4464	&Mips::GPR32NONZERORegClass,	---
4465	nullptr	---	4465	nullptr	---
4466	};	---	4466	};	---
4467		---	4467		---
4468	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	---	4468	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	---
4469	&Mips::DSPRRegClass,	---	4469	&Mips::DSPRRegClass,	---
4470	&Mips::GPR32RegClass,	---	4470	&Mips::GPR32RegClass,	---
4471	&Mips::GPR32NONZERORegClass,	---	4471	&Mips::GPR32NONZERORegClass,	---
4472	&Mips::CPU16RegsPlusSPRegClass,	---	4472	&Mips::CPU16RegsPlusSPRegClass,	---
4473	&Mips::CPU16RegsRegClass,	---	4473	&Mips::CPU16RegsRegClass,	---
4474	&Mips::GPRMM16RegClass,	---	4474	&Mips::GPRMM16RegClass,	---
4475	&Mips::GPRMM16MovePRegClass,	---	4475	&Mips::GPRMM16MovePRegClass,	---
4476	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---	4476	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---
4477	nullptr	---	4477	nullptr	---
4478	};	---	4478	};	---
4479		---	4479		---
4480	static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	---	4480	static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	---
4481	&Mips::DSPRRegClass,	---	4481	&Mips::DSPRRegClass,	---
4482	&Mips::GPR32RegClass,	---	4482	&Mips::GPR32RegClass,	---
4483	&Mips::GPRMM16MovePRegClass,	---	4483	&Mips::GPRMM16MovePRegClass,	---
4484	&Mips::GPRMM16ZeroRegClass,	---	4484	&Mips::GPRMM16ZeroRegClass,	---
4485	nullptr	---	4485	nullptr	---
4486	};	---	4486	};	---
4487		---	4487		---
4488	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	---	4488	static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	---
4489	&Mips::DSPRRegClass,	---	4489	&Mips::DSPRRegClass,	---
4490	&Mips::GPR32RegClass,	---	4490	&Mips::GPR32RegClass,	---
4491	&Mips::GPR32NONZERORegClass,	---	4491	&Mips::GPR32NONZERORegClass,	---
4492	&Mips::CPU16RegsPlusSPRegClass,	---	4492	&Mips::CPU16RegsPlusSPRegClass,	---
4493	&Mips::CPU16RegsRegClass,	---	4493	&Mips::CPU16RegsRegClass,	---
4494	&Mips::GPRMM16RegClass,	---	4494	&Mips::GPRMM16RegClass,	---
4495	&Mips::GPRMM16ZeroRegClass,	---	4495	&Mips::GPRMM16ZeroRegClass,	---
4496	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---	4496	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---
4497	&Mips::GPRMM16MovePPairSecondRegClass,	---	4497	&Mips::GPRMM16MovePPairSecondRegClass,	---
4498	nullptr	---	4498	nullptr	---
4499	};	---	4499	};	---
4500		---	4500		---
4501	static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {	---	4501	static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {	---
4502	&Mips::DSPRRegClass,	---	4502	&Mips::DSPRRegClass,	---
4503	&Mips::GPR32RegClass,	---	4503	&Mips::GPR32RegClass,	---
4504	&Mips::GPR32NONZERORegClass,	---	4504	&Mips::GPR32NONZERORegClass,	---
4505	&Mips::CPU16RegsPlusSPRegClass,	---	4505	&Mips::CPU16RegsPlusSPRegClass,	---
4506	&Mips::CPU16RegsRegClass,	---	4506	&Mips::CPU16RegsRegClass,	---
4507	&Mips::GPRMM16RegClass,	---	4507	&Mips::GPRMM16RegClass,	---
4508	&Mips::GPRMM16ZeroRegClass,	---	4508	&Mips::GPRMM16ZeroRegClass,	---
4509	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---	4509	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---
4510	nullptr	---	4510	nullptr	---
4511	};	---	4511	};	---
4512		---	4512		---
4513	static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---	4513	static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---
4514	&Mips::DSPRRegClass,	---	4514	&Mips::DSPRRegClass,	---
4515	&Mips::GPR32RegClass,	---	4515	&Mips::GPR32RegClass,	---
4516	&Mips::GPR32NONZERORegClass,	---	4516	&Mips::GPR32NONZERORegClass,	---
4517	&Mips::CPU16RegsPlusSPRegClass,	---	4517	&Mips::CPU16RegsPlusSPRegClass,	---
4518	&Mips::CPU16RegsRegClass,	---	4518	&Mips::CPU16RegsRegClass,	---
4519	&Mips::GPRMM16RegClass,	---	4519	&Mips::GPRMM16RegClass,	---
4520	&Mips::GPRMM16MovePRegClass,	---	4520	&Mips::GPRMM16MovePRegClass,	---
4521	&Mips::GPRMM16ZeroRegClass,	---	4521	&Mips::GPRMM16ZeroRegClass,	---
4522	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---	4522	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---
4523	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---	4523	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---
4524	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	---	4524	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	---
4525	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	4525	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
4526	nullptr	---	4526	nullptr	---
4527	};	---	4527	};	---
4528		---	4528		---
4529	static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	---	4529	static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	---
4530	&Mips::DSPRRegClass,	---	4530	&Mips::DSPRRegClass,	---
4531	&Mips::GPR32RegClass,	---	4531	&Mips::GPR32RegClass,	---
4532	&Mips::GPR32NONZERORegClass,	---	4532	&Mips::GPR32NONZERORegClass,	---
4533	&Mips::CPU16RegsPlusSPRegClass,	---	4533	&Mips::CPU16RegsPlusSPRegClass,	---
4534	&Mips::CPU16RegsRegClass,	---	4534	&Mips::CPU16RegsRegClass,	---
4535	&Mips::GPRMM16RegClass,	---	4535	&Mips::GPRMM16RegClass,	---
4536	&Mips::GPRMM16ZeroRegClass,	---	4536	&Mips::GPRMM16ZeroRegClass,	---
4537	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---	4537	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---
4538	&Mips::GPRMM16MovePPairSecondRegClass,	---	4538	&Mips::GPRMM16MovePPairSecondRegClass,	---
4539	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---	4539	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---
4540	&Mips::GPRMM16MovePPairFirstRegClass,	---	4540	&Mips::GPRMM16MovePPairFirstRegClass,	---
4541	nullptr	---	4541	nullptr	---
4542	};	---	4542	};	---
4543		---	4543		---
4544	static const TargetRegisterClass *const CPURARegSuperclasses[] = {	---	4544	static const TargetRegisterClass *const CPURARegSuperclasses[] = {	---
4545	&Mips::DSPRRegClass,	---	4545	&Mips::DSPRRegClass,	---
4546	&Mips::GPR32RegClass,	---	4546	&Mips::GPR32RegClass,	---
4547	&Mips::GPR32NONZERORegClass,	---	4547	&Mips::GPR32NONZERORegClass,	---
4548	nullptr	---	4548	nullptr	---
4549	};	---	4549	};	---
4550		---	4550		---
4551	static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {	---	4551	static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {	---
4552	&Mips::DSPRRegClass,	---	4552	&Mips::DSPRRegClass,	---
4553	&Mips::GPR32RegClass,	---	4553	&Mips::GPR32RegClass,	---
4554	&Mips::GPR32NONZERORegClass,	---	4554	&Mips::GPR32NONZERORegClass,	---
4555	&Mips::CPU16RegsPlusSPRegClass,	---	4555	&Mips::CPU16RegsPlusSPRegClass,	---
4556	nullptr	---	4556	nullptr	---
4557	};	---	4557	};	---
4558		---	4558		---
4559	static const TargetRegisterClass *const GP32Superclasses[] = {	---	4559	static const TargetRegisterClass *const GP32Superclasses[] = {	---
4560	&Mips::DSPRRegClass,	---	4560	&Mips::DSPRRegClass,	---
4561	&Mips::GPR32RegClass,	---	4561	&Mips::GPR32RegClass,	---
4562	&Mips::GPR32NONZERORegClass,	---	4562	&Mips::GPR32NONZERORegClass,	---
4563	nullptr	---	4563	nullptr	---
4564	};	---	4564	};	---
4565		---	4565		---
4566	static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {	---	4566	static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {	---
4567	&Mips::DSPRRegClass,	---	4567	&Mips::DSPRRegClass,	---
4568	&Mips::GPR32RegClass,	---	4568	&Mips::GPR32RegClass,	---
4569	&Mips::GPRMM16MovePRegClass,	---	4569	&Mips::GPRMM16MovePRegClass,	---
4570	&Mips::GPRMM16ZeroRegClass,	---	4570	&Mips::GPRMM16ZeroRegClass,	---
4571	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	4571	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
4572	nullptr	---	4572	nullptr	---
4573	};	---	4573	};	---
4574		---	4574		---
4575	static const TargetRegisterClass *const HI32Superclasses[] = {	---	4575	static const TargetRegisterClass *const HI32Superclasses[] = {	---
4576	&Mips::HI32DSPRegClass,	---	4576	&Mips::HI32DSPRegClass,	---
4577	nullptr	---	4577	nullptr	---
4578	};	---	4578	};	---
4579		---	4579		---
4580	static const TargetRegisterClass *const LO32Superclasses[] = {	---	4580	static const TargetRegisterClass *const LO32Superclasses[] = {	---
4581	&Mips::LO32DSPRegClass,	---	4581	&Mips::LO32DSPRegClass,	---
4582	nullptr	---	4582	nullptr	---
4583	};	---	4583	};	---
4584		---	4584		---
4585	static const TargetRegisterClass *const SP32Superclasses[] = {	---	4585	static const TargetRegisterClass *const SP32Superclasses[] = {	---
4586	&Mips::DSPRRegClass,	---	4586	&Mips::DSPRRegClass,	---
4587	&Mips::GPR32RegClass,	---	4587	&Mips::GPR32RegClass,	---
4588	&Mips::GPR32NONZERORegClass,	---	4588	&Mips::GPR32NONZERORegClass,	---
4589	&Mips::CPU16RegsPlusSPRegClass,	---	4589	&Mips::CPU16RegsPlusSPRegClass,	---
4590	&Mips::CPUSPRegRegClass,	---	4590	&Mips::CPUSPRegRegClass,	---
4591	nullptr	---	4591	nullptr	---
4592	};	---	4592	};	---
4593		---	4593		---
4594	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {	---	4594	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {	---
4595	&Mips::GPR64RegClass,	---	4595	&Mips::GPR64RegClass,	---
4596	nullptr	---	4596	nullptr	---
4597	};	---	4597	};	---
4598		---	4598		---
4599	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {	---	4599	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {	---
4600	&Mips::GPR64RegClass,	---	4600	&Mips::GPR64RegClass,	---
4601	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4601	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4602	nullptr	---	4602	nullptr	---
4603	};	---	4603	};	---
4604		---	4604		---
4605	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {	---	4605	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {	---
4606	&Mips::GPR64RegClass,	---	4606	&Mips::GPR64RegClass,	---
4607	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4607	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4608	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4608	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4609	nullptr	---	4609	nullptr	---
4610	};	---	4610	};	---
4611		---	4611		---
4612	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {	---	4612	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {	---
4613	&Mips::GPR64RegClass,	---	4613	&Mips::GPR64RegClass,	---
4614	nullptr	---	4614	nullptr	---
4615	};	---	4615	};	---
4616		---	4616		---
4617	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {	---	4617	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {	---
4618	&Mips::GPR64RegClass,	---	4618	&Mips::GPR64RegClass,	---
4619	nullptr	---	4619	nullptr	---
4620	};	---	4620	};	---
4621		---	4621		---
4622	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---	4622	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---
4623	&Mips::GPR64RegClass,	---	4623	&Mips::GPR64RegClass,	---
4624	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4624	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4625	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4625	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4626	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4626	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4627	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4627	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4628	nullptr	---	4628	nullptr	---
4629	};	---	4629	};	---
4630		---	4630		---
4631	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	---	4631	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {	---
4632	&Mips::GPR64RegClass,	---	4632	&Mips::GPR64RegClass,	---
4633	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4633	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4634	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	4634	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
4635	nullptr	---	4635	nullptr	---
4636	};	---	4636	};	---
4637		---	4637		---
4638	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {	---	4638	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {	---
4639	&Mips::GPR64RegClass,	---	4639	&Mips::GPR64RegClass,	---
4640	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4640	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4641	nullptr	---	4641	nullptr	---
4642	};	---	4642	};	---
4643		---	4643		---
4644	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	---	4644	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {	---
4645	&Mips::GPR64RegClass,	---	4645	&Mips::GPR64RegClass,	---
4646	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4646	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4647	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4647	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4648	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4648	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4649	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	4649	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
4650	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---	4650	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---
4651	nullptr	---	4651	nullptr	---
4652	};	---	4652	};	---
4653		---	4653		---
4654	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	---	4654	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {	---
4655	&Mips::GPR64RegClass,	---	4655	&Mips::GPR64RegClass,	---
4656	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	4656	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
4657	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4657	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4658	nullptr	---	4658	nullptr	---
4659	};	---	4659	};	---
4660		---	4660		---
4661	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	---	4661	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {	---
4662	&Mips::GPR64RegClass,	---	4662	&Mips::GPR64RegClass,	---
4663	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4663	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4664	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4664	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4665	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4665	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4666	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4666	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4667	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---	4667	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---
4668	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---	4668	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---
4669	nullptr	---	4669	nullptr	---
4670	};	---	4670	};	---
4671		---	4671		---
4672	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {	---	4672	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {	---
4673	&Mips::GPR64RegClass,	---	4673	&Mips::GPR64RegClass,	---
4674	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4674	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4675	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4675	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4676	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4676	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4677	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4677	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4678	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---	4678	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---
4679	nullptr	---	4679	nullptr	---
4680	};	---	4680	};	---
4681		---	4681		---
4682	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---	4682	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {	---
4683	&Mips::GPR64RegClass,	---	4683	&Mips::GPR64RegClass,	---
4684	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4684	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4685	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4685	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4686	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4686	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4687	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	4687	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
4688	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4688	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4689	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---	4689	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---
4690	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---	4690	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---
4691	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	---	4691	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	---
4692	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	4692	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
4693	nullptr	---	4693	nullptr	---
4694	};	---	4694	};	---
4695		---	4695		---
4696	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	---	4696	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {	---
4697	&Mips::GPR64RegClass,	---	4697	&Mips::GPR64RegClass,	---
4698	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4698	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4699	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4699	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4700	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	4700	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
4701	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4701	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4702	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---	4702	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---
4703	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---	4703	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---
4704	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---	4704	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---
4705	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	---	4705	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	---
4706	nullptr	---	4706	nullptr	---
4707	};	---	4707	};	---
4708		---	4708		---
4709	static const TargetRegisterClass *const ACC64Superclasses[] = {	---	4709	static const TargetRegisterClass *const ACC64Superclasses[] = {	---
4710	&Mips::ACC64DSPRegClass,	---	4710	&Mips::ACC64DSPRegClass,	---
4711	nullptr	---	4711	nullptr	---
4712	};	---	4712	};	---
4713		---	4713		---
4714	static const TargetRegisterClass *const GP64Superclasses[] = {	---	4714	static const TargetRegisterClass *const GP64Superclasses[] = {	---
4715	&Mips::GPR64RegClass,	---	4715	&Mips::GPR64RegClass,	---
4716	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4716	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4717	nullptr	---	4717	nullptr	---
4718	};	---	4718	};	---
4719		---	4719		---
4720	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {	---	4720	static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {	---
4721	&Mips::GPR64RegClass,	---	4721	&Mips::GPR64RegClass,	---
4722	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4722	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4723	nullptr	---	4723	nullptr	---
4724	};	---	4724	};	---
4725		---	4725		---
4726	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {	---	4726	static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {	---
4727	&Mips::GPR64RegClass,	---	4727	&Mips::GPR64RegClass,	---
4728	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	4728	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
4729	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	4729	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
4730	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	4730	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
4731	nullptr	---	4731	nullptr	---
4732	};	---	4732	};	---
4733		---	4733		---
4734	static const TargetRegisterClass *const SP64Superclasses[] = {	---	4734	static const TargetRegisterClass *const SP64Superclasses[] = {	---
4735	&Mips::GPR64RegClass,	---	4735	&Mips::GPR64RegClass,	---
4736	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	4736	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
4737	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	4737	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
4738	nullptr	---	4738	nullptr	---
4739	};	---	4739	};	---
4740		---	4740		---
4741	static const TargetRegisterClass *const MSA128BSuperclasses[] = {	---	4741	static const TargetRegisterClass *const MSA128BSuperclasses[] = {	---
4742	&Mips::MSA128F16RegClass,	---	4742	&Mips::MSA128F16RegClass,	---
4743	&Mips::MSA128DRegClass,	---	4743	&Mips::MSA128DRegClass,	---
4744	&Mips::MSA128HRegClass,	---	4744	&Mips::MSA128HRegClass,	---
4745	&Mips::MSA128WRegClass,	---	4745	&Mips::MSA128WRegClass,	---
4746	nullptr	---	4746	nullptr	---
4747	};	---	4747	};	---
4748		---	4748		---
4749	static const TargetRegisterClass *const MSA128DSuperclasses[] = {	---	4749	static const TargetRegisterClass *const MSA128DSuperclasses[] = {	---
4750	&Mips::MSA128F16RegClass,	---	4750	&Mips::MSA128F16RegClass,	---
4751	&Mips::MSA128BRegClass,	---	4751	&Mips::MSA128BRegClass,	---
4752	&Mips::MSA128HRegClass,	---	4752	&Mips::MSA128HRegClass,	---
4753	&Mips::MSA128WRegClass,	---	4753	&Mips::MSA128WRegClass,	---
4754	nullptr	---	4754	nullptr	---
4755	};	---	4755	};	---
4756		---	4756		---
4757	static const TargetRegisterClass *const MSA128HSuperclasses[] = {	---	4757	static const TargetRegisterClass *const MSA128HSuperclasses[] = {	---
4758	&Mips::MSA128F16RegClass,	---	4758	&Mips::MSA128F16RegClass,	---
4759	&Mips::MSA128BRegClass,	---	4759	&Mips::MSA128BRegClass,	---
4760	&Mips::MSA128DRegClass,	---	4760	&Mips::MSA128DRegClass,	---
4761	&Mips::MSA128WRegClass,	---	4761	&Mips::MSA128WRegClass,	---
4762	nullptr	---	4762	nullptr	---
4763	};	---	4763	};	---
4764		---	4764		---
4765	static const TargetRegisterClass *const MSA128WSuperclasses[] = {	---	4765	static const TargetRegisterClass *const MSA128WSuperclasses[] = {	---
4766	&Mips::MSA128F16RegClass,	---	4766	&Mips::MSA128F16RegClass,	---
4767	&Mips::MSA128BRegClass,	---	4767	&Mips::MSA128BRegClass,	---
4768	&Mips::MSA128DRegClass,	---	4768	&Mips::MSA128DRegClass,	---
4769	&Mips::MSA128HRegClass,	---	4769	&Mips::MSA128HRegClass,	---
4770	nullptr	---	4770	nullptr	---
4771	};	---	4771	};	---
4772		---	4772		---
4773	static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {	---	4773	static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {	---
4774	&Mips::MSA128F16RegClass,	---	4774	&Mips::MSA128F16RegClass,	---
4775	&Mips::MSA128BRegClass,	---	4775	&Mips::MSA128BRegClass,	---
4776	&Mips::MSA128DRegClass,	---	4776	&Mips::MSA128DRegClass,	---
4777	&Mips::MSA128HRegClass,	---	4777	&Mips::MSA128HRegClass,	---
4778	&Mips::MSA128WRegClass,	---	4778	&Mips::MSA128WRegClass,	---
4779	nullptr	---	4779	nullptr	---
4780	};	---	4780	};	---
4781		---	4781		---
4782		---	4782		---
4783	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {	0	4783	static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {	0
4784	const auto & S = MF.getSubtarget();	0	4784	const auto & S = MF.getSubtarget();	0
4785	return S.isABI_O32() && !S.useOddSPReg();	0	4785	return S.isABI_O32() && !S.useOddSPReg();	0
4786	}	---	4786	}	---
4787		---	4787		---
4788	static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) {	0	4788	static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) {	0
4789	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };	---	4789	static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };	---
4790	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];	0	4790	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];	0
4791	const ArrayRef Order[] = {	---	4791	const ArrayRef Order[] = {	---
4792	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0	4792	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0
4793	ArrayRef(AltOrder1)	---	4793	ArrayRef(AltOrder1)	---
4794	};	0	4794	};	0
4795	const unsigned Select = FGR32AltOrderSelect(MF);	0	4795	const unsigned Select = FGR32AltOrderSelect(MF);	0
4796	assert(Select < 2);	0	4796	assert(Select < 2);	0
4797	return Order[Select];	0	4797	return Order[Select];	0
4798	}	---	4798	}	---
4799		---	4799		---
4800	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {	0	4800	static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {	0
4801	const auto & S = MF.getSubtarget();	0	4801	const auto & S = MF.getSubtarget();	0
4802	return S.isABI_O32() && !S.useOddSPReg();	0	4802	return S.isABI_O32() && !S.useOddSPReg();	0
4803	}	---	4803	}	---
4804		---	4804		---
4805	static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) {	0	4805	static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) {	0
4806	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };	---	4806	static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };	---
4807	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];	0	4807	const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];	0
4808	const ArrayRef Order[] = {	---	4808	const ArrayRef Order[] = {	---
4809	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0	4809	ArrayRef(MCR.begin(), MCR.getNumRegs()),	0
4810	ArrayRef(AltOrder1)	---	4810	ArrayRef(AltOrder1)	---
4811	};	0	4811	};	0
4812	const unsigned Select = FGR64AltOrderSelect(MF);	0	4812	const unsigned Select = FGR64AltOrderSelect(MF);	0
4813	assert(Select < 2);	0	4813	assert(Select < 2);	0
4814	return Order[Select];	0	4814	return Order[Select];	0
4815	}	---	4815	}	---
4816		---	4816		---
4817	namespace Mips { // Register class instances	---	4817	namespace Mips { // Register class instances	---
4818	extern const TargetRegisterClass MSA128F16RegClass = {	---	4818	extern const TargetRegisterClass MSA128F16RegClass = {	---
4819	&MipsMCRegisterClasses[MSA128F16RegClassID],	---	4819	&MipsMCRegisterClasses[MSA128F16RegClassID],	---
4820	MSA128F16SubClassMask,	---	4820	MSA128F16SubClassMask,	---
4821	SuperRegIdxSeqs + 1,	---	4821	SuperRegIdxSeqs + 1,	---
4822	LaneBitmask(0x0000000000000041),	---	4822	LaneBitmask(0x0000000000000041),	---
4823	0,	---	4823	0,	---
4824	false,	---	4824	false,	---
4825	0x00, /* TSFlags */	---	4825	0x00, /* TSFlags */	---
4826	true, /* HasDisjunctSubRegs */	---	4826	true, /* HasDisjunctSubRegs */	---
4827	false, /* CoveredBySubRegs */	---	4827	false, /* CoveredBySubRegs */	---
4828	NullRegClasses,	---	4828	NullRegClasses,	---
4829	nullptr	---	4829	nullptr	---
4830	};	---	4830	};	---
4831		---	4831		---
4832	extern const TargetRegisterClass CCRRegClass = {	---	4832	extern const TargetRegisterClass CCRRegClass = {	---
4833	&MipsMCRegisterClasses[CCRRegClassID],	---	4833	&MipsMCRegisterClasses[CCRRegClassID],	---
4834	CCRSubClassMask,	---	4834	CCRSubClassMask,	---
4835	SuperRegIdxSeqs + 1,	---	4835	SuperRegIdxSeqs + 1,	---
4836	LaneBitmask(0x0000000000000001),	---	4836	LaneBitmask(0x0000000000000001),	---
4837	0,	---	4837	0,	---
4838	false,	---	4838	false,	---
4839	0x00, /* TSFlags */	---	4839	0x00, /* TSFlags */	---
4840	false, /* HasDisjunctSubRegs */	---	4840	false, /* HasDisjunctSubRegs */	---
4841	false, /* CoveredBySubRegs */	---	4841	false, /* CoveredBySubRegs */	---
4842	NullRegClasses,	---	4842	NullRegClasses,	---
4843	nullptr	---	4843	nullptr	---
4844	};	---	4844	};	---
4845		---	4845		---
4846	extern const TargetRegisterClass COP0RegClass = {	---	4846	extern const TargetRegisterClass COP0RegClass = {	---
4847	&MipsMCRegisterClasses[COP0RegClassID],	---	4847	&MipsMCRegisterClasses[COP0RegClassID],	---
4848	COP0SubClassMask,	---	4848	COP0SubClassMask,	---
4849	SuperRegIdxSeqs + 1,	---	4849	SuperRegIdxSeqs + 1,	---
4850	LaneBitmask(0x0000000000000001),	---	4850	LaneBitmask(0x0000000000000001),	---
4851	0,	---	4851	0,	---
4852	false,	---	4852	false,	---
4853	0x00, /* TSFlags */	---	4853	0x00, /* TSFlags */	---
4854	false, /* HasDisjunctSubRegs */	---	4854	false, /* HasDisjunctSubRegs */	---
4855	false, /* CoveredBySubRegs */	---	4855	false, /* CoveredBySubRegs */	---
4856	NullRegClasses,	---	4856	NullRegClasses,	---
4857	nullptr	---	4857	nullptr	---
4858	};	---	4858	};	---
4859		---	4859		---
4860	extern const TargetRegisterClass COP2RegClass = {	---	4860	extern const TargetRegisterClass COP2RegClass = {	---
4861	&MipsMCRegisterClasses[COP2RegClassID],	---	4861	&MipsMCRegisterClasses[COP2RegClassID],	---
4862	COP2SubClassMask,	---	4862	COP2SubClassMask,	---
4863	SuperRegIdxSeqs + 1,	---	4863	SuperRegIdxSeqs + 1,	---
4864	LaneBitmask(0x0000000000000001),	---	4864	LaneBitmask(0x0000000000000001),	---
4865	0,	---	4865	0,	---
4866	false,	---	4866	false,	---
4867	0x00, /* TSFlags */	---	4867	0x00, /* TSFlags */	---
4868	false, /* HasDisjunctSubRegs */	---	4868	false, /* HasDisjunctSubRegs */	---
4869	false, /* CoveredBySubRegs */	---	4869	false, /* CoveredBySubRegs */	---
4870	NullRegClasses,	---	4870	NullRegClasses,	---
4871	nullptr	---	4871	nullptr	---
4872	};	---	4872	};	---
4873		---	4873		---
4874	extern const TargetRegisterClass COP3RegClass = {	---	4874	extern const TargetRegisterClass COP3RegClass = {	---
4875	&MipsMCRegisterClasses[COP3RegClassID],	---	4875	&MipsMCRegisterClasses[COP3RegClassID],	---
4876	COP3SubClassMask,	---	4876	COP3SubClassMask,	---
4877	SuperRegIdxSeqs + 1,	---	4877	SuperRegIdxSeqs + 1,	---
4878	LaneBitmask(0x0000000000000001),	---	4878	LaneBitmask(0x0000000000000001),	---
4879	0,	---	4879	0,	---
4880	false,	---	4880	false,	---
4881	0x00, /* TSFlags */	---	4881	0x00, /* TSFlags */	---
4882	false, /* HasDisjunctSubRegs */	---	4882	false, /* HasDisjunctSubRegs */	---
4883	false, /* CoveredBySubRegs */	---	4883	false, /* CoveredBySubRegs */	---
4884	NullRegClasses,	---	4884	NullRegClasses,	---
4885	nullptr	---	4885	nullptr	---
4886	};	---	4886	};	---
4887		---	4887		---
4888	extern const TargetRegisterClass DSPRRegClass = {	---	4888	extern const TargetRegisterClass DSPRRegClass = {	---
4889	&MipsMCRegisterClasses[DSPRRegClassID],	---	4889	&MipsMCRegisterClasses[DSPRRegClassID],	---
4890	DSPRSubClassMask,	---	4890	DSPRSubClassMask,	---
4891	SuperRegIdxSeqs + 0,	---	4891	SuperRegIdxSeqs + 0,	---
4892	LaneBitmask(0x0000000000000001),	---	4892	LaneBitmask(0x0000000000000001),	---
4893	0,	---	4893	0,	---
4894	false,	---	4894	false,	---
4895	0x00, /* TSFlags */	---	4895	0x00, /* TSFlags */	---
4896	false, /* HasDisjunctSubRegs */	---	4896	false, /* HasDisjunctSubRegs */	---
4897	false, /* CoveredBySubRegs */	---	4897	false, /* CoveredBySubRegs */	---
4898	NullRegClasses,	---	4898	NullRegClasses,	---
4899	nullptr	---	4899	nullptr	---
4900	};	---	4900	};	---
4901		---	4901		---
4902	extern const TargetRegisterClass FGR32RegClass = {	---	4902	extern const TargetRegisterClass FGR32RegClass = {	---
4903	&MipsMCRegisterClasses[FGR32RegClassID],	---	4903	&MipsMCRegisterClasses[FGR32RegClassID],	---
4904	FGR32SubClassMask,	---	4904	FGR32SubClassMask,	---
4905	SuperRegIdxSeqs + 9,	---	4905	SuperRegIdxSeqs + 9,	---
4906	LaneBitmask(0x0000000000000001),	---	4906	LaneBitmask(0x0000000000000001),	---
4907	0,	---	4907	0,	---
4908	false,	---	4908	false,	---
4909	0x00, /* TSFlags */	---	4909	0x00, /* TSFlags */	---
4910	false, /* HasDisjunctSubRegs */	---	4910	false, /* HasDisjunctSubRegs */	---
4911	false, /* CoveredBySubRegs */	---	4911	false, /* CoveredBySubRegs */	---
4912	FGR32Superclasses,	---	4912	FGR32Superclasses,	---
4913	FGR32GetRawAllocationOrder	---	4913	FGR32GetRawAllocationOrder	---
4914	};	---	4914	};	---
4915		---	4915		---
4916	extern const TargetRegisterClass FGRCCRegClass = {	---	4916	extern const TargetRegisterClass FGRCCRegClass = {	---
4917	&MipsMCRegisterClasses[FGRCCRegClassID],	---	4917	&MipsMCRegisterClasses[FGRCCRegClassID],	---
4918	FGRCCSubClassMask,	---	4918	FGRCCSubClassMask,	---
4919	SuperRegIdxSeqs + 9,	---	4919	SuperRegIdxSeqs + 9,	---
4920	LaneBitmask(0x0000000000000001),	---	4920	LaneBitmask(0x0000000000000001),	---
4921	0,	---	4921	0,	---
4922	false,	---	4922	false,	---
4923	0x00, /* TSFlags */	---	4923	0x00, /* TSFlags */	---
4924	false, /* HasDisjunctSubRegs */	---	4924	false, /* HasDisjunctSubRegs */	---
4925	false, /* CoveredBySubRegs */	---	4925	false, /* CoveredBySubRegs */	---
4926	FGRCCSuperclasses,	---	4926	FGRCCSuperclasses,	---
4927	nullptr	---	4927	nullptr	---
4928	};	---	4928	};	---
4929		---	4929		---
4930	extern const TargetRegisterClass GPR32RegClass = {	---	4930	extern const TargetRegisterClass GPR32RegClass = {	---
4931	&MipsMCRegisterClasses[GPR32RegClassID],	---	4931	&MipsMCRegisterClasses[GPR32RegClassID],	---
4932	GPR32SubClassMask,	---	4932	GPR32SubClassMask,	---
4933	SuperRegIdxSeqs + 0,	---	4933	SuperRegIdxSeqs + 0,	---
4934	LaneBitmask(0x0000000000000001),	---	4934	LaneBitmask(0x0000000000000001),	---
4935	0,	---	4935	0,	---
4936	false,	---	4936	false,	---
4937	0x00, /* TSFlags */	---	4937	0x00, /* TSFlags */	---
4938	false, /* HasDisjunctSubRegs */	---	4938	false, /* HasDisjunctSubRegs */	---
4939	false, /* CoveredBySubRegs */	---	4939	false, /* CoveredBySubRegs */	---
4940	GPR32Superclasses,	---	4940	GPR32Superclasses,	---
4941	nullptr	---	4941	nullptr	---
4942	};	---	4942	};	---
4943		---	4943		---
4944	extern const TargetRegisterClass HWRegsRegClass = {	---	4944	extern const TargetRegisterClass HWRegsRegClass = {	---
4945	&MipsMCRegisterClasses[HWRegsRegClassID],	---	4945	&MipsMCRegisterClasses[HWRegsRegClassID],	---
4946	HWRegsSubClassMask,	---	4946	HWRegsSubClassMask,	---
4947	SuperRegIdxSeqs + 1,	---	4947	SuperRegIdxSeqs + 1,	---
4948	LaneBitmask(0x0000000000000001),	---	4948	LaneBitmask(0x0000000000000001),	---
4949	0,	---	4949	0,	---
4950	false,	---	4950	false,	---
4951	0x00, /* TSFlags */	---	4951	0x00, /* TSFlags */	---
4952	false, /* HasDisjunctSubRegs */	---	4952	false, /* HasDisjunctSubRegs */	---
4953	false, /* CoveredBySubRegs */	---	4953	false, /* CoveredBySubRegs */	---
4954	NullRegClasses,	---	4954	NullRegClasses,	---
4955	nullptr	---	4955	nullptr	---
4956	};	---	4956	};	---
4957		---	4957		---
4958	extern const TargetRegisterClass MSACtrlRegClass = {	---	4958	extern const TargetRegisterClass MSACtrlRegClass = {	---
4959	&MipsMCRegisterClasses[MSACtrlRegClassID],	---	4959	&MipsMCRegisterClasses[MSACtrlRegClassID],	---
4960	MSACtrlSubClassMask,	---	4960	MSACtrlSubClassMask,	---
4961	SuperRegIdxSeqs + 1,	---	4961	SuperRegIdxSeqs + 1,	---
4962	LaneBitmask(0x0000000000000001),	---	4962	LaneBitmask(0x0000000000000001),	---
4963	0,	---	4963	0,	---
4964	false,	---	4964	false,	---
4965	0x00, /* TSFlags */	---	4965	0x00, /* TSFlags */	---
4966	false, /* HasDisjunctSubRegs */	---	4966	false, /* HasDisjunctSubRegs */	---
4967	false, /* CoveredBySubRegs */	---	4967	false, /* CoveredBySubRegs */	---
4968	NullRegClasses,	---	4968	NullRegClasses,	---
4969	nullptr	---	4969	nullptr	---
4970	};	---	4970	};	---
4971		---	4971		---
4972	extern const TargetRegisterClass GPR32NONZERORegClass = {	---	4972	extern const TargetRegisterClass GPR32NONZERORegClass = {	---
4973	&MipsMCRegisterClasses[GPR32NONZERORegClassID],	---	4973	&MipsMCRegisterClasses[GPR32NONZERORegClassID],	---
4974	GPR32NONZEROSubClassMask,	---	4974	GPR32NONZEROSubClassMask,	---
4975	SuperRegIdxSeqs + 0,	---	4975	SuperRegIdxSeqs + 0,	---
4976	LaneBitmask(0x0000000000000001),	---	4976	LaneBitmask(0x0000000000000001),	---
4977	0,	---	4977	0,	---
4978	false,	---	4978	false,	---
4979	0x00, /* TSFlags */	---	4979	0x00, /* TSFlags */	---
4980	false, /* HasDisjunctSubRegs */	---	4980	false, /* HasDisjunctSubRegs */	---
4981	false, /* CoveredBySubRegs */	---	4981	false, /* CoveredBySubRegs */	---
4982	GPR32NONZEROSuperclasses,	---	4982	GPR32NONZEROSuperclasses,	---
4983	nullptr	---	4983	nullptr	---
4984	};	---	4984	};	---
4985		---	4985		---
4986	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {	---	4986	extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {	---
4987	&MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],	---	4987	&MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],	---
4988	CPU16RegsPlusSPSubClassMask,	---	4988	CPU16RegsPlusSPSubClassMask,	---
4989	SuperRegIdxSeqs + 0,	---	4989	SuperRegIdxSeqs + 0,	---
4990	LaneBitmask(0x0000000000000001),	---	4990	LaneBitmask(0x0000000000000001),	---
4991	0,	---	4991	0,	---
4992	false,	---	4992	false,	---
4993	0x00, /* TSFlags */	---	4993	0x00, /* TSFlags */	---
4994	false, /* HasDisjunctSubRegs */	---	4994	false, /* HasDisjunctSubRegs */	---
4995	false, /* CoveredBySubRegs */	---	4995	false, /* CoveredBySubRegs */	---
4996	CPU16RegsPlusSPSuperclasses,	---	4996	CPU16RegsPlusSPSuperclasses,	---
4997	nullptr	---	4997	nullptr	---
4998	};	---	4998	};	---
4999		---	4999		---
5000	extern const TargetRegisterClass CPU16RegsRegClass = {	---	5000	extern const TargetRegisterClass CPU16RegsRegClass = {	---
5001	&MipsMCRegisterClasses[CPU16RegsRegClassID],	---	5001	&MipsMCRegisterClasses[CPU16RegsRegClassID],	---
5002	CPU16RegsSubClassMask,	---	5002	CPU16RegsSubClassMask,	---
5003	SuperRegIdxSeqs + 0,	---	5003	SuperRegIdxSeqs + 0,	---
5004	LaneBitmask(0x0000000000000001),	---	5004	LaneBitmask(0x0000000000000001),	---
5005	0,	---	5005	0,	---
5006	false,	---	5006	false,	---
5007	0x00, /* TSFlags */	---	5007	0x00, /* TSFlags */	---
5008	false, /* HasDisjunctSubRegs */	---	5008	false, /* HasDisjunctSubRegs */	---
5009	false, /* CoveredBySubRegs */	---	5009	false, /* CoveredBySubRegs */	---
5010	CPU16RegsSuperclasses,	---	5010	CPU16RegsSuperclasses,	---
5011	nullptr	---	5011	nullptr	---
5012	};	---	5012	};	---
5013		---	5013		---
5014	extern const TargetRegisterClass FCCRegClass = {	---	5014	extern const TargetRegisterClass FCCRegClass = {	---
5015	&MipsMCRegisterClasses[FCCRegClassID],	---	5015	&MipsMCRegisterClasses[FCCRegClassID],	---
5016	FCCSubClassMask,	---	5016	FCCSubClassMask,	---
5017	SuperRegIdxSeqs + 1,	---	5017	SuperRegIdxSeqs + 1,	---
5018	LaneBitmask(0x0000000000000001),	---	5018	LaneBitmask(0x0000000000000001),	---
5019	0,	---	5019	0,	---
5020	false,	---	5020	false,	---
5021	0x00, /* TSFlags */	---	5021	0x00, /* TSFlags */	---
5022	false, /* HasDisjunctSubRegs */	---	5022	false, /* HasDisjunctSubRegs */	---
5023	false, /* CoveredBySubRegs */	---	5023	false, /* CoveredBySubRegs */	---
5024	NullRegClasses,	---	5024	NullRegClasses,	---
5025	nullptr	---	5025	nullptr	---
5026	};	---	5026	};	---
5027		---	5027		---
5028	extern const TargetRegisterClass GPRMM16RegClass = {	---	5028	extern const TargetRegisterClass GPRMM16RegClass = {	---
5029	&MipsMCRegisterClasses[GPRMM16RegClassID],	---	5029	&MipsMCRegisterClasses[GPRMM16RegClassID],	---
5030	GPRMM16SubClassMask,	---	5030	GPRMM16SubClassMask,	---
5031	SuperRegIdxSeqs + 0,	---	5031	SuperRegIdxSeqs + 0,	---
5032	LaneBitmask(0x0000000000000001),	---	5032	LaneBitmask(0x0000000000000001),	---
5033	0,	---	5033	0,	---
5034	false,	---	5034	false,	---
5035	0x00, /* TSFlags */	---	5035	0x00, /* TSFlags */	---
5036	false, /* HasDisjunctSubRegs */	---	5036	false, /* HasDisjunctSubRegs */	---
5037	false, /* CoveredBySubRegs */	---	5037	false, /* CoveredBySubRegs */	---
5038	GPRMM16Superclasses,	---	5038	GPRMM16Superclasses,	---
5039	nullptr	---	5039	nullptr	---
5040	};	---	5040	};	---
5041		---	5041		---
5042	extern const TargetRegisterClass GPRMM16MovePRegClass = {	---	5042	extern const TargetRegisterClass GPRMM16MovePRegClass = {	---
5043	&MipsMCRegisterClasses[GPRMM16MovePRegClassID],	---	5043	&MipsMCRegisterClasses[GPRMM16MovePRegClassID],	---
5044	GPRMM16MovePSubClassMask,	---	5044	GPRMM16MovePSubClassMask,	---
5045	SuperRegIdxSeqs + 0,	---	5045	SuperRegIdxSeqs + 0,	---
5046	LaneBitmask(0x0000000000000001),	---	5046	LaneBitmask(0x0000000000000001),	---
5047	0,	---	5047	0,	---
5048	false,	---	5048	false,	---
5049	0x00, /* TSFlags */	---	5049	0x00, /* TSFlags */	---
5050	false, /* HasDisjunctSubRegs */	---	5050	false, /* HasDisjunctSubRegs */	---
5051	false, /* CoveredBySubRegs */	---	5051	false, /* CoveredBySubRegs */	---
5052	GPRMM16MovePSuperclasses,	---	5052	GPRMM16MovePSuperclasses,	---
5053	nullptr	---	5053	nullptr	---
5054	};	---	5054	};	---
5055		---	5055		---
5056	extern const TargetRegisterClass GPRMM16ZeroRegClass = {	---	5056	extern const TargetRegisterClass GPRMM16ZeroRegClass = {	---
5057	&MipsMCRegisterClasses[GPRMM16ZeroRegClassID],	---	5057	&MipsMCRegisterClasses[GPRMM16ZeroRegClassID],	---
5058	GPRMM16ZeroSubClassMask,	---	5058	GPRMM16ZeroSubClassMask,	---
5059	SuperRegIdxSeqs + 0,	---	5059	SuperRegIdxSeqs + 0,	---
5060	LaneBitmask(0x0000000000000001),	---	5060	LaneBitmask(0x0000000000000001),	---
5061	0,	---	5061	0,	---
5062	false,	---	5062	false,	---
5063	0x00, /* TSFlags */	---	5063	0x00, /* TSFlags */	---
5064	false, /* HasDisjunctSubRegs */	---	5064	false, /* HasDisjunctSubRegs */	---
5065	false, /* CoveredBySubRegs */	---	5065	false, /* CoveredBySubRegs */	---
5066	GPRMM16ZeroSuperclasses,	---	5066	GPRMM16ZeroSuperclasses,	---
5067	nullptr	---	5067	nullptr	---
5068	};	---	5068	};	---
5069		---	5069		---
5070	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {	---	5070	extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {	---
5071	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],	---	5071	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],	---
5072	CPU16Regs_and_GPRMM16ZeroSubClassMask,	---	5072	CPU16Regs_and_GPRMM16ZeroSubClassMask,	---
5073	SuperRegIdxSeqs + 0,	---	5073	SuperRegIdxSeqs + 0,	---
5074	LaneBitmask(0x0000000000000001),	---	5074	LaneBitmask(0x0000000000000001),	---
5075	0,	---	5075	0,	---
5076	false,	---	5076	false,	---
5077	0x00, /* TSFlags */	---	5077	0x00, /* TSFlags */	---
5078	false, /* HasDisjunctSubRegs */	---	5078	false, /* HasDisjunctSubRegs */	---
5079	false, /* CoveredBySubRegs */	---	5079	false, /* CoveredBySubRegs */	---
5080	CPU16Regs_and_GPRMM16ZeroSuperclasses,	---	5080	CPU16Regs_and_GPRMM16ZeroSuperclasses,	---
5081	nullptr	---	5081	nullptr	---
5082	};	---	5082	};	---
5083		---	5083		---
5084	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {	---	5084	extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {	---
5085	&MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],	---	5085	&MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],	---
5086	GPR32NONZERO_and_GPRMM16MovePSubClassMask,	---	5086	GPR32NONZERO_and_GPRMM16MovePSubClassMask,	---
5087	SuperRegIdxSeqs + 0,	---	5087	SuperRegIdxSeqs + 0,	---
5088	LaneBitmask(0x0000000000000001),	---	5088	LaneBitmask(0x0000000000000001),	---
5089	0,	---	5089	0,	---
5090	false,	---	5090	false,	---
5091	0x00, /* TSFlags */	---	5091	0x00, /* TSFlags */	---
5092	false, /* HasDisjunctSubRegs */	---	5092	false, /* HasDisjunctSubRegs */	---
5093	false, /* CoveredBySubRegs */	---	5093	false, /* CoveredBySubRegs */	---
5094	GPR32NONZERO_and_GPRMM16MovePSuperclasses,	---	5094	GPR32NONZERO_and_GPRMM16MovePSuperclasses,	---
5095	nullptr	---	5095	nullptr	---
5096	};	---	5096	};	---
5097		---	5097		---
5098	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {	---	5098	extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {	---
5099	&MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],	---	5099	&MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],	---
5100	GPRMM16MovePPairSecondSubClassMask,	---	5100	GPRMM16MovePPairSecondSubClassMask,	---
5101	SuperRegIdxSeqs + 0,	---	5101	SuperRegIdxSeqs + 0,	---
5102	LaneBitmask(0x0000000000000001),	---	5102	LaneBitmask(0x0000000000000001),	---
5103	0,	---	5103	0,	---
5104	false,	---	5104	false,	---
5105	0x00, /* TSFlags */	---	5105	0x00, /* TSFlags */	---
5106	false, /* HasDisjunctSubRegs */	---	5106	false, /* HasDisjunctSubRegs */	---
5107	false, /* CoveredBySubRegs */	---	5107	false, /* CoveredBySubRegs */	---
5108	GPRMM16MovePPairSecondSuperclasses,	---	5108	GPRMM16MovePPairSecondSuperclasses,	---
5109	nullptr	---	5109	nullptr	---
5110	};	---	5110	};	---
5111		---	5111		---
5112	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {	---	5112	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {	---
5113	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],	---	5113	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],	---
5114	CPU16Regs_and_GPRMM16MovePSubClassMask,	---	5114	CPU16Regs_and_GPRMM16MovePSubClassMask,	---
5115	SuperRegIdxSeqs + 0,	---	5115	SuperRegIdxSeqs + 0,	---
5116	LaneBitmask(0x0000000000000001),	---	5116	LaneBitmask(0x0000000000000001),	---
5117	0,	---	5117	0,	---
5118	false,	---	5118	false,	---
5119	0x00, /* TSFlags */	---	5119	0x00, /* TSFlags */	---
5120	false, /* HasDisjunctSubRegs */	---	5120	false, /* HasDisjunctSubRegs */	---
5121	false, /* CoveredBySubRegs */	---	5121	false, /* CoveredBySubRegs */	---
5122	CPU16Regs_and_GPRMM16MovePSuperclasses,	---	5122	CPU16Regs_and_GPRMM16MovePSuperclasses,	---
5123	nullptr	---	5123	nullptr	---
5124	};	---	5124	};	---
5125		---	5125		---
5126	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	---	5126	extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	---
5127	&MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	---	5127	&MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	---
5128	GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	---	5128	GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	---
5129	SuperRegIdxSeqs + 0,	---	5129	SuperRegIdxSeqs + 0,	---
5130	LaneBitmask(0x0000000000000001),	---	5130	LaneBitmask(0x0000000000000001),	---
5131	0,	---	5131	0,	---
5132	false,	---	5132	false,	---
5133	0x00, /* TSFlags */	---	5133	0x00, /* TSFlags */	---
5134	false, /* HasDisjunctSubRegs */	---	5134	false, /* HasDisjunctSubRegs */	---
5135	false, /* CoveredBySubRegs */	---	5135	false, /* CoveredBySubRegs */	---
5136	GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	---	5136	GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	---
5137	nullptr	---	5137	nullptr	---
5138	};	---	5138	};	---
5139		---	5139		---
5140	extern const TargetRegisterClass HI32DSPRegClass = {	---	5140	extern const TargetRegisterClass HI32DSPRegClass = {	---
5141	&MipsMCRegisterClasses[HI32DSPRegClassID],	---	5141	&MipsMCRegisterClasses[HI32DSPRegClassID],	---
5142	HI32DSPSubClassMask,	---	5142	HI32DSPSubClassMask,	---
5143	SuperRegIdxSeqs + 12,	---	5143	SuperRegIdxSeqs + 12,	---
5144	LaneBitmask(0x0000000000000001),	---	5144	LaneBitmask(0x0000000000000001),	---
5145	0,	---	5145	0,	---
5146	false,	---	5146	false,	---
5147	0x00, /* TSFlags */	---	5147	0x00, /* TSFlags */	---
5148	false, /* HasDisjunctSubRegs */	---	5148	false, /* HasDisjunctSubRegs */	---
5149	false, /* CoveredBySubRegs */	---	5149	false, /* CoveredBySubRegs */	---
5150	NullRegClasses,	---	5150	NullRegClasses,	---
5151	nullptr	---	5151	nullptr	---
5152	};	---	5152	};	---
5153		---	5153		---
5154	extern const TargetRegisterClass LO32DSPRegClass = {	---	5154	extern const TargetRegisterClass LO32DSPRegClass = {	---
5155	&MipsMCRegisterClasses[LO32DSPRegClassID],	---	5155	&MipsMCRegisterClasses[LO32DSPRegClassID],	---
5156	LO32DSPSubClassMask,	---	5156	LO32DSPSubClassMask,	---
5157	SuperRegIdxSeqs + 6,	---	5157	SuperRegIdxSeqs + 6,	---
5158	LaneBitmask(0x0000000000000001),	---	5158	LaneBitmask(0x0000000000000001),	---
5159	0,	---	5159	0,	---
5160	false,	---	5160	false,	---
5161	0x00, /* TSFlags */	---	5161	0x00, /* TSFlags */	---
5162	false, /* HasDisjunctSubRegs */	---	5162	false, /* HasDisjunctSubRegs */	---
5163	false, /* CoveredBySubRegs */	---	5163	false, /* CoveredBySubRegs */	---
5164	NullRegClasses,	---	5164	NullRegClasses,	---
5165	nullptr	---	5165	nullptr	---
5166	};	---	5166	};	---
5167		---	5167		---
5168	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	---	5168	extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	---
5169	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	---	5169	&MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	---
5170	CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	---	5170	CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	---
5171	SuperRegIdxSeqs + 0,	---	5171	SuperRegIdxSeqs + 0,	---
5172	LaneBitmask(0x0000000000000001),	---	5172	LaneBitmask(0x0000000000000001),	---
5173	0,	---	5173	0,	---
5174	false,	---	5174	false,	---
5175	0x00, /* TSFlags */	---	5175	0x00, /* TSFlags */	---
5176	false, /* HasDisjunctSubRegs */	---	5176	false, /* HasDisjunctSubRegs */	---
5177	false, /* CoveredBySubRegs */	---	5177	false, /* CoveredBySubRegs */	---
5178	CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	---	5178	CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	---
5179	nullptr	---	5179	nullptr	---
5180	};	---	5180	};	---
5181		---	5181		---
5182	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {	---	5182	extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {	---
5183	&MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],	---	5183	&MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],	---
5184	GPRMM16MovePPairFirstSubClassMask,	---	5184	GPRMM16MovePPairFirstSubClassMask,	---
5185	SuperRegIdxSeqs + 0,	---	5185	SuperRegIdxSeqs + 0,	---
5186	LaneBitmask(0x0000000000000001),	---	5186	LaneBitmask(0x0000000000000001),	---
5187	0,	---	5187	0,	---
5188	false,	---	5188	false,	---
5189	0x00, /* TSFlags */	---	5189	0x00, /* TSFlags */	---
5190	false, /* HasDisjunctSubRegs */	---	5190	false, /* HasDisjunctSubRegs */	---
5191	false, /* CoveredBySubRegs */	---	5191	false, /* CoveredBySubRegs */	---
5192	GPRMM16MovePPairFirstSuperclasses,	---	5192	GPRMM16MovePPairFirstSuperclasses,	---
5193	nullptr	---	5193	nullptr	---
5194	};	---	5194	};	---
5195		---	5195		---
5196	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	---	5196	extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	---
5197	&MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	---	5197	&MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	---
5198	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---	5198	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---
5199	SuperRegIdxSeqs + 0,	---	5199	SuperRegIdxSeqs + 0,	---
5200	LaneBitmask(0x0000000000000001),	---	5200	LaneBitmask(0x0000000000000001),	---
5201	0,	---	5201	0,	---
5202	false,	---	5202	false,	---
5203	0x00, /* TSFlags */	---	5203	0x00, /* TSFlags */	---
5204	false, /* HasDisjunctSubRegs */	---	5204	false, /* HasDisjunctSubRegs */	---
5205	false, /* CoveredBySubRegs */	---	5205	false, /* CoveredBySubRegs */	---
5206	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---	5206	GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---
5207	nullptr	---	5207	nullptr	---
5208	};	---	5208	};	---
5209		---	5209		---
5210	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	---	5210	extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	---
5211	&MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	---	5211	&MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	---
5212	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	---	5212	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	---
5213	SuperRegIdxSeqs + 0,	---	5213	SuperRegIdxSeqs + 0,	---
5214	LaneBitmask(0x0000000000000001),	---	5214	LaneBitmask(0x0000000000000001),	---
5215	0,	---	5215	0,	---
5216	false,	---	5216	false,	---
5217	0x00, /* TSFlags */	---	5217	0x00, /* TSFlags */	---
5218	false, /* HasDisjunctSubRegs */	---	5218	false, /* HasDisjunctSubRegs */	---
5219	false, /* CoveredBySubRegs */	---	5219	false, /* CoveredBySubRegs */	---
5220	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	---	5220	GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	---
5221	nullptr	---	5221	nullptr	---
5222	};	---	5222	};	---
5223		---	5223		---
5224	extern const TargetRegisterClass CPURARegRegClass = {	---	5224	extern const TargetRegisterClass CPURARegRegClass = {	---
5225	&MipsMCRegisterClasses[CPURARegRegClassID],	---	5225	&MipsMCRegisterClasses[CPURARegRegClassID],	---
5226	CPURARegSubClassMask,	---	5226	CPURARegSubClassMask,	---
5227	SuperRegIdxSeqs + 0,	---	5227	SuperRegIdxSeqs + 0,	---
5228	LaneBitmask(0x0000000000000001),	---	5228	LaneBitmask(0x0000000000000001),	---
5229	0,	---	5229	0,	---
5230	false,	---	5230	false,	---
5231	0x00, /* TSFlags */	---	5231	0x00, /* TSFlags */	---
5232	false, /* HasDisjunctSubRegs */	---	5232	false, /* HasDisjunctSubRegs */	---
5233	false, /* CoveredBySubRegs */	---	5233	false, /* CoveredBySubRegs */	---
5234	CPURARegSuperclasses,	---	5234	CPURARegSuperclasses,	---
5235	nullptr	---	5235	nullptr	---
5236	};	---	5236	};	---
5237		---	5237		---
5238	extern const TargetRegisterClass CPUSPRegRegClass = {	---	5238	extern const TargetRegisterClass CPUSPRegRegClass = {	---
5239	&MipsMCRegisterClasses[CPUSPRegRegClassID],	---	5239	&MipsMCRegisterClasses[CPUSPRegRegClassID],	---
5240	CPUSPRegSubClassMask,	---	5240	CPUSPRegSubClassMask,	---
5241	SuperRegIdxSeqs + 0,	---	5241	SuperRegIdxSeqs + 0,	---
5242	LaneBitmask(0x0000000000000001),	---	5242	LaneBitmask(0x0000000000000001),	---
5243	0,	---	5243	0,	---
5244	false,	---	5244	false,	---
5245	0x00, /* TSFlags */	---	5245	0x00, /* TSFlags */	---
5246	false, /* HasDisjunctSubRegs */	---	5246	false, /* HasDisjunctSubRegs */	---
5247	false, /* CoveredBySubRegs */	---	5247	false, /* CoveredBySubRegs */	---
5248	CPUSPRegSuperclasses,	---	5248	CPUSPRegSuperclasses,	---
5249	nullptr	---	5249	nullptr	---
5250	};	---	5250	};	---
5251		---	5251		---
5252	extern const TargetRegisterClass DSPCCRegClass = {	---	5252	extern const TargetRegisterClass DSPCCRegClass = {	---
5253	&MipsMCRegisterClasses[DSPCCRegClassID],	---	5253	&MipsMCRegisterClasses[DSPCCRegClassID],	---
5254	DSPCCSubClassMask,	---	5254	DSPCCSubClassMask,	---
5255	SuperRegIdxSeqs + 1,	---	5255	SuperRegIdxSeqs + 1,	---
5256	LaneBitmask(0x0000000000000001),	---	5256	LaneBitmask(0x0000000000000001),	---
5257	0,	---	5257	0,	---
5258	false,	---	5258	false,	---
5259	0x00, /* TSFlags */	---	5259	0x00, /* TSFlags */	---
5260	false, /* HasDisjunctSubRegs */	---	5260	false, /* HasDisjunctSubRegs */	---
5261	false, /* CoveredBySubRegs */	---	5261	false, /* CoveredBySubRegs */	---
5262	NullRegClasses,	---	5262	NullRegClasses,	---
5263	nullptr	---	5263	nullptr	---
5264	};	---	5264	};	---
5265		---	5265		---
5266	extern const TargetRegisterClass GP32RegClass = {	---	5266	extern const TargetRegisterClass GP32RegClass = {	---
5267	&MipsMCRegisterClasses[GP32RegClassID],	---	5267	&MipsMCRegisterClasses[GP32RegClassID],	---
5268	GP32SubClassMask,	---	5268	GP32SubClassMask,	---
5269	SuperRegIdxSeqs + 0,	---	5269	SuperRegIdxSeqs + 0,	---
5270	LaneBitmask(0x0000000000000001),	---	5270	LaneBitmask(0x0000000000000001),	---
5271	0,	---	5271	0,	---
5272	false,	---	5272	false,	---
5273	0x00, /* TSFlags */	---	5273	0x00, /* TSFlags */	---
5274	false, /* HasDisjunctSubRegs */	---	5274	false, /* HasDisjunctSubRegs */	---
5275	false, /* CoveredBySubRegs */	---	5275	false, /* CoveredBySubRegs */	---
5276	GP32Superclasses,	---	5276	GP32Superclasses,	---
5277	nullptr	---	5277	nullptr	---
5278	};	---	5278	};	---
5279		---	5279		---
5280	extern const TargetRegisterClass GPR32ZERORegClass = {	---	5280	extern const TargetRegisterClass GPR32ZERORegClass = {	---
5281	&MipsMCRegisterClasses[GPR32ZERORegClassID],	---	5281	&MipsMCRegisterClasses[GPR32ZERORegClassID],	---
5282	GPR32ZEROSubClassMask,	---	5282	GPR32ZEROSubClassMask,	---
5283	SuperRegIdxSeqs + 0,	---	5283	SuperRegIdxSeqs + 0,	---
5284	LaneBitmask(0x0000000000000001),	---	5284	LaneBitmask(0x0000000000000001),	---
5285	0,	---	5285	0,	---
5286	false,	---	5286	false,	---
5287	0x00, /* TSFlags */	---	5287	0x00, /* TSFlags */	---
5288	false, /* HasDisjunctSubRegs */	---	5288	false, /* HasDisjunctSubRegs */	---
5289	false, /* CoveredBySubRegs */	---	5289	false, /* CoveredBySubRegs */	---
5290	GPR32ZEROSuperclasses,	---	5290	GPR32ZEROSuperclasses,	---
5291	nullptr	---	5291	nullptr	---
5292	};	---	5292	};	---
5293		---	5293		---
5294	extern const TargetRegisterClass HI32RegClass = {	---	5294	extern const TargetRegisterClass HI32RegClass = {	---
5295	&MipsMCRegisterClasses[HI32RegClassID],	---	5295	&MipsMCRegisterClasses[HI32RegClassID],	---
5296	HI32SubClassMask,	---	5296	HI32SubClassMask,	---
5297	SuperRegIdxSeqs + 12,	---	5297	SuperRegIdxSeqs + 12,	---
5298	LaneBitmask(0x0000000000000001),	---	5298	LaneBitmask(0x0000000000000001),	---
5299	0,	---	5299	0,	---
5300	false,	---	5300	false,	---
5301	0x00, /* TSFlags */	---	5301	0x00, /* TSFlags */	---
5302	false, /* HasDisjunctSubRegs */	---	5302	false, /* HasDisjunctSubRegs */	---
5303	false, /* CoveredBySubRegs */	---	5303	false, /* CoveredBySubRegs */	---
5304	HI32Superclasses,	---	5304	HI32Superclasses,	---
5305	nullptr	---	5305	nullptr	---
5306	};	---	5306	};	---
5307		---	5307		---
5308	extern const TargetRegisterClass LO32RegClass = {	---	5308	extern const TargetRegisterClass LO32RegClass = {	---
5309	&MipsMCRegisterClasses[LO32RegClassID],	---	5309	&MipsMCRegisterClasses[LO32RegClassID],	---
5310	LO32SubClassMask,	---	5310	LO32SubClassMask,	---
5311	SuperRegIdxSeqs + 6,	---	5311	SuperRegIdxSeqs + 6,	---
5312	LaneBitmask(0x0000000000000001),	---	5312	LaneBitmask(0x0000000000000001),	---
5313	0,	---	5313	0,	---
5314	false,	---	5314	false,	---
5315	0x00, /* TSFlags */	---	5315	0x00, /* TSFlags */	---
5316	false, /* HasDisjunctSubRegs */	---	5316	false, /* HasDisjunctSubRegs */	---
5317	false, /* CoveredBySubRegs */	---	5317	false, /* CoveredBySubRegs */	---
5318	LO32Superclasses,	---	5318	LO32Superclasses,	---
5319	nullptr	---	5319	nullptr	---
5320	};	---	5320	};	---
5321		---	5321		---
5322	extern const TargetRegisterClass SP32RegClass = {	---	5322	extern const TargetRegisterClass SP32RegClass = {	---
5323	&MipsMCRegisterClasses[SP32RegClassID],	---	5323	&MipsMCRegisterClasses[SP32RegClassID],	---
5324	SP32SubClassMask,	---	5324	SP32SubClassMask,	---
5325	SuperRegIdxSeqs + 0,	---	5325	SuperRegIdxSeqs + 0,	---
5326	LaneBitmask(0x0000000000000001),	---	5326	LaneBitmask(0x0000000000000001),	---
5327	0,	---	5327	0,	---
5328	false,	---	5328	false,	---
5329	0x00, /* TSFlags */	---	5329	0x00, /* TSFlags */	---
5330	false, /* HasDisjunctSubRegs */	---	5330	false, /* HasDisjunctSubRegs */	---
5331	false, /* CoveredBySubRegs */	---	5331	false, /* CoveredBySubRegs */	---
5332	SP32Superclasses,	---	5332	SP32Superclasses,	---
5333	nullptr	---	5333	nullptr	---
5334	};	---	5334	};	---
5335		---	5335		---
5336	extern const TargetRegisterClass FGR64RegClass = {	---	5336	extern const TargetRegisterClass FGR64RegClass = {	---
5337	&MipsMCRegisterClasses[FGR64RegClassID],	---	5337	&MipsMCRegisterClasses[FGR64RegClassID],	---
5338	FGR64SubClassMask,	---	5338	FGR64SubClassMask,	---
5339	SuperRegIdxSeqs + 2,	---	5339	SuperRegIdxSeqs + 2,	---
5340	LaneBitmask(0x0000000000000041),	---	5340	LaneBitmask(0x0000000000000041),	---
5341	0,	---	5341	0,	---
5342	false,	---	5342	false,	---
5343	0x00, /* TSFlags */	---	5343	0x00, /* TSFlags */	---
5344	true, /* HasDisjunctSubRegs */	---	5344	true, /* HasDisjunctSubRegs */	---
5345	true, /* CoveredBySubRegs */	---	5345	true, /* CoveredBySubRegs */	---
5346	NullRegClasses,	---	5346	NullRegClasses,	---
5347	FGR64GetRawAllocationOrder	---	5347	FGR64GetRawAllocationOrder	---
5348	};	---	5348	};	---
5349		---	5349		---
5350	extern const TargetRegisterClass GPR64RegClass = {	---	5350	extern const TargetRegisterClass GPR64RegClass = {	---
5351	&MipsMCRegisterClasses[GPR64RegClassID],	---	5351	&MipsMCRegisterClasses[GPR64RegClassID],	---
5352	GPR64SubClassMask,	---	5352	GPR64SubClassMask,	---
5353	SuperRegIdxSeqs + 1,	---	5353	SuperRegIdxSeqs + 1,	---
5354	LaneBitmask(0x0000000000000001),	---	5354	LaneBitmask(0x0000000000000001),	---
5355	0,	---	5355	0,	---
5356	false,	---	5356	false,	---
5357	0x00, /* TSFlags */	---	5357	0x00, /* TSFlags */	---
5358	false, /* HasDisjunctSubRegs */	---	5358	false, /* HasDisjunctSubRegs */	---
5359	false, /* CoveredBySubRegs */	---	5359	false, /* CoveredBySubRegs */	---
5360	NullRegClasses,	---	5360	NullRegClasses,	---
5361	nullptr	---	5361	nullptr	---
5362	};	---	5362	};	---
5363		---	5363		---
5364	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {	---	5364	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {	---
5365	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],	---	5365	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],	---
5366	GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,	---	5366	GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,	---
5367	SuperRegIdxSeqs + 1,	---	5367	SuperRegIdxSeqs + 1,	---
5368	LaneBitmask(0x0000000000000001),	---	5368	LaneBitmask(0x0000000000000001),	---
5369	0,	---	5369	0,	---
5370	false,	---	5370	false,	---
5371	0x00, /* TSFlags */	---	5371	0x00, /* TSFlags */	---
5372	false, /* HasDisjunctSubRegs */	---	5372	false, /* HasDisjunctSubRegs */	---
5373	false, /* CoveredBySubRegs */	---	5373	false, /* CoveredBySubRegs */	---
5374	GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,	---	5374	GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,	---
5375	nullptr	---	5375	nullptr	---
5376	};	---	5376	};	---
5377		---	5377		---
5378	extern const TargetRegisterClass AFGR64RegClass = {	---	5378	extern const TargetRegisterClass AFGR64RegClass = {	---
5379	&MipsMCRegisterClasses[AFGR64RegClassID],	---	5379	&MipsMCRegisterClasses[AFGR64RegClassID],	---
5380	AFGR64SubClassMask,	---	5380	AFGR64SubClassMask,	---
5381	SuperRegIdxSeqs + 1,	---	5381	SuperRegIdxSeqs + 1,	---
5382	LaneBitmask(0x0000000000000041),	---	5382	LaneBitmask(0x0000000000000041),	---
5383	0,	---	5383	0,	---
5384	false,	---	5384	false,	---
5385	0x00, /* TSFlags */	---	5385	0x00, /* TSFlags */	---
5386	true, /* HasDisjunctSubRegs */	---	5386	true, /* HasDisjunctSubRegs */	---
5387	true, /* CoveredBySubRegs */	---	5387	true, /* CoveredBySubRegs */	---
5388	NullRegClasses,	---	5388	NullRegClasses,	---
5389	nullptr	---	5389	nullptr	---
5390	};	---	5390	};	---
5391		---	5391		---
5392	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {	---	5392	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {	---
5393	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],	---	5393	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],	---
5394	GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,	---	5394	GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,	---
5395	SuperRegIdxSeqs + 1,	---	5395	SuperRegIdxSeqs + 1,	---
5396	LaneBitmask(0x0000000000000001),	---	5396	LaneBitmask(0x0000000000000001),	---
5397	0,	---	5397	0,	---
5398	false,	---	5398	false,	---
5399	0x00, /* TSFlags */	---	5399	0x00, /* TSFlags */	---
5400	false, /* HasDisjunctSubRegs */	---	5400	false, /* HasDisjunctSubRegs */	---
5401	false, /* CoveredBySubRegs */	---	5401	false, /* CoveredBySubRegs */	---
5402	GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,	---	5402	GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,	---
5403	nullptr	---	5403	nullptr	---
5404	};	---	5404	};	---
5405		---	5405		---
5406	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {	---	5406	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {	---
5407	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],	---	5407	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],	---
5408	GPR64_with_sub_32_in_CPU16RegsSubClassMask,	---	5408	GPR64_with_sub_32_in_CPU16RegsSubClassMask,	---
5409	SuperRegIdxSeqs + 1,	---	5409	SuperRegIdxSeqs + 1,	---
5410	LaneBitmask(0x0000000000000001),	---	5410	LaneBitmask(0x0000000000000001),	---
5411	0,	---	5411	0,	---
5412	false,	---	5412	false,	---
5413	0x00, /* TSFlags */	---	5413	0x00, /* TSFlags */	---
5414	false, /* HasDisjunctSubRegs */	---	5414	false, /* HasDisjunctSubRegs */	---
5415	false, /* CoveredBySubRegs */	---	5415	false, /* CoveredBySubRegs */	---
5416	GPR64_with_sub_32_in_CPU16RegsSuperclasses,	---	5416	GPR64_with_sub_32_in_CPU16RegsSuperclasses,	---
5417	nullptr	---	5417	nullptr	---
5418	};	---	5418	};	---
5419		---	5419		---
5420	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {	---	5420	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {	---
5421	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],	---	5421	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],	---
5422	GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,	---	5422	GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,	---
5423	SuperRegIdxSeqs + 1,	---	5423	SuperRegIdxSeqs + 1,	---
5424	LaneBitmask(0x0000000000000001),	---	5424	LaneBitmask(0x0000000000000001),	---
5425	0,	---	5425	0,	---
5426	false,	---	5426	false,	---
5427	0x00, /* TSFlags */	---	5427	0x00, /* TSFlags */	---
5428	false, /* HasDisjunctSubRegs */	---	5428	false, /* HasDisjunctSubRegs */	---
5429	false, /* CoveredBySubRegs */	---	5429	false, /* CoveredBySubRegs */	---
5430	GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,	---	5430	GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,	---
5431	nullptr	---	5431	nullptr	---
5432	};	---	5432	};	---
5433		---	5433		---
5434	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {	---	5434	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {	---
5435	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],	---	5435	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],	---
5436	GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,	---	5436	GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,	---
5437	SuperRegIdxSeqs + 1,	---	5437	SuperRegIdxSeqs + 1,	---
5438	LaneBitmask(0x0000000000000001),	---	5438	LaneBitmask(0x0000000000000001),	---
5439	0,	---	5439	0,	---
5440	false,	---	5440	false,	---
5441	0x00, /* TSFlags */	---	5441	0x00, /* TSFlags */	---
5442	false, /* HasDisjunctSubRegs */	---	5442	false, /* HasDisjunctSubRegs */	---
5443	false, /* CoveredBySubRegs */	---	5443	false, /* CoveredBySubRegs */	---
5444	GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,	---	5444	GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,	---
5445	nullptr	---	5445	nullptr	---
5446	};	---	5446	};	---
5447		---	5447		---
5448	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {	---	5448	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {	---
5449	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],	---	5449	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],	---
5450	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---	5450	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---
5451	SuperRegIdxSeqs + 1,	---	5451	SuperRegIdxSeqs + 1,	---
5452	LaneBitmask(0x0000000000000001),	---	5452	LaneBitmask(0x0000000000000001),	---
5453	0,	---	5453	0,	---
5454	false,	---	5454	false,	---
5455	0x00, /* TSFlags */	---	5455	0x00, /* TSFlags */	---
5456	false, /* HasDisjunctSubRegs */	---	5456	false, /* HasDisjunctSubRegs */	---
5457	false, /* CoveredBySubRegs */	---	5457	false, /* CoveredBySubRegs */	---
5458	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---	5458	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---
5459	nullptr	---	5459	nullptr	---
5460	};	---	5460	};	---
5461		---	5461		---
5462	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {	---	5462	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {	---
5463	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],	---	5463	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],	---
5464	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,	---	5464	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,	---
5465	SuperRegIdxSeqs + 1,	---	5465	SuperRegIdxSeqs + 1,	---
5466	LaneBitmask(0x0000000000000001),	---	5466	LaneBitmask(0x0000000000000001),	---
5467	0,	---	5467	0,	---
5468	false,	---	5468	false,	---
5469	0x00, /* TSFlags */	---	5469	0x00, /* TSFlags */	---
5470	false, /* HasDisjunctSubRegs */	---	5470	false, /* HasDisjunctSubRegs */	---
5471	false, /* CoveredBySubRegs */	---	5471	false, /* CoveredBySubRegs */	---
5472	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,	---	5472	GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,	---
5473	nullptr	---	5473	nullptr	---
5474	};	---	5474	};	---
5475		---	5475		---
5476	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {	---	5476	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {	---
5477	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],	---	5477	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],	---
5478	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,	---	5478	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,	---
5479	SuperRegIdxSeqs + 1,	---	5479	SuperRegIdxSeqs + 1,	---
5480	LaneBitmask(0x0000000000000001),	---	5480	LaneBitmask(0x0000000000000001),	---
5481	0,	---	5481	0,	---
5482	false,	---	5482	false,	---
5483	0x00, /* TSFlags */	---	5483	0x00, /* TSFlags */	---
5484	false, /* HasDisjunctSubRegs */	---	5484	false, /* HasDisjunctSubRegs */	---
5485	false, /* CoveredBySubRegs */	---	5485	false, /* CoveredBySubRegs */	---
5486	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,	---	5486	GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,	---
5487	nullptr	---	5487	nullptr	---
5488	};	---	5488	};	---
5489		---	5489		---
5490	extern const TargetRegisterClass ACC64DSPRegClass = {	---	5490	extern const TargetRegisterClass ACC64DSPRegClass = {	---
5491	&MipsMCRegisterClasses[ACC64DSPRegClassID],	---	5491	&MipsMCRegisterClasses[ACC64DSPRegClassID],	---
5492	ACC64DSPSubClassMask,	---	5492	ACC64DSPSubClassMask,	---
5493	SuperRegIdxSeqs + 16,	---	5493	SuperRegIdxSeqs + 16,	---
5494	LaneBitmask(0x0000000000000041),	---	5494	LaneBitmask(0x0000000000000041),	---
5495	0,	---	5495	0,	---
5496	false,	---	5496	false,	---
5497	0x00, /* TSFlags */	---	5497	0x00, /* TSFlags */	---
5498	true, /* HasDisjunctSubRegs */	---	5498	true, /* HasDisjunctSubRegs */	---
5499	true, /* CoveredBySubRegs */	---	5499	true, /* CoveredBySubRegs */	---
5500	NullRegClasses,	---	5500	NullRegClasses,	---
5501	nullptr	---	5501	nullptr	---
5502	};	---	5502	};	---
5503		---	5503		---
5504	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {	---	5504	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {	---
5505	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],	---	5505	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],	---
5506	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,	---	5506	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,	---
5507	SuperRegIdxSeqs + 1,	---	5507	SuperRegIdxSeqs + 1,	---
5508	LaneBitmask(0x0000000000000001),	---	5508	LaneBitmask(0x0000000000000001),	---
5509	0,	---	5509	0,	---
5510	false,	---	5510	false,	---
5511	0x00, /* TSFlags */	---	5511	0x00, /* TSFlags */	---
5512	false, /* HasDisjunctSubRegs */	---	5512	false, /* HasDisjunctSubRegs */	---
5513	false, /* CoveredBySubRegs */	---	5513	false, /* CoveredBySubRegs */	---
5514	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,	---	5514	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,	---
5515	nullptr	---	5515	nullptr	---
5516	};	---	5516	};	---
5517		---	5517		---
5518	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	---	5518	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {	---
5519	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	---	5519	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],	---
5520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	---	5520	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,	---
5521	SuperRegIdxSeqs + 1,	---	5521	SuperRegIdxSeqs + 1,	---
5522	LaneBitmask(0x0000000000000001),	---	5522	LaneBitmask(0x0000000000000001),	---
5523	0,	---	5523	0,	---
5524	false,	---	5524	false,	---
5525	0x00, /* TSFlags */	---	5525	0x00, /* TSFlags */	---
5526	false, /* HasDisjunctSubRegs */	---	5526	false, /* HasDisjunctSubRegs */	---
5527	false, /* CoveredBySubRegs */	---	5527	false, /* CoveredBySubRegs */	---
5528	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	---	5528	GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,	---
5529	nullptr	---	5529	nullptr	---
5530	};	---	5530	};	---
5531		---	5531		---
5532	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	---	5532	extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {	---
5533	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	---	5533	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],	---
5534	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	---	5534	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,	---
5535	SuperRegIdxSeqs + 1,	---	5535	SuperRegIdxSeqs + 1,	---
5536	LaneBitmask(0x0000000000000001),	---	5536	LaneBitmask(0x0000000000000001),	---
5537	0,	---	5537	0,	---
5538	false,	---	5538	false,	---
5539	0x00, /* TSFlags */	---	5539	0x00, /* TSFlags */	---
5540	false, /* HasDisjunctSubRegs */	---	5540	false, /* HasDisjunctSubRegs */	---
5541	false, /* CoveredBySubRegs */	---	5541	false, /* CoveredBySubRegs */	---
5542	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	---	5542	GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,	---
5543	nullptr	---	5543	nullptr	---
5544	};	---	5544	};	---
5545		---	5545		---
5546	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {	---	5546	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {	---
5547	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],	---	5547	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],	---
5548	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,	---	5548	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,	---
5549	SuperRegIdxSeqs + 1,	---	5549	SuperRegIdxSeqs + 1,	---
5550	LaneBitmask(0x0000000000000001),	---	5550	LaneBitmask(0x0000000000000001),	---
5551	0,	---	5551	0,	---
5552	false,	---	5552	false,	---
5553	0x00, /* TSFlags */	---	5553	0x00, /* TSFlags */	---
5554	false, /* HasDisjunctSubRegs */	---	5554	false, /* HasDisjunctSubRegs */	---
5555	false, /* CoveredBySubRegs */	---	5555	false, /* CoveredBySubRegs */	---
5556	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,	---	5556	GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,	---
5557	nullptr	---	5557	nullptr	---
5558	};	---	5558	};	---
5559		---	5559		---
5560	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	---	5560	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {	---
5561	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	---	5561	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],	---
5562	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---	5562	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,	---
5563	SuperRegIdxSeqs + 1,	---	5563	SuperRegIdxSeqs + 1,	---
5564	LaneBitmask(0x0000000000000001),	---	5564	LaneBitmask(0x0000000000000001),	---
5565	0,	---	5565	0,	---
5566	false,	---	5566	false,	---
5567	0x00, /* TSFlags */	---	5567	0x00, /* TSFlags */	---
5568	false, /* HasDisjunctSubRegs */	---	5568	false, /* HasDisjunctSubRegs */	---
5569	false, /* CoveredBySubRegs */	---	5569	false, /* CoveredBySubRegs */	---
5570	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---	5570	GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,	---
5571	nullptr	---	5571	nullptr	---
5572	};	---	5572	};	---
5573		---	5573		---
5574	extern const TargetRegisterClass OCTEON_MPLRegClass = {	---	5574	extern const TargetRegisterClass OCTEON_MPLRegClass = {	---
5575	&MipsMCRegisterClasses[OCTEON_MPLRegClassID],	---	5575	&MipsMCRegisterClasses[OCTEON_MPLRegClassID],	---
5576	OCTEON_MPLSubClassMask,	---	5576	OCTEON_MPLSubClassMask,	---
5577	SuperRegIdxSeqs + 1,	---	5577	SuperRegIdxSeqs + 1,	---
5578	LaneBitmask(0x0000000000000001),	---	5578	LaneBitmask(0x0000000000000001),	---
5579	0,	---	5579	0,	---
5580	false,	---	5580	false,	---
5581	0x00, /* TSFlags */	---	5581	0x00, /* TSFlags */	---
5582	false, /* HasDisjunctSubRegs */	---	5582	false, /* HasDisjunctSubRegs */	---
5583	false, /* CoveredBySubRegs */	---	5583	false, /* CoveredBySubRegs */	---
5584	NullRegClasses,	---	5584	NullRegClasses,	---
5585	nullptr	---	5585	nullptr	---
5586	};	---	5586	};	---
5587		---	5587		---
5588	extern const TargetRegisterClass OCTEON_PRegClass = {	---	5588	extern const TargetRegisterClass OCTEON_PRegClass = {	---
5589	&MipsMCRegisterClasses[OCTEON_PRegClassID],	---	5589	&MipsMCRegisterClasses[OCTEON_PRegClassID],	---
5590	OCTEON_PSubClassMask,	---	5590	OCTEON_PSubClassMask,	---
5591	SuperRegIdxSeqs + 1,	---	5591	SuperRegIdxSeqs + 1,	---
5592	LaneBitmask(0x0000000000000001),	---	5592	LaneBitmask(0x0000000000000001),	---
5593	0,	---	5593	0,	---
5594	false,	---	5594	false,	---
5595	0x00, /* TSFlags */	---	5595	0x00, /* TSFlags */	---
5596	false, /* HasDisjunctSubRegs */	---	5596	false, /* HasDisjunctSubRegs */	---
5597	false, /* CoveredBySubRegs */	---	5597	false, /* CoveredBySubRegs */	---
5598	NullRegClasses,	---	5598	NullRegClasses,	---
5599	nullptr	---	5599	nullptr	---
5600	};	---	5600	};	---
5601		---	5601		---
5602	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	---	5602	extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {	---
5603	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	---	5603	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],	---
5604	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	---	5604	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,	---
5605	SuperRegIdxSeqs + 1,	---	5605	SuperRegIdxSeqs + 1,	---
5606	LaneBitmask(0x0000000000000001),	---	5606	LaneBitmask(0x0000000000000001),	---
5607	0,	---	5607	0,	---
5608	false,	---	5608	false,	---
5609	0x00, /* TSFlags */	---	5609	0x00, /* TSFlags */	---
5610	false, /* HasDisjunctSubRegs */	---	5610	false, /* HasDisjunctSubRegs */	---
5611	false, /* CoveredBySubRegs */	---	5611	false, /* CoveredBySubRegs */	---
5612	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	---	5612	GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,	---
5613	nullptr	---	5613	nullptr	---
5614	};	---	5614	};	---
5615		---	5615		---
5616	extern const TargetRegisterClass ACC64RegClass = {	---	5616	extern const TargetRegisterClass ACC64RegClass = {	---
5617	&MipsMCRegisterClasses[ACC64RegClassID],	---	5617	&MipsMCRegisterClasses[ACC64RegClassID],	---
5618	ACC64SubClassMask,	---	5618	ACC64SubClassMask,	---
5619	SuperRegIdxSeqs + 16,	---	5619	SuperRegIdxSeqs + 16,	---
5620	LaneBitmask(0x0000000000000041),	---	5620	LaneBitmask(0x0000000000000041),	---
5621	0,	---	5621	0,	---
5622	false,	---	5622	false,	---
5623	0x00, /* TSFlags */	---	5623	0x00, /* TSFlags */	---
5624	true, /* HasDisjunctSubRegs */	---	5624	true, /* HasDisjunctSubRegs */	---
5625	true, /* CoveredBySubRegs */	---	5625	true, /* CoveredBySubRegs */	---
5626	ACC64Superclasses,	---	5626	ACC64Superclasses,	---
5627	nullptr	---	5627	nullptr	---
5628	};	---	5628	};	---
5629		---	5629		---
5630	extern const TargetRegisterClass GP64RegClass = {	---	5630	extern const TargetRegisterClass GP64RegClass = {	---
5631	&MipsMCRegisterClasses[GP64RegClassID],	---	5631	&MipsMCRegisterClasses[GP64RegClassID],	---
5632	GP64SubClassMask,	---	5632	GP64SubClassMask,	---
5633	SuperRegIdxSeqs + 1,	---	5633	SuperRegIdxSeqs + 1,	---
5634	LaneBitmask(0x0000000000000001),	---	5634	LaneBitmask(0x0000000000000001),	---
5635	0,	---	5635	0,	---
5636	false,	---	5636	false,	---
5637	0x00, /* TSFlags */	---	5637	0x00, /* TSFlags */	---
5638	false, /* HasDisjunctSubRegs */	---	5638	false, /* HasDisjunctSubRegs */	---
5639	false, /* CoveredBySubRegs */	---	5639	false, /* CoveredBySubRegs */	---
5640	GP64Superclasses,	---	5640	GP64Superclasses,	---
5641	nullptr	---	5641	nullptr	---
5642	};	---	5642	};	---
5643		---	5643		---
5644	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {	---	5644	extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {	---
5645	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],	---	5645	&MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],	---
5646	GPR64_with_sub_32_in_CPURARegSubClassMask,	---	5646	GPR64_with_sub_32_in_CPURARegSubClassMask,	---
5647	SuperRegIdxSeqs + 1,	---	5647	SuperRegIdxSeqs + 1,	---
5648	LaneBitmask(0x0000000000000001),	---	5648	LaneBitmask(0x0000000000000001),	---
5649	0,	---	5649	0,	---
5650	false,	---	5650	false,	---
5651	0x00, /* TSFlags */	---	5651	0x00, /* TSFlags */	---
5652	false, /* HasDisjunctSubRegs */	---	5652	false, /* HasDisjunctSubRegs */	---
5653	false, /* CoveredBySubRegs */	---	5653	false, /* CoveredBySubRegs */	---
5654	GPR64_with_sub_32_in_CPURARegSuperclasses,	---	5654	GPR64_with_sub_32_in_CPURARegSuperclasses,	---
5655	nullptr	---	5655	nullptr	---
5656	};	---	5656	};	---
5657		---	5657		---
5658	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {	---	5658	extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {	---
5659	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],	---	5659	&MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],	---
5660	GPR64_with_sub_32_in_GPR32ZEROSubClassMask,	---	5660	GPR64_with_sub_32_in_GPR32ZEROSubClassMask,	---
5661	SuperRegIdxSeqs + 1,	---	5661	SuperRegIdxSeqs + 1,	---
5662	LaneBitmask(0x0000000000000001),	---	5662	LaneBitmask(0x0000000000000001),	---
5663	0,	---	5663	0,	---
5664	false,	---	5664	false,	---
5665	0x00, /* TSFlags */	---	5665	0x00, /* TSFlags */	---
5666	false, /* HasDisjunctSubRegs */	---	5666	false, /* HasDisjunctSubRegs */	---
5667	false, /* CoveredBySubRegs */	---	5667	false, /* CoveredBySubRegs */	---
5668	GPR64_with_sub_32_in_GPR32ZEROSuperclasses,	---	5668	GPR64_with_sub_32_in_GPR32ZEROSuperclasses,	---
5669	nullptr	---	5669	nullptr	---
5670	};	---	5670	};	---
5671		---	5671		---
5672	extern const TargetRegisterClass HI64RegClass = {	---	5672	extern const TargetRegisterClass HI64RegClass = {	---
5673	&MipsMCRegisterClasses[HI64RegClassID],	---	5673	&MipsMCRegisterClasses[HI64RegClassID],	---
5674	HI64SubClassMask,	---	5674	HI64SubClassMask,	---
5675	SuperRegIdxSeqs + 4,	---	5675	SuperRegIdxSeqs + 4,	---
5676	LaneBitmask(0x0000000000000001),	---	5676	LaneBitmask(0x0000000000000001),	---
5677	0,	---	5677	0,	---
5678	false,	---	5678	false,	---
5679	0x00, /* TSFlags */	---	5679	0x00, /* TSFlags */	---
5680	false, /* HasDisjunctSubRegs */	---	5680	false, /* HasDisjunctSubRegs */	---
5681	false, /* CoveredBySubRegs */	---	5681	false, /* CoveredBySubRegs */	---
5682	NullRegClasses,	---	5682	NullRegClasses,	---
5683	nullptr	---	5683	nullptr	---
5684	};	---	5684	};	---
5685		---	5685		---
5686	extern const TargetRegisterClass LO64RegClass = {	---	5686	extern const TargetRegisterClass LO64RegClass = {	---
5687	&MipsMCRegisterClasses[LO64RegClassID],	---	5687	&MipsMCRegisterClasses[LO64RegClassID],	---
5688	LO64SubClassMask,	---	5688	LO64SubClassMask,	---
5689	SuperRegIdxSeqs + 7,	---	5689	SuperRegIdxSeqs + 7,	---
5690	LaneBitmask(0x0000000000000001),	---	5690	LaneBitmask(0x0000000000000001),	---
5691	0,	---	5691	0,	---
5692	false,	---	5692	false,	---
5693	0x00, /* TSFlags */	---	5693	0x00, /* TSFlags */	---
5694	false, /* HasDisjunctSubRegs */	---	5694	false, /* HasDisjunctSubRegs */	---
5695	false, /* CoveredBySubRegs */	---	5695	false, /* CoveredBySubRegs */	---
5696	NullRegClasses,	---	5696	NullRegClasses,	---
5697	nullptr	---	5697	nullptr	---
5698	};	---	5698	};	---
5699		---	5699		---
5700	extern const TargetRegisterClass SP64RegClass = {	---	5700	extern const TargetRegisterClass SP64RegClass = {	---
5701	&MipsMCRegisterClasses[SP64RegClassID],	---	5701	&MipsMCRegisterClasses[SP64RegClassID],	---
5702	SP64SubClassMask,	---	5702	SP64SubClassMask,	---
5703	SuperRegIdxSeqs + 1,	---	5703	SuperRegIdxSeqs + 1,	---
5704	LaneBitmask(0x0000000000000001),	---	5704	LaneBitmask(0x0000000000000001),	---
5705	0,	---	5705	0,	---
5706	false,	---	5706	false,	---
5707	0x00, /* TSFlags */	---	5707	0x00, /* TSFlags */	---
5708	false, /* HasDisjunctSubRegs */	---	5708	false, /* HasDisjunctSubRegs */	---
5709	false, /* CoveredBySubRegs */	---	5709	false, /* CoveredBySubRegs */	---
5710	SP64Superclasses,	---	5710	SP64Superclasses,	---
5711	nullptr	---	5711	nullptr	---
5712	};	---	5712	};	---
5713		---	5713		---
5714	extern const TargetRegisterClass MSA128BRegClass = {	---	5714	extern const TargetRegisterClass MSA128BRegClass = {	---
5715	&MipsMCRegisterClasses[MSA128BRegClassID],	---	5715	&MipsMCRegisterClasses[MSA128BRegClassID],	---
5716	MSA128BSubClassMask,	---	5716	MSA128BSubClassMask,	---
5717	SuperRegIdxSeqs + 1,	---	5717	SuperRegIdxSeqs + 1,	---
5718	LaneBitmask(0x0000000000000041),	---	5718	LaneBitmask(0x0000000000000041),	---
5719	0,	---	5719	0,	---
5720	false,	---	5720	false,	---
5721	0x00, /* TSFlags */	---	5721	0x00, /* TSFlags */	---
5722	true, /* HasDisjunctSubRegs */	---	5722	true, /* HasDisjunctSubRegs */	---
5723	false, /* CoveredBySubRegs */	---	5723	false, /* CoveredBySubRegs */	---
5724	MSA128BSuperclasses,	---	5724	MSA128BSuperclasses,	---
5725	nullptr	---	5725	nullptr	---
5726	};	---	5726	};	---
5727		---	5727		---
5728	extern const TargetRegisterClass MSA128DRegClass = {	---	5728	extern const TargetRegisterClass MSA128DRegClass = {	---
5729	&MipsMCRegisterClasses[MSA128DRegClassID],	---	5729	&MipsMCRegisterClasses[MSA128DRegClassID],	---
5730	MSA128DSubClassMask,	---	5730	MSA128DSubClassMask,	---
5731	SuperRegIdxSeqs + 1,	---	5731	SuperRegIdxSeqs + 1,	---
5732	LaneBitmask(0x0000000000000041),	---	5732	LaneBitmask(0x0000000000000041),	---
5733	0,	---	5733	0,	---
5734	false,	---	5734	false,	---
5735	0x00, /* TSFlags */	---	5735	0x00, /* TSFlags */	---
5736	true, /* HasDisjunctSubRegs */	---	5736	true, /* HasDisjunctSubRegs */	---
5737	false, /* CoveredBySubRegs */	---	5737	false, /* CoveredBySubRegs */	---
5738	MSA128DSuperclasses,	---	5738	MSA128DSuperclasses,	---
5739	nullptr	---	5739	nullptr	---
5740	};	---	5740	};	---
5741		---	5741		---
5742	extern const TargetRegisterClass MSA128HRegClass = {	---	5742	extern const TargetRegisterClass MSA128HRegClass = {	---
5743	&MipsMCRegisterClasses[MSA128HRegClassID],	---	5743	&MipsMCRegisterClasses[MSA128HRegClassID],	---
5744	MSA128HSubClassMask,	---	5744	MSA128HSubClassMask,	---
5745	SuperRegIdxSeqs + 1,	---	5745	SuperRegIdxSeqs + 1,	---
5746	LaneBitmask(0x0000000000000041),	---	5746	LaneBitmask(0x0000000000000041),	---
5747	0,	---	5747	0,	---
5748	false,	---	5748	false,	---
5749	0x00, /* TSFlags */	---	5749	0x00, /* TSFlags */	---
5750	true, /* HasDisjunctSubRegs */	---	5750	true, /* HasDisjunctSubRegs */	---
5751	false, /* CoveredBySubRegs */	---	5751	false, /* CoveredBySubRegs */	---
5752	MSA128HSuperclasses,	---	5752	MSA128HSuperclasses,	---
5753	nullptr	---	5753	nullptr	---
5754	};	---	5754	};	---
5755		---	5755		---
5756	extern const TargetRegisterClass MSA128WRegClass = {	---	5756	extern const TargetRegisterClass MSA128WRegClass = {	---
5757	&MipsMCRegisterClasses[MSA128WRegClassID],	---	5757	&MipsMCRegisterClasses[MSA128WRegClassID],	---
5758	MSA128WSubClassMask,	---	5758	MSA128WSubClassMask,	---
5759	SuperRegIdxSeqs + 1,	---	5759	SuperRegIdxSeqs + 1,	---
5760	LaneBitmask(0x0000000000000041),	---	5760	LaneBitmask(0x0000000000000041),	---
5761	0,	---	5761	0,	---
5762	false,	---	5762	false,	---
5763	0x00, /* TSFlags */	---	5763	0x00, /* TSFlags */	---
5764	true, /* HasDisjunctSubRegs */	---	5764	true, /* HasDisjunctSubRegs */	---
5765	false, /* CoveredBySubRegs */	---	5765	false, /* CoveredBySubRegs */	---
5766	MSA128WSuperclasses,	---	5766	MSA128WSuperclasses,	---
5767	nullptr	---	5767	nullptr	---
5768	};	---	5768	};	---
5769		---	5769		---
5770	extern const TargetRegisterClass MSA128WEvensRegClass = {	---	5770	extern const TargetRegisterClass MSA128WEvensRegClass = {	---
5771	&MipsMCRegisterClasses[MSA128WEvensRegClassID],	---	5771	&MipsMCRegisterClasses[MSA128WEvensRegClassID],	---
5772	MSA128WEvensSubClassMask,	---	5772	MSA128WEvensSubClassMask,	---
5773	SuperRegIdxSeqs + 1,	---	5773	SuperRegIdxSeqs + 1,	---
5774	LaneBitmask(0x0000000000000041),	---	5774	LaneBitmask(0x0000000000000041),	---
5775	0,	---	5775	0,	---
5776	false,	---	5776	false,	---
5777	0x00, /* TSFlags */	---	5777	0x00, /* TSFlags */	---
5778	true, /* HasDisjunctSubRegs */	---	5778	true, /* HasDisjunctSubRegs */	---
5779	false, /* CoveredBySubRegs */	---	5779	false, /* CoveredBySubRegs */	---
5780	MSA128WEvensSuperclasses,	---	5780	MSA128WEvensSuperclasses,	---
5781	nullptr	---	5781	nullptr	---
5782	};	---	5782	};	---
5783		---	5783		---
5784	extern const TargetRegisterClass ACC128RegClass = {	---	5784	extern const TargetRegisterClass ACC128RegClass = {	---
5785	&MipsMCRegisterClasses[ACC128RegClassID],	---	5785	&MipsMCRegisterClasses[ACC128RegClassID],	---
5786	ACC128SubClassMask,	---	5786	ACC128SubClassMask,	---
5787	SuperRegIdxSeqs + 1,	---	5787	SuperRegIdxSeqs + 1,	---
5788	LaneBitmask(0x0000000000000041),	---	5788	LaneBitmask(0x0000000000000041),	---
5789	0,	---	5789	0,	---
5790	false,	---	5790	false,	---
5791	0x00, /* TSFlags */	---	5791	0x00, /* TSFlags */	---
5792	true, /* HasDisjunctSubRegs */	---	5792	true, /* HasDisjunctSubRegs */	---
5793	true, /* CoveredBySubRegs */	---	5793	true, /* CoveredBySubRegs */	---
5794	NullRegClasses,	---	5794	NullRegClasses,	---
5795	nullptr	---	5795	nullptr	---
5796	};	---	5796	};	---
5797		---	5797		---
5798	} // end namespace Mips	---	5798	} // end namespace Mips	---
5799		---	5799		---
5800	namespace {	---	5800	namespace {	---
5801	const TargetRegisterClass *const RegisterClasses[] = {	---	5801	const TargetRegisterClass *const RegisterClasses[] = {	---
5802	&Mips::MSA128F16RegClass,	---	5802	&Mips::MSA128F16RegClass,	---
5803	&Mips::CCRRegClass,	---	5803	&Mips::CCRRegClass,	---
5804	&Mips::COP0RegClass,	---	5804	&Mips::COP0RegClass,	---
5805	&Mips::COP2RegClass,	---	5805	&Mips::COP2RegClass,	---
5806	&Mips::COP3RegClass,	---	5806	&Mips::COP3RegClass,	---
5807	&Mips::DSPRRegClass,	---	5807	&Mips::DSPRRegClass,	---
5808	&Mips::FGR32RegClass,	---	5808	&Mips::FGR32RegClass,	---
5809	&Mips::FGRCCRegClass,	---	5809	&Mips::FGRCCRegClass,	---
5810	&Mips::GPR32RegClass,	---	5810	&Mips::GPR32RegClass,	---
5811	&Mips::HWRegsRegClass,	---	5811	&Mips::HWRegsRegClass,	---
5812	&Mips::MSACtrlRegClass,	---	5812	&Mips::MSACtrlRegClass,	---
5813	&Mips::GPR32NONZERORegClass,	---	5813	&Mips::GPR32NONZERORegClass,	---
5814	&Mips::CPU16RegsPlusSPRegClass,	---	5814	&Mips::CPU16RegsPlusSPRegClass,	---
5815	&Mips::CPU16RegsRegClass,	---	5815	&Mips::CPU16RegsRegClass,	---
5816	&Mips::FCCRegClass,	---	5816	&Mips::FCCRegClass,	---
5817	&Mips::GPRMM16RegClass,	---	5817	&Mips::GPRMM16RegClass,	---
5818	&Mips::GPRMM16MovePRegClass,	---	5818	&Mips::GPRMM16MovePRegClass,	---
5819	&Mips::GPRMM16ZeroRegClass,	---	5819	&Mips::GPRMM16ZeroRegClass,	---
5820	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---	5820	&Mips::CPU16Regs_and_GPRMM16ZeroRegClass,	---
5821	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---	5821	&Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,	---
5822	&Mips::GPRMM16MovePPairSecondRegClass,	---	5822	&Mips::GPRMM16MovePPairSecondRegClass,	---
5823	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	---	5823	&Mips::CPU16Regs_and_GPRMM16MovePRegClass,	---
5824	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	5824	&Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
5825	&Mips::HI32DSPRegClass,	---	5825	&Mips::HI32DSPRegClass,	---
5826	&Mips::LO32DSPRegClass,	---	5826	&Mips::LO32DSPRegClass,	---
5827	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---	5827	&Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---
5828	&Mips::GPRMM16MovePPairFirstRegClass,	---	5828	&Mips::GPRMM16MovePPairFirstRegClass,	---
5829	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	---	5829	&Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	---
5830	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	---	5830	&Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	---
5831	&Mips::CPURARegRegClass,	---	5831	&Mips::CPURARegRegClass,	---
5832	&Mips::CPUSPRegRegClass,	---	5832	&Mips::CPUSPRegRegClass,	---
5833	&Mips::DSPCCRegClass,	---	5833	&Mips::DSPCCRegClass,	---
5834	&Mips::GP32RegClass,	---	5834	&Mips::GP32RegClass,	---
5835	&Mips::GPR32ZERORegClass,	---	5835	&Mips::GPR32ZERORegClass,	---
5836	&Mips::HI32RegClass,	---	5836	&Mips::HI32RegClass,	---
5837	&Mips::LO32RegClass,	---	5837	&Mips::LO32RegClass,	---
5838	&Mips::SP32RegClass,	---	5838	&Mips::SP32RegClass,	---
5839	&Mips::FGR64RegClass,	---	5839	&Mips::FGR64RegClass,	---
5840	&Mips::GPR64RegClass,	---	5840	&Mips::GPR64RegClass,	---
5841	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---	5841	&Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,	---
5842	&Mips::AFGR64RegClass,	---	5842	&Mips::AFGR64RegClass,	---
5843	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---	5843	&Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,	---
5844	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---	5844	&Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,	---
5845	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---	5845	&Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,	---
5846	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---	5846	&Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,	---
5847	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---	5847	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,	---
5848	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---	5848	&Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,	---
5849	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---	5849	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,	---
5850	&Mips::ACC64DSPRegClass,	---	5850	&Mips::ACC64DSPRegClass,	---
5851	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	---	5851	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,	---
5852	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---	5852	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,	---
5853	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---	5853	&Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,	---
5854	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	---	5854	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,	---
5855	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	---	5855	&Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,	---
5856	&Mips::OCTEON_MPLRegClass,	---	5856	&Mips::OCTEON_MPLRegClass,	---
5857	&Mips::OCTEON_PRegClass,	---	5857	&Mips::OCTEON_PRegClass,	---
5858	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	---	5858	&Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,	---
5859	&Mips::ACC64RegClass,	---	5859	&Mips::ACC64RegClass,	---
5860	&Mips::GP64RegClass,	---	5860	&Mips::GP64RegClass,	---
5861	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,	---	5861	&Mips::GPR64_with_sub_32_in_CPURARegRegClass,	---
5862	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,	---	5862	&Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,	---
5863	&Mips::HI64RegClass,	---	5863	&Mips::HI64RegClass,	---
5864	&Mips::LO64RegClass,	---	5864	&Mips::LO64RegClass,	---
5865	&Mips::SP64RegClass,	---	5865	&Mips::SP64RegClass,	---
5866	&Mips::MSA128BRegClass,	---	5866	&Mips::MSA128BRegClass,	---
5867	&Mips::MSA128DRegClass,	---	5867	&Mips::MSA128DRegClass,	---
5868	&Mips::MSA128HRegClass,	---	5868	&Mips::MSA128HRegClass,	---
5869	&Mips::MSA128WRegClass,	---	5869	&Mips::MSA128WRegClass,	---
5870	&Mips::MSA128WEvensRegClass,	---	5870	&Mips::MSA128WEvensRegClass,	---
5871	&Mips::ACC128RegClass,	---	5871	&Mips::ACC128RegClass,	---
5872	};	---	5872	};	---
5873	} // end anonymous namespace	---	5873	} // end anonymous namespace	---
5874		---	5874		---
5875	static const uint8_t CostPerUseTable[] = {	---	5875	static const uint8_t CostPerUseTable[] = {	---
5876	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };	---	5876	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };	---
5877		---	5877		---
5878		---	5878		---
5879	static const bool InAllocatableClassTable[] = {	---	5879	static const bool InAllocatableClassTable[] = {	---
5880	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };	---	5880	false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };	---
5881		---	5881		---
5882		---	5882		---
5883	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors	---	5883	static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors	---
5884	CostPerUseTable, 1, InAllocatableClassTable};	---	5884	CostPerUseTable, 1, InAllocatableClassTable};	---
5885		---	5885		---
5886	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {	0	5886	unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {	0
5887	static const uint8_t RowMap[11] = {	---	5887	static const uint8_t RowMap[11] = {	---
5888	0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,	---	5888	0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,	---
5889	};	---	5889	};	---
5890	static const uint8_t Rows[2][11] = {	---	5890	static const uint8_t Rows[2][11] = {	---
5891	{ Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },	---	5891	{ Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },	---
5892	{ Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },	---	5892	{ Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },	---
5893	};	---	5893	};	---
5894		---	5894		---
5895	--IdxA; assert(IdxA < 11); (void) IdxA;	0	5895	--IdxA; assert(IdxA < 11); (void) IdxA;	0
5896	--IdxB; assert(IdxB < 11);	0	5896	--IdxB; assert(IdxB < 11);	0
5897	return Rows[RowMap[IdxA]][IdxB];	0	5897	return Rows[RowMap[IdxA]][IdxB];	0
5898	}	---	5898	}	---
5899		---	5899		---
5900	struct MaskRolOp {	---	5900	struct MaskRolOp {	---
5901	LaneBitmask Mask;	---	5901	LaneBitmask Mask;	---
5902	uint8_t RotateLeft;	---	5902	uint8_t RotateLeft;	---
5903	};	---	5903	};	---
5904	static const MaskRolOp LaneMaskComposeSequences[] = {	---	5904	static const MaskRolOp LaneMaskComposeSequences[] = {	---
5905	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0	---	5905	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0	---
5906	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2	---	5906	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2	---
5907	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4	---	5907	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4	---
5908	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6	---	5908	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6	---
5909	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8	---	5909	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8	---
5910	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10	---	5910	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10	---
5911	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12	---	5911	{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12	---
5912	};	---	5912	};	---
5913	static const uint8_t CompositeSequences[] = {	---	5913	static const uint8_t CompositeSequences[] = {	---
5914	0, // to sub_32	---	5914	0, // to sub_32	---
5915	0, // to sub_64	---	5915	0, // to sub_64	---
5916	2, // to sub_dsp16_19	---	5916	2, // to sub_dsp16_19	---
5917	4, // to sub_dsp20	---	5917	4, // to sub_dsp20	---
5918	6, // to sub_dsp21	---	5918	6, // to sub_dsp21	---
5919	8, // to sub_dsp22	---	5919	8, // to sub_dsp22	---
5920	10, // to sub_dsp23	---	5920	10, // to sub_dsp23	---
5921	12, // to sub_hi	---	5921	12, // to sub_hi	---
5922	0, // to sub_lo	---	5922	0, // to sub_lo	---
5923	12, // to sub_hi_then_sub_32	---	5923	12, // to sub_hi_then_sub_32	---
5924	0 // to sub_32_sub_hi_then_sub_32	---	5924	0 // to sub_32_sub_hi_then_sub_32	---
5925	};	---	5925	};	---
5926		---	5926		---
5927	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0	5927	LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0
5928	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0	5928	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0
5929	LaneBitmask Result;	0	5929	LaneBitmask Result;	0
5930	for (const MaskRolOp *Ops =	0	5930	for (const MaskRolOp *Ops =	0
5931	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0	5931	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0
5932	Ops->Mask.any(); ++Ops) {	0	5932	Ops->Mask.any(); ++Ops) {	0
5933	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();	0	5933	LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();	0
5934	if (unsigned S = Ops->RotateLeft)	0	5934	if (unsigned S = Ops->RotateLeft)	0
5935	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));	0	5935	Result \|= LaneBitmask((M << S) \| (M >> (LaneBitmask::BitWidth - S)));	0
5936	else	---	5936	else	---
5937	Result \|= LaneBitmask(M);	0	5937	Result \|= LaneBitmask(M);	0
5938	}	---	5938	}	---
5939	return Result;	0	5939	return Result;	0
5940	}	---	5940	}	---
5941		---	5941		---
5942	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0	5942	LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {	0
5943	LaneMask &= getSubRegIndexLaneMask(IdxA);	0	5943	LaneMask &= getSubRegIndexLaneMask(IdxA);	0
5944	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0	5944	--IdxA; assert(IdxA < 11 && "Subregister index out of bounds");	0
5945	LaneBitmask Result;	0	5945	LaneBitmask Result;	0
5946	for (const MaskRolOp *Ops =	0	5946	for (const MaskRolOp *Ops =	0
5947	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0	5947	&LaneMaskComposeSequences[CompositeSequences[IdxA]];	0
5948	Ops->Mask.any(); ++Ops) {	0	5948	Ops->Mask.any(); ++Ops) {	0
5949	LaneBitmask::Type M = LaneMask.getAsInteger();	0	5949	LaneBitmask::Type M = LaneMask.getAsInteger();	0
5950	if (unsigned S = Ops->RotateLeft)	0	5950	if (unsigned S = Ops->RotateLeft)	0
5951	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));	0	5951	Result \|= LaneBitmask((M >> S) \| (M << (LaneBitmask::BitWidth - S)));	0
5952	else	---	5952	else	---
5953	Result \|= LaneBitmask(M);	0	5953	Result \|= LaneBitmask(M);	0
5954	}	---	5954	}	---
5955	return Result;	0	5955	return Result;	0
5956	}	---	5956	}	---
5957		---	5957		---
5958	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {	0	5958	const TargetRegisterClass MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass RC, unsigned Idx) const {	0
5959	static const uint8_t Table[70][11] = {	---	5959	static const uint8_t Table[70][11] = {	---
5960	{ // MSA128F16	---	5960	{ // MSA128F16	---
5961	0, // sub_32	---	5961	0, // sub_32	---
5962	1, // sub_64 -> MSA128F16	---	5962	1, // sub_64 -> MSA128F16	---
5963	0, // sub_dsp16_19	---	5963	0, // sub_dsp16_19	---
5964	0, // sub_dsp20	---	5964	0, // sub_dsp20	---
5965	0, // sub_dsp21	---	5965	0, // sub_dsp21	---
5966	0, // sub_dsp22	---	5966	0, // sub_dsp22	---
5967	0, // sub_dsp23	---	5967	0, // sub_dsp23	---
5968	1, // sub_hi -> MSA128F16	---	5968	1, // sub_hi -> MSA128F16	---
5969	1, // sub_lo -> MSA128F16	---	5969	1, // sub_lo -> MSA128F16	---
5970	0, // sub_hi_then_sub_32	---	5970	0, // sub_hi_then_sub_32	---
5971	0, // sub_32_sub_hi_then_sub_32	---	5971	0, // sub_32_sub_hi_then_sub_32	---
5972	},	---	5972	},	---
5973	{ // CCR	---	5973	{ // CCR	---
5974	0, // sub_32	---	5974	0, // sub_32	---
5975	0, // sub_64	---	5975	0, // sub_64	---
5976	0, // sub_dsp16_19	---	5976	0, // sub_dsp16_19	---
5977	0, // sub_dsp20	---	5977	0, // sub_dsp20	---
5978	0, // sub_dsp21	---	5978	0, // sub_dsp21	---
5979	0, // sub_dsp22	---	5979	0, // sub_dsp22	---
5980	0, // sub_dsp23	---	5980	0, // sub_dsp23	---
5981	0, // sub_hi	---	5981	0, // sub_hi	---
5982	0, // sub_lo	---	5982	0, // sub_lo	---
5983	0, // sub_hi_then_sub_32	---	5983	0, // sub_hi_then_sub_32	---
5984	0, // sub_32_sub_hi_then_sub_32	---	5984	0, // sub_32_sub_hi_then_sub_32	---
5985	},	---	5985	},	---
5986	{ // COP0	---	5986	{ // COP0	---
5987	0, // sub_32	---	5987	0, // sub_32	---
5988	0, // sub_64	---	5988	0, // sub_64	---
5989	0, // sub_dsp16_19	---	5989	0, // sub_dsp16_19	---
5990	0, // sub_dsp20	---	5990	0, // sub_dsp20	---
5991	0, // sub_dsp21	---	5991	0, // sub_dsp21	---
5992	0, // sub_dsp22	---	5992	0, // sub_dsp22	---
5993	0, // sub_dsp23	---	5993	0, // sub_dsp23	---
5994	0, // sub_hi	---	5994	0, // sub_hi	---
5995	0, // sub_lo	---	5995	0, // sub_lo	---
5996	0, // sub_hi_then_sub_32	---	5996	0, // sub_hi_then_sub_32	---
5997	0, // sub_32_sub_hi_then_sub_32	---	5997	0, // sub_32_sub_hi_then_sub_32	---
5998	},	---	5998	},	---
5999	{ // COP2	---	5999	{ // COP2	---
6000	0, // sub_32	---	6000	0, // sub_32	---
6001	0, // sub_64	---	6001	0, // sub_64	---
6002	0, // sub_dsp16_19	---	6002	0, // sub_dsp16_19	---
6003	0, // sub_dsp20	---	6003	0, // sub_dsp20	---
6004	0, // sub_dsp21	---	6004	0, // sub_dsp21	---
6005	0, // sub_dsp22	---	6005	0, // sub_dsp22	---
6006	0, // sub_dsp23	---	6006	0, // sub_dsp23	---
6007	0, // sub_hi	---	6007	0, // sub_hi	---
6008	0, // sub_lo	---	6008	0, // sub_lo	---
6009	0, // sub_hi_then_sub_32	---	6009	0, // sub_hi_then_sub_32	---
6010	0, // sub_32_sub_hi_then_sub_32	---	6010	0, // sub_32_sub_hi_then_sub_32	---
6011	},	---	6011	},	---
6012	{ // COP3	---	6012	{ // COP3	---
6013	0, // sub_32	---	6013	0, // sub_32	---
6014	0, // sub_64	---	6014	0, // sub_64	---
6015	0, // sub_dsp16_19	---	6015	0, // sub_dsp16_19	---
6016	0, // sub_dsp20	---	6016	0, // sub_dsp20	---
6017	0, // sub_dsp21	---	6017	0, // sub_dsp21	---
6018	0, // sub_dsp22	---	6018	0, // sub_dsp22	---
6019	0, // sub_dsp23	---	6019	0, // sub_dsp23	---
6020	0, // sub_hi	---	6020	0, // sub_hi	---
6021	0, // sub_lo	---	6021	0, // sub_lo	---
6022	0, // sub_hi_then_sub_32	---	6022	0, // sub_hi_then_sub_32	---
6023	0, // sub_32_sub_hi_then_sub_32	---	6023	0, // sub_32_sub_hi_then_sub_32	---
6024	},	---	6024	},	---
6025	{ // DSPR	---	6025	{ // DSPR	---
6026	0, // sub_32	---	6026	0, // sub_32	---
6027	0, // sub_64	---	6027	0, // sub_64	---
6028	0, // sub_dsp16_19	---	6028	0, // sub_dsp16_19	---
6029	0, // sub_dsp20	---	6029	0, // sub_dsp20	---
6030	0, // sub_dsp21	---	6030	0, // sub_dsp21	---
6031	0, // sub_dsp22	---	6031	0, // sub_dsp22	---
6032	0, // sub_dsp23	---	6032	0, // sub_dsp23	---
6033	0, // sub_hi	---	6033	0, // sub_hi	---
6034	0, // sub_lo	---	6034	0, // sub_lo	---
6035	0, // sub_hi_then_sub_32	---	6035	0, // sub_hi_then_sub_32	---
6036	0, // sub_32_sub_hi_then_sub_32	---	6036	0, // sub_32_sub_hi_then_sub_32	---
6037	},	---	6037	},	---
6038	{ // FGR32	---	6038	{ // FGR32	---
6039	0, // sub_32	---	6039	0, // sub_32	---
6040	0, // sub_64	---	6040	0, // sub_64	---
6041	0, // sub_dsp16_19	---	6041	0, // sub_dsp16_19	---
6042	0, // sub_dsp20	---	6042	0, // sub_dsp20	---
6043	0, // sub_dsp21	---	6043	0, // sub_dsp21	---
6044	0, // sub_dsp22	---	6044	0, // sub_dsp22	---
6045	0, // sub_dsp23	---	6045	0, // sub_dsp23	---
6046	0, // sub_hi	---	6046	0, // sub_hi	---
6047	0, // sub_lo	---	6047	0, // sub_lo	---
6048	0, // sub_hi_then_sub_32	---	6048	0, // sub_hi_then_sub_32	---
6049	0, // sub_32_sub_hi_then_sub_32	---	6049	0, // sub_32_sub_hi_then_sub_32	---
6050	},	---	6050	},	---
6051	{ // FGRCC	---	6051	{ // FGRCC	---
6052	0, // sub_32	---	6052	0, // sub_32	---
6053	0, // sub_64	---	6053	0, // sub_64	---
6054	0, // sub_dsp16_19	---	6054	0, // sub_dsp16_19	---
6055	0, // sub_dsp20	---	6055	0, // sub_dsp20	---
6056	0, // sub_dsp21	---	6056	0, // sub_dsp21	---
6057	0, // sub_dsp22	---	6057	0, // sub_dsp22	---
6058	0, // sub_dsp23	---	6058	0, // sub_dsp23	---
6059	0, // sub_hi	---	6059	0, // sub_hi	---
6060	0, // sub_lo	---	6060	0, // sub_lo	---
6061	0, // sub_hi_then_sub_32	---	6061	0, // sub_hi_then_sub_32	---
6062	0, // sub_32_sub_hi_then_sub_32	---	6062	0, // sub_32_sub_hi_then_sub_32	---
6063	},	---	6063	},	---
6064	{ // GPR32	---	6064	{ // GPR32	---
6065	0, // sub_32	---	6065	0, // sub_32	---
6066	0, // sub_64	---	6066	0, // sub_64	---
6067	0, // sub_dsp16_19	---	6067	0, // sub_dsp16_19	---
6068	0, // sub_dsp20	---	6068	0, // sub_dsp20	---
6069	0, // sub_dsp21	---	6069	0, // sub_dsp21	---
6070	0, // sub_dsp22	---	6070	0, // sub_dsp22	---
6071	0, // sub_dsp23	---	6071	0, // sub_dsp23	---
6072	0, // sub_hi	---	6072	0, // sub_hi	---
6073	0, // sub_lo	---	6073	0, // sub_lo	---
6074	0, // sub_hi_then_sub_32	---	6074	0, // sub_hi_then_sub_32	---
6075	0, // sub_32_sub_hi_then_sub_32	---	6075	0, // sub_32_sub_hi_then_sub_32	---
6076	},	---	6076	},	---
6077	{ // HWRegs	---	6077	{ // HWRegs	---
6078	0, // sub_32	---	6078	0, // sub_32	---
6079	0, // sub_64	---	6079	0, // sub_64	---
6080	0, // sub_dsp16_19	---	6080	0, // sub_dsp16_19	---
6081	0, // sub_dsp20	---	6081	0, // sub_dsp20	---
6082	0, // sub_dsp21	---	6082	0, // sub_dsp21	---
6083	0, // sub_dsp22	---	6083	0, // sub_dsp22	---
6084	0, // sub_dsp23	---	6084	0, // sub_dsp23	---
6085	0, // sub_hi	---	6085	0, // sub_hi	---
6086	0, // sub_lo	---	6086	0, // sub_lo	---
6087	0, // sub_hi_then_sub_32	---	6087	0, // sub_hi_then_sub_32	---
6088	0, // sub_32_sub_hi_then_sub_32	---	6088	0, // sub_32_sub_hi_then_sub_32	---
6089	},	---	6089	},	---
6090	{ // MSACtrl	---	6090	{ // MSACtrl	---
6091	0, // sub_32	---	6091	0, // sub_32	---
6092	0, // sub_64	---	6092	0, // sub_64	---
6093	0, // sub_dsp16_19	---	6093	0, // sub_dsp16_19	---
6094	0, // sub_dsp20	---	6094	0, // sub_dsp20	---
6095	0, // sub_dsp21	---	6095	0, // sub_dsp21	---
6096	0, // sub_dsp22	---	6096	0, // sub_dsp22	---
6097	0, // sub_dsp23	---	6097	0, // sub_dsp23	---
6098	0, // sub_hi	---	6098	0, // sub_hi	---
6099	0, // sub_lo	---	6099	0, // sub_lo	---
6100	0, // sub_hi_then_sub_32	---	6100	0, // sub_hi_then_sub_32	---
6101	0, // sub_32_sub_hi_then_sub_32	---	6101	0, // sub_32_sub_hi_then_sub_32	---
6102	},	---	6102	},	---
6103	{ // GPR32NONZERO	---	6103	{ // GPR32NONZERO	---
6104	0, // sub_32	---	6104	0, // sub_32	---
6105	0, // sub_64	---	6105	0, // sub_64	---
6106	0, // sub_dsp16_19	---	6106	0, // sub_dsp16_19	---
6107	0, // sub_dsp20	---	6107	0, // sub_dsp20	---
6108	0, // sub_dsp21	---	6108	0, // sub_dsp21	---
6109	0, // sub_dsp22	---	6109	0, // sub_dsp22	---
6110	0, // sub_dsp23	---	6110	0, // sub_dsp23	---
6111	0, // sub_hi	---	6111	0, // sub_hi	---
6112	0, // sub_lo	---	6112	0, // sub_lo	---
6113	0, // sub_hi_then_sub_32	---	6113	0, // sub_hi_then_sub_32	---
6114	0, // sub_32_sub_hi_then_sub_32	---	6114	0, // sub_32_sub_hi_then_sub_32	---
6115	},	---	6115	},	---
6116	{ // CPU16RegsPlusSP	---	6116	{ // CPU16RegsPlusSP	---
6117	0, // sub_32	---	6117	0, // sub_32	---
6118	0, // sub_64	---	6118	0, // sub_64	---
6119	0, // sub_dsp16_19	---	6119	0, // sub_dsp16_19	---
6120	0, // sub_dsp20	---	6120	0, // sub_dsp20	---
6121	0, // sub_dsp21	---	6121	0, // sub_dsp21	---
6122	0, // sub_dsp22	---	6122	0, // sub_dsp22	---
6123	0, // sub_dsp23	---	6123	0, // sub_dsp23	---
6124	0, // sub_hi	---	6124	0, // sub_hi	---
6125	0, // sub_lo	---	6125	0, // sub_lo	---
6126	0, // sub_hi_then_sub_32	---	6126	0, // sub_hi_then_sub_32	---
6127	0, // sub_32_sub_hi_then_sub_32	---	6127	0, // sub_32_sub_hi_then_sub_32	---
6128	},	---	6128	},	---
6129	{ // CPU16Regs	---	6129	{ // CPU16Regs	---
6130	0, // sub_32	---	6130	0, // sub_32	---
6131	0, // sub_64	---	6131	0, // sub_64	---
6132	0, // sub_dsp16_19	---	6132	0, // sub_dsp16_19	---
6133	0, // sub_dsp20	---	6133	0, // sub_dsp20	---
6134	0, // sub_dsp21	---	6134	0, // sub_dsp21	---
6135	0, // sub_dsp22	---	6135	0, // sub_dsp22	---
6136	0, // sub_dsp23	---	6136	0, // sub_dsp23	---
6137	0, // sub_hi	---	6137	0, // sub_hi	---
6138	0, // sub_lo	---	6138	0, // sub_lo	---
6139	0, // sub_hi_then_sub_32	---	6139	0, // sub_hi_then_sub_32	---
6140	0, // sub_32_sub_hi_then_sub_32	---	6140	0, // sub_32_sub_hi_then_sub_32	---
6141	},	---	6141	},	---
6142	{ // FCC	---	6142	{ // FCC	---
6143	0, // sub_32	---	6143	0, // sub_32	---
6144	0, // sub_64	---	6144	0, // sub_64	---
6145	0, // sub_dsp16_19	---	6145	0, // sub_dsp16_19	---
6146	0, // sub_dsp20	---	6146	0, // sub_dsp20	---
6147	0, // sub_dsp21	---	6147	0, // sub_dsp21	---
6148	0, // sub_dsp22	---	6148	0, // sub_dsp22	---
6149	0, // sub_dsp23	---	6149	0, // sub_dsp23	---
6150	0, // sub_hi	---	6150	0, // sub_hi	---
6151	0, // sub_lo	---	6151	0, // sub_lo	---
6152	0, // sub_hi_then_sub_32	---	6152	0, // sub_hi_then_sub_32	---
6153	0, // sub_32_sub_hi_then_sub_32	---	6153	0, // sub_32_sub_hi_then_sub_32	---
6154	},	---	6154	},	---
6155	{ // GPRMM16	---	6155	{ // GPRMM16	---
6156	0, // sub_32	---	6156	0, // sub_32	---
6157	0, // sub_64	---	6157	0, // sub_64	---
6158	0, // sub_dsp16_19	---	6158	0, // sub_dsp16_19	---
6159	0, // sub_dsp20	---	6159	0, // sub_dsp20	---
6160	0, // sub_dsp21	---	6160	0, // sub_dsp21	---
6161	0, // sub_dsp22	---	6161	0, // sub_dsp22	---
6162	0, // sub_dsp23	---	6162	0, // sub_dsp23	---
6163	0, // sub_hi	---	6163	0, // sub_hi	---
6164	0, // sub_lo	---	6164	0, // sub_lo	---
6165	0, // sub_hi_then_sub_32	---	6165	0, // sub_hi_then_sub_32	---
6166	0, // sub_32_sub_hi_then_sub_32	---	6166	0, // sub_32_sub_hi_then_sub_32	---
6167	},	---	6167	},	---
6168	{ // GPRMM16MoveP	---	6168	{ // GPRMM16MoveP	---
6169	0, // sub_32	---	6169	0, // sub_32	---
6170	0, // sub_64	---	6170	0, // sub_64	---
6171	0, // sub_dsp16_19	---	6171	0, // sub_dsp16_19	---
6172	0, // sub_dsp20	---	6172	0, // sub_dsp20	---
6173	0, // sub_dsp21	---	6173	0, // sub_dsp21	---
6174	0, // sub_dsp22	---	6174	0, // sub_dsp22	---
6175	0, // sub_dsp23	---	6175	0, // sub_dsp23	---
6176	0, // sub_hi	---	6176	0, // sub_hi	---
6177	0, // sub_lo	---	6177	0, // sub_lo	---
6178	0, // sub_hi_then_sub_32	---	6178	0, // sub_hi_then_sub_32	---
6179	0, // sub_32_sub_hi_then_sub_32	---	6179	0, // sub_32_sub_hi_then_sub_32	---
6180	},	---	6180	},	---
6181	{ // GPRMM16Zero	---	6181	{ // GPRMM16Zero	---
6182	0, // sub_32	---	6182	0, // sub_32	---
6183	0, // sub_64	---	6183	0, // sub_64	---
6184	0, // sub_dsp16_19	---	6184	0, // sub_dsp16_19	---
6185	0, // sub_dsp20	---	6185	0, // sub_dsp20	---
6186	0, // sub_dsp21	---	6186	0, // sub_dsp21	---
6187	0, // sub_dsp22	---	6187	0, // sub_dsp22	---
6188	0, // sub_dsp23	---	6188	0, // sub_dsp23	---
6189	0, // sub_hi	---	6189	0, // sub_hi	---
6190	0, // sub_lo	---	6190	0, // sub_lo	---
6191	0, // sub_hi_then_sub_32	---	6191	0, // sub_hi_then_sub_32	---
6192	0, // sub_32_sub_hi_then_sub_32	---	6192	0, // sub_32_sub_hi_then_sub_32	---
6193	},	---	6193	},	---
6194	{ // CPU16Regs_and_GPRMM16Zero	---	6194	{ // CPU16Regs_and_GPRMM16Zero	---
6195	0, // sub_32	---	6195	0, // sub_32	---
6196	0, // sub_64	---	6196	0, // sub_64	---
6197	0, // sub_dsp16_19	---	6197	0, // sub_dsp16_19	---
6198	0, // sub_dsp20	---	6198	0, // sub_dsp20	---
6199	0, // sub_dsp21	---	6199	0, // sub_dsp21	---
6200	0, // sub_dsp22	---	6200	0, // sub_dsp22	---
6201	0, // sub_dsp23	---	6201	0, // sub_dsp23	---
6202	0, // sub_hi	---	6202	0, // sub_hi	---
6203	0, // sub_lo	---	6203	0, // sub_lo	---
6204	0, // sub_hi_then_sub_32	---	6204	0, // sub_hi_then_sub_32	---
6205	0, // sub_32_sub_hi_then_sub_32	---	6205	0, // sub_32_sub_hi_then_sub_32	---
6206	},	---	6206	},	---
6207	{ // GPR32NONZERO_and_GPRMM16MoveP	---	6207	{ // GPR32NONZERO_and_GPRMM16MoveP	---
6208	0, // sub_32	---	6208	0, // sub_32	---
6209	0, // sub_64	---	6209	0, // sub_64	---
6210	0, // sub_dsp16_19	---	6210	0, // sub_dsp16_19	---
6211	0, // sub_dsp20	---	6211	0, // sub_dsp20	---
6212	0, // sub_dsp21	---	6212	0, // sub_dsp21	---
6213	0, // sub_dsp22	---	6213	0, // sub_dsp22	---
6214	0, // sub_dsp23	---	6214	0, // sub_dsp23	---
6215	0, // sub_hi	---	6215	0, // sub_hi	---
6216	0, // sub_lo	---	6216	0, // sub_lo	---
6217	0, // sub_hi_then_sub_32	---	6217	0, // sub_hi_then_sub_32	---
6218	0, // sub_32_sub_hi_then_sub_32	---	6218	0, // sub_32_sub_hi_then_sub_32	---
6219	},	---	6219	},	---
6220	{ // GPRMM16MovePPairSecond	---	6220	{ // GPRMM16MovePPairSecond	---
6221	0, // sub_32	---	6221	0, // sub_32	---
6222	0, // sub_64	---	6222	0, // sub_64	---
6223	0, // sub_dsp16_19	---	6223	0, // sub_dsp16_19	---
6224	0, // sub_dsp20	---	6224	0, // sub_dsp20	---
6225	0, // sub_dsp21	---	6225	0, // sub_dsp21	---
6226	0, // sub_dsp22	---	6226	0, // sub_dsp22	---
6227	0, // sub_dsp23	---	6227	0, // sub_dsp23	---
6228	0, // sub_hi	---	6228	0, // sub_hi	---
6229	0, // sub_lo	---	6229	0, // sub_lo	---
6230	0, // sub_hi_then_sub_32	---	6230	0, // sub_hi_then_sub_32	---
6231	0, // sub_32_sub_hi_then_sub_32	---	6231	0, // sub_32_sub_hi_then_sub_32	---
6232	},	---	6232	},	---
6233	{ // CPU16Regs_and_GPRMM16MoveP	---	6233	{ // CPU16Regs_and_GPRMM16MoveP	---
6234	0, // sub_32	---	6234	0, // sub_32	---
6235	0, // sub_64	---	6235	0, // sub_64	---
6236	0, // sub_dsp16_19	---	6236	0, // sub_dsp16_19	---
6237	0, // sub_dsp20	---	6237	0, // sub_dsp20	---
6238	0, // sub_dsp21	---	6238	0, // sub_dsp21	---
6239	0, // sub_dsp22	---	6239	0, // sub_dsp22	---
6240	0, // sub_dsp23	---	6240	0, // sub_dsp23	---
6241	0, // sub_hi	---	6241	0, // sub_hi	---
6242	0, // sub_lo	---	6242	0, // sub_lo	---
6243	0, // sub_hi_then_sub_32	---	6243	0, // sub_hi_then_sub_32	---
6244	0, // sub_32_sub_hi_then_sub_32	---	6244	0, // sub_32_sub_hi_then_sub_32	---
6245	},	---	6245	},	---
6246	{ // GPRMM16MoveP_and_GPRMM16Zero	---	6246	{ // GPRMM16MoveP_and_GPRMM16Zero	---
6247	0, // sub_32	---	6247	0, // sub_32	---
6248	0, // sub_64	---	6248	0, // sub_64	---
6249	0, // sub_dsp16_19	---	6249	0, // sub_dsp16_19	---
6250	0, // sub_dsp20	---	6250	0, // sub_dsp20	---
6251	0, // sub_dsp21	---	6251	0, // sub_dsp21	---
6252	0, // sub_dsp22	---	6252	0, // sub_dsp22	---
6253	0, // sub_dsp23	---	6253	0, // sub_dsp23	---
6254	0, // sub_hi	---	6254	0, // sub_hi	---
6255	0, // sub_lo	---	6255	0, // sub_lo	---
6256	0, // sub_hi_then_sub_32	---	6256	0, // sub_hi_then_sub_32	---
6257	0, // sub_32_sub_hi_then_sub_32	---	6257	0, // sub_32_sub_hi_then_sub_32	---
6258	},	---	6258	},	---
6259	{ // HI32DSP	---	6259	{ // HI32DSP	---
6260	0, // sub_32	---	6260	0, // sub_32	---
6261	0, // sub_64	---	6261	0, // sub_64	---
6262	0, // sub_dsp16_19	---	6262	0, // sub_dsp16_19	---
6263	0, // sub_dsp20	---	6263	0, // sub_dsp20	---
6264	0, // sub_dsp21	---	6264	0, // sub_dsp21	---
6265	0, // sub_dsp22	---	6265	0, // sub_dsp22	---
6266	0, // sub_dsp23	---	6266	0, // sub_dsp23	---
6267	0, // sub_hi	---	6267	0, // sub_hi	---
6268	0, // sub_lo	---	6268	0, // sub_lo	---
6269	0, // sub_hi_then_sub_32	---	6269	0, // sub_hi_then_sub_32	---
6270	0, // sub_32_sub_hi_then_sub_32	---	6270	0, // sub_32_sub_hi_then_sub_32	---
6271	},	---	6271	},	---
6272	{ // LO32DSP	---	6272	{ // LO32DSP	---
6273	0, // sub_32	---	6273	0, // sub_32	---
6274	0, // sub_64	---	6274	0, // sub_64	---
6275	0, // sub_dsp16_19	---	6275	0, // sub_dsp16_19	---
6276	0, // sub_dsp20	---	6276	0, // sub_dsp20	---
6277	0, // sub_dsp21	---	6277	0, // sub_dsp21	---
6278	0, // sub_dsp22	---	6278	0, // sub_dsp22	---
6279	0, // sub_dsp23	---	6279	0, // sub_dsp23	---
6280	0, // sub_hi	---	6280	0, // sub_hi	---
6281	0, // sub_lo	---	6281	0, // sub_lo	---
6282	0, // sub_hi_then_sub_32	---	6282	0, // sub_hi_then_sub_32	---
6283	0, // sub_32_sub_hi_then_sub_32	---	6283	0, // sub_32_sub_hi_then_sub_32	---
6284	},	---	6284	},	---
6285	{ // CPU16Regs_and_GPRMM16MovePPairSecond	---	6285	{ // CPU16Regs_and_GPRMM16MovePPairSecond	---
6286	0, // sub_32	---	6286	0, // sub_32	---
6287	0, // sub_64	---	6287	0, // sub_64	---
6288	0, // sub_dsp16_19	---	6288	0, // sub_dsp16_19	---
6289	0, // sub_dsp20	---	6289	0, // sub_dsp20	---
6290	0, // sub_dsp21	---	6290	0, // sub_dsp21	---
6291	0, // sub_dsp22	---	6291	0, // sub_dsp22	---
6292	0, // sub_dsp23	---	6292	0, // sub_dsp23	---
6293	0, // sub_hi	---	6293	0, // sub_hi	---
6294	0, // sub_lo	---	6294	0, // sub_lo	---
6295	0, // sub_hi_then_sub_32	---	6295	0, // sub_hi_then_sub_32	---
6296	0, // sub_32_sub_hi_then_sub_32	---	6296	0, // sub_32_sub_hi_then_sub_32	---
6297	},	---	6297	},	---
6298	{ // GPRMM16MovePPairFirst	---	6298	{ // GPRMM16MovePPairFirst	---
6299	0, // sub_32	---	6299	0, // sub_32	---
6300	0, // sub_64	---	6300	0, // sub_64	---
6301	0, // sub_dsp16_19	---	6301	0, // sub_dsp16_19	---
6302	0, // sub_dsp20	---	6302	0, // sub_dsp20	---
6303	0, // sub_dsp21	---	6303	0, // sub_dsp21	---
6304	0, // sub_dsp22	---	6304	0, // sub_dsp22	---
6305	0, // sub_dsp23	---	6305	0, // sub_dsp23	---
6306	0, // sub_hi	---	6306	0, // sub_hi	---
6307	0, // sub_lo	---	6307	0, // sub_lo	---
6308	0, // sub_hi_then_sub_32	---	6308	0, // sub_hi_then_sub_32	---
6309	0, // sub_32_sub_hi_then_sub_32	---	6309	0, // sub_32_sub_hi_then_sub_32	---
6310	},	---	6310	},	---
6311	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	6311	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
6312	0, // sub_32	---	6312	0, // sub_32	---
6313	0, // sub_64	---	6313	0, // sub_64	---
6314	0, // sub_dsp16_19	---	6314	0, // sub_dsp16_19	---
6315	0, // sub_dsp20	---	6315	0, // sub_dsp20	---
6316	0, // sub_dsp21	---	6316	0, // sub_dsp21	---
6317	0, // sub_dsp22	---	6317	0, // sub_dsp22	---
6318	0, // sub_dsp23	---	6318	0, // sub_dsp23	---
6319	0, // sub_hi	---	6319	0, // sub_hi	---
6320	0, // sub_lo	---	6320	0, // sub_lo	---
6321	0, // sub_hi_then_sub_32	---	6321	0, // sub_hi_then_sub_32	---
6322	0, // sub_32_sub_hi_then_sub_32	---	6322	0, // sub_32_sub_hi_then_sub_32	---
6323	},	---	6323	},	---
6324	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	6324	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
6325	0, // sub_32	---	6325	0, // sub_32	---
6326	0, // sub_64	---	6326	0, // sub_64	---
6327	0, // sub_dsp16_19	---	6327	0, // sub_dsp16_19	---
6328	0, // sub_dsp20	---	6328	0, // sub_dsp20	---
6329	0, // sub_dsp21	---	6329	0, // sub_dsp21	---
6330	0, // sub_dsp22	---	6330	0, // sub_dsp22	---
6331	0, // sub_dsp23	---	6331	0, // sub_dsp23	---
6332	0, // sub_hi	---	6332	0, // sub_hi	---
6333	0, // sub_lo	---	6333	0, // sub_lo	---
6334	0, // sub_hi_then_sub_32	---	6334	0, // sub_hi_then_sub_32	---
6335	0, // sub_32_sub_hi_then_sub_32	---	6335	0, // sub_32_sub_hi_then_sub_32	---
6336	},	---	6336	},	---
6337	{ // CPURAReg	---	6337	{ // CPURAReg	---
6338	0, // sub_32	---	6338	0, // sub_32	---
6339	0, // sub_64	---	6339	0, // sub_64	---
6340	0, // sub_dsp16_19	---	6340	0, // sub_dsp16_19	---
6341	0, // sub_dsp20	---	6341	0, // sub_dsp20	---
6342	0, // sub_dsp21	---	6342	0, // sub_dsp21	---
6343	0, // sub_dsp22	---	6343	0, // sub_dsp22	---
6344	0, // sub_dsp23	---	6344	0, // sub_dsp23	---
6345	0, // sub_hi	---	6345	0, // sub_hi	---
6346	0, // sub_lo	---	6346	0, // sub_lo	---
6347	0, // sub_hi_then_sub_32	---	6347	0, // sub_hi_then_sub_32	---
6348	0, // sub_32_sub_hi_then_sub_32	---	6348	0, // sub_32_sub_hi_then_sub_32	---
6349	},	---	6349	},	---
6350	{ // CPUSPReg	---	6350	{ // CPUSPReg	---
6351	0, // sub_32	---	6351	0, // sub_32	---
6352	0, // sub_64	---	6352	0, // sub_64	---
6353	0, // sub_dsp16_19	---	6353	0, // sub_dsp16_19	---
6354	0, // sub_dsp20	---	6354	0, // sub_dsp20	---
6355	0, // sub_dsp21	---	6355	0, // sub_dsp21	---
6356	0, // sub_dsp22	---	6356	0, // sub_dsp22	---
6357	0, // sub_dsp23	---	6357	0, // sub_dsp23	---
6358	0, // sub_hi	---	6358	0, // sub_hi	---
6359	0, // sub_lo	---	6359	0, // sub_lo	---
6360	0, // sub_hi_then_sub_32	---	6360	0, // sub_hi_then_sub_32	---
6361	0, // sub_32_sub_hi_then_sub_32	---	6361	0, // sub_32_sub_hi_then_sub_32	---
6362	},	---	6362	},	---
6363	{ // DSPCC	---	6363	{ // DSPCC	---
6364	0, // sub_32	---	6364	0, // sub_32	---
6365	0, // sub_64	---	6365	0, // sub_64	---
6366	0, // sub_dsp16_19	---	6366	0, // sub_dsp16_19	---
6367	0, // sub_dsp20	---	6367	0, // sub_dsp20	---
6368	0, // sub_dsp21	---	6368	0, // sub_dsp21	---
6369	0, // sub_dsp22	---	6369	0, // sub_dsp22	---
6370	0, // sub_dsp23	---	6370	0, // sub_dsp23	---
6371	0, // sub_hi	---	6371	0, // sub_hi	---
6372	0, // sub_lo	---	6372	0, // sub_lo	---
6373	0, // sub_hi_then_sub_32	---	6373	0, // sub_hi_then_sub_32	---
6374	0, // sub_32_sub_hi_then_sub_32	---	6374	0, // sub_32_sub_hi_then_sub_32	---
6375	},	---	6375	},	---
6376	{ // GP32	---	6376	{ // GP32	---
6377	0, // sub_32	---	6377	0, // sub_32	---
6378	0, // sub_64	---	6378	0, // sub_64	---
6379	0, // sub_dsp16_19	---	6379	0, // sub_dsp16_19	---
6380	0, // sub_dsp20	---	6380	0, // sub_dsp20	---
6381	0, // sub_dsp21	---	6381	0, // sub_dsp21	---
6382	0, // sub_dsp22	---	6382	0, // sub_dsp22	---
6383	0, // sub_dsp23	---	6383	0, // sub_dsp23	---
6384	0, // sub_hi	---	6384	0, // sub_hi	---
6385	0, // sub_lo	---	6385	0, // sub_lo	---
6386	0, // sub_hi_then_sub_32	---	6386	0, // sub_hi_then_sub_32	---
6387	0, // sub_32_sub_hi_then_sub_32	---	6387	0, // sub_32_sub_hi_then_sub_32	---
6388	},	---	6388	},	---
6389	{ // GPR32ZERO	---	6389	{ // GPR32ZERO	---
6390	0, // sub_32	---	6390	0, // sub_32	---
6391	0, // sub_64	---	6391	0, // sub_64	---
6392	0, // sub_dsp16_19	---	6392	0, // sub_dsp16_19	---
6393	0, // sub_dsp20	---	6393	0, // sub_dsp20	---
6394	0, // sub_dsp21	---	6394	0, // sub_dsp21	---
6395	0, // sub_dsp22	---	6395	0, // sub_dsp22	---
6396	0, // sub_dsp23	---	6396	0, // sub_dsp23	---
6397	0, // sub_hi	---	6397	0, // sub_hi	---
6398	0, // sub_lo	---	6398	0, // sub_lo	---
6399	0, // sub_hi_then_sub_32	---	6399	0, // sub_hi_then_sub_32	---
6400	0, // sub_32_sub_hi_then_sub_32	---	6400	0, // sub_32_sub_hi_then_sub_32	---
6401	},	---	6401	},	---
6402	{ // HI32	---	6402	{ // HI32	---
6403	0, // sub_32	---	6403	0, // sub_32	---
6404	0, // sub_64	---	6404	0, // sub_64	---
6405	0, // sub_dsp16_19	---	6405	0, // sub_dsp16_19	---
6406	0, // sub_dsp20	---	6406	0, // sub_dsp20	---
6407	0, // sub_dsp21	---	6407	0, // sub_dsp21	---
6408	0, // sub_dsp22	---	6408	0, // sub_dsp22	---
6409	0, // sub_dsp23	---	6409	0, // sub_dsp23	---
6410	0, // sub_hi	---	6410	0, // sub_hi	---
6411	0, // sub_lo	---	6411	0, // sub_lo	---
6412	0, // sub_hi_then_sub_32	---	6412	0, // sub_hi_then_sub_32	---
6413	0, // sub_32_sub_hi_then_sub_32	---	6413	0, // sub_32_sub_hi_then_sub_32	---
6414	},	---	6414	},	---
6415	{ // LO32	---	6415	{ // LO32	---
6416	0, // sub_32	---	6416	0, // sub_32	---
6417	0, // sub_64	---	6417	0, // sub_64	---
6418	0, // sub_dsp16_19	---	6418	0, // sub_dsp16_19	---
6419	0, // sub_dsp20	---	6419	0, // sub_dsp20	---
6420	0, // sub_dsp21	---	6420	0, // sub_dsp21	---
6421	0, // sub_dsp22	---	6421	0, // sub_dsp22	---
6422	0, // sub_dsp23	---	6422	0, // sub_dsp23	---
6423	0, // sub_hi	---	6423	0, // sub_hi	---
6424	0, // sub_lo	---	6424	0, // sub_lo	---
6425	0, // sub_hi_then_sub_32	---	6425	0, // sub_hi_then_sub_32	---
6426	0, // sub_32_sub_hi_then_sub_32	---	6426	0, // sub_32_sub_hi_then_sub_32	---
6427	},	---	6427	},	---
6428	{ // SP32	---	6428	{ // SP32	---
6429	0, // sub_32	---	6429	0, // sub_32	---
6430	0, // sub_64	---	6430	0, // sub_64	---
6431	0, // sub_dsp16_19	---	6431	0, // sub_dsp16_19	---
6432	0, // sub_dsp20	---	6432	0, // sub_dsp20	---
6433	0, // sub_dsp21	---	6433	0, // sub_dsp21	---
6434	0, // sub_dsp22	---	6434	0, // sub_dsp22	---
6435	0, // sub_dsp23	---	6435	0, // sub_dsp23	---
6436	0, // sub_hi	---	6436	0, // sub_hi	---
6437	0, // sub_lo	---	6437	0, // sub_lo	---
6438	0, // sub_hi_then_sub_32	---	6438	0, // sub_hi_then_sub_32	---
6439	0, // sub_32_sub_hi_then_sub_32	---	6439	0, // sub_32_sub_hi_then_sub_32	---
6440	},	---	6440	},	---
6441	{ // FGR64	---	6441	{ // FGR64	---
6442	0, // sub_32	---	6442	0, // sub_32	---
6443	0, // sub_64	---	6443	0, // sub_64	---
6444	0, // sub_dsp16_19	---	6444	0, // sub_dsp16_19	---
6445	0, // sub_dsp20	---	6445	0, // sub_dsp20	---
6446	0, // sub_dsp21	---	6446	0, // sub_dsp21	---
6447	0, // sub_dsp22	---	6447	0, // sub_dsp22	---
6448	0, // sub_dsp23	---	6448	0, // sub_dsp23	---
6449	38, // sub_hi -> FGR64	---	6449	38, // sub_hi -> FGR64	---
6450	38, // sub_lo -> FGR64	---	6450	38, // sub_lo -> FGR64	---
6451	0, // sub_hi_then_sub_32	---	6451	0, // sub_hi_then_sub_32	---
6452	0, // sub_32_sub_hi_then_sub_32	---	6452	0, // sub_32_sub_hi_then_sub_32	---
6453	},	---	6453	},	---
6454	{ // GPR64	---	6454	{ // GPR64	---
6455	39, // sub_32 -> GPR64	---	6455	39, // sub_32 -> GPR64	---
6456	0, // sub_64	---	6456	0, // sub_64	---
6457	0, // sub_dsp16_19	---	6457	0, // sub_dsp16_19	---
6458	0, // sub_dsp20	---	6458	0, // sub_dsp20	---
6459	0, // sub_dsp21	---	6459	0, // sub_dsp21	---
6460	0, // sub_dsp22	---	6460	0, // sub_dsp22	---
6461	0, // sub_dsp23	---	6461	0, // sub_dsp23	---
6462	0, // sub_hi	---	6462	0, // sub_hi	---
6463	0, // sub_lo	---	6463	0, // sub_lo	---
6464	0, // sub_hi_then_sub_32	---	6464	0, // sub_hi_then_sub_32	---
6465	0, // sub_32_sub_hi_then_sub_32	---	6465	0, // sub_32_sub_hi_then_sub_32	---
6466	},	---	6466	},	---
6467	{ // GPR64_with_sub_32_in_GPR32NONZERO	---	6467	{ // GPR64_with_sub_32_in_GPR32NONZERO	---
6468	40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO	---	6468	40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO	---
6469	0, // sub_64	---	6469	0, // sub_64	---
6470	0, // sub_dsp16_19	---	6470	0, // sub_dsp16_19	---
6471	0, // sub_dsp20	---	6471	0, // sub_dsp20	---
6472	0, // sub_dsp21	---	6472	0, // sub_dsp21	---
6473	0, // sub_dsp22	---	6473	0, // sub_dsp22	---
6474	0, // sub_dsp23	---	6474	0, // sub_dsp23	---
6475	0, // sub_hi	---	6475	0, // sub_hi	---
6476	0, // sub_lo	---	6476	0, // sub_lo	---
6477	0, // sub_hi_then_sub_32	---	6477	0, // sub_hi_then_sub_32	---
6478	0, // sub_32_sub_hi_then_sub_32	---	6478	0, // sub_32_sub_hi_then_sub_32	---
6479	},	---	6479	},	---
6480	{ // AFGR64	---	6480	{ // AFGR64	---
6481	0, // sub_32	---	6481	0, // sub_32	---
6482	0, // sub_64	---	6482	0, // sub_64	---
6483	0, // sub_dsp16_19	---	6483	0, // sub_dsp16_19	---
6484	0, // sub_dsp20	---	6484	0, // sub_dsp20	---
6485	0, // sub_dsp21	---	6485	0, // sub_dsp21	---
6486	0, // sub_dsp22	---	6486	0, // sub_dsp22	---
6487	0, // sub_dsp23	---	6487	0, // sub_dsp23	---
6488	41, // sub_hi -> AFGR64	---	6488	41, // sub_hi -> AFGR64	---
6489	41, // sub_lo -> AFGR64	---	6489	41, // sub_lo -> AFGR64	---
6490	0, // sub_hi_then_sub_32	---	6490	0, // sub_hi_then_sub_32	---
6491	0, // sub_32_sub_hi_then_sub_32	---	6491	0, // sub_32_sub_hi_then_sub_32	---
6492	},	---	6492	},	---
6493	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	---	6493	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	---
6494	42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP	---	6494	42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP	---
6495	0, // sub_64	---	6495	0, // sub_64	---
6496	0, // sub_dsp16_19	---	6496	0, // sub_dsp16_19	---
6497	0, // sub_dsp20	---	6497	0, // sub_dsp20	---
6498	0, // sub_dsp21	---	6498	0, // sub_dsp21	---
6499	0, // sub_dsp22	---	6499	0, // sub_dsp22	---
6500	0, // sub_dsp23	---	6500	0, // sub_dsp23	---
6501	0, // sub_hi	---	6501	0, // sub_hi	---
6502	0, // sub_lo	---	6502	0, // sub_lo	---
6503	0, // sub_hi_then_sub_32	---	6503	0, // sub_hi_then_sub_32	---
6504	0, // sub_32_sub_hi_then_sub_32	---	6504	0, // sub_32_sub_hi_then_sub_32	---
6505	},	---	6505	},	---
6506	{ // GPR64_with_sub_32_in_CPU16Regs	---	6506	{ // GPR64_with_sub_32_in_CPU16Regs	---
6507	43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs	---	6507	43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs	---
6508	0, // sub_64	---	6508	0, // sub_64	---
6509	0, // sub_dsp16_19	---	6509	0, // sub_dsp16_19	---
6510	0, // sub_dsp20	---	6510	0, // sub_dsp20	---
6511	0, // sub_dsp21	---	6511	0, // sub_dsp21	---
6512	0, // sub_dsp22	---	6512	0, // sub_dsp22	---
6513	0, // sub_dsp23	---	6513	0, // sub_dsp23	---
6514	0, // sub_hi	---	6514	0, // sub_hi	---
6515	0, // sub_lo	---	6515	0, // sub_lo	---
6516	0, // sub_hi_then_sub_32	---	6516	0, // sub_hi_then_sub_32	---
6517	0, // sub_32_sub_hi_then_sub_32	---	6517	0, // sub_32_sub_hi_then_sub_32	---
6518	},	---	6518	},	---
6519	{ // GPR64_with_sub_32_in_GPRMM16MoveP	---	6519	{ // GPR64_with_sub_32_in_GPRMM16MoveP	---
6520	44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP	---	6520	44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP	---
6521	0, // sub_64	---	6521	0, // sub_64	---
6522	0, // sub_dsp16_19	---	6522	0, // sub_dsp16_19	---
6523	0, // sub_dsp20	---	6523	0, // sub_dsp20	---
6524	0, // sub_dsp21	---	6524	0, // sub_dsp21	---
6525	0, // sub_dsp22	---	6525	0, // sub_dsp22	---
6526	0, // sub_dsp23	---	6526	0, // sub_dsp23	---
6527	0, // sub_hi	---	6527	0, // sub_hi	---
6528	0, // sub_lo	---	6528	0, // sub_lo	---
6529	0, // sub_hi_then_sub_32	---	6529	0, // sub_hi_then_sub_32	---
6530	0, // sub_32_sub_hi_then_sub_32	---	6530	0, // sub_32_sub_hi_then_sub_32	---
6531	},	---	6531	},	---
6532	{ // GPR64_with_sub_32_in_GPRMM16Zero	---	6532	{ // GPR64_with_sub_32_in_GPRMM16Zero	---
6533	45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero	---	6533	45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero	---
6534	0, // sub_64	---	6534	0, // sub_64	---
6535	0, // sub_dsp16_19	---	6535	0, // sub_dsp16_19	---
6536	0, // sub_dsp20	---	6536	0, // sub_dsp20	---
6537	0, // sub_dsp21	---	6537	0, // sub_dsp21	---
6538	0, // sub_dsp22	---	6538	0, // sub_dsp22	---
6539	0, // sub_dsp23	---	6539	0, // sub_dsp23	---
6540	0, // sub_hi	---	6540	0, // sub_hi	---
6541	0, // sub_lo	---	6541	0, // sub_lo	---
6542	0, // sub_hi_then_sub_32	---	6542	0, // sub_hi_then_sub_32	---
6543	0, // sub_32_sub_hi_then_sub_32	---	6543	0, // sub_32_sub_hi_then_sub_32	---
6544	},	---	6544	},	---
6545	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---	6545	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---
6546	46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---	6546	46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---
6547	0, // sub_64	---	6547	0, // sub_64	---
6548	0, // sub_dsp16_19	---	6548	0, // sub_dsp16_19	---
6549	0, // sub_dsp20	---	6549	0, // sub_dsp20	---
6550	0, // sub_dsp21	---	6550	0, // sub_dsp21	---
6551	0, // sub_dsp22	---	6551	0, // sub_dsp22	---
6552	0, // sub_dsp23	---	6552	0, // sub_dsp23	---
6553	0, // sub_hi	---	6553	0, // sub_hi	---
6554	0, // sub_lo	---	6554	0, // sub_lo	---
6555	0, // sub_hi_then_sub_32	---	6555	0, // sub_hi_then_sub_32	---
6556	0, // sub_32_sub_hi_then_sub_32	---	6556	0, // sub_32_sub_hi_then_sub_32	---
6557	},	---	6557	},	---
6558	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---	6558	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---
6559	47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---	6559	47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---
6560	0, // sub_64	---	6560	0, // sub_64	---
6561	0, // sub_dsp16_19	---	6561	0, // sub_dsp16_19	---
6562	0, // sub_dsp20	---	6562	0, // sub_dsp20	---
6563	0, // sub_dsp21	---	6563	0, // sub_dsp21	---
6564	0, // sub_dsp22	---	6564	0, // sub_dsp22	---
6565	0, // sub_dsp23	---	6565	0, // sub_dsp23	---
6566	0, // sub_hi	---	6566	0, // sub_hi	---
6567	0, // sub_lo	---	6567	0, // sub_lo	---
6568	0, // sub_hi_then_sub_32	---	6568	0, // sub_hi_then_sub_32	---
6569	0, // sub_32_sub_hi_then_sub_32	---	6569	0, // sub_32_sub_hi_then_sub_32	---
6570	},	---	6570	},	---
6571	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---	6571	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---
6572	48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---	6572	48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---
6573	0, // sub_64	---	6573	0, // sub_64	---
6574	0, // sub_dsp16_19	---	6574	0, // sub_dsp16_19	---
6575	0, // sub_dsp20	---	6575	0, // sub_dsp20	---
6576	0, // sub_dsp21	---	6576	0, // sub_dsp21	---
6577	0, // sub_dsp22	---	6577	0, // sub_dsp22	---
6578	0, // sub_dsp23	---	6578	0, // sub_dsp23	---
6579	0, // sub_hi	---	6579	0, // sub_hi	---
6580	0, // sub_lo	---	6580	0, // sub_lo	---
6581	0, // sub_hi_then_sub_32	---	6581	0, // sub_hi_then_sub_32	---
6582	0, // sub_32_sub_hi_then_sub_32	---	6582	0, // sub_32_sub_hi_then_sub_32	---
6583	},	---	6583	},	---
6584	{ // ACC64DSP	---	6584	{ // ACC64DSP	---
6585	0, // sub_32	---	6585	0, // sub_32	---
6586	0, // sub_64	---	6586	0, // sub_64	---
6587	0, // sub_dsp16_19	---	6587	0, // sub_dsp16_19	---
6588	0, // sub_dsp20	---	6588	0, // sub_dsp20	---
6589	0, // sub_dsp21	---	6589	0, // sub_dsp21	---
6590	0, // sub_dsp22	---	6590	0, // sub_dsp22	---
6591	0, // sub_dsp23	---	6591	0, // sub_dsp23	---
6592	49, // sub_hi -> ACC64DSP	---	6592	49, // sub_hi -> ACC64DSP	---
6593	49, // sub_lo -> ACC64DSP	---	6593	49, // sub_lo -> ACC64DSP	---
6594	0, // sub_hi_then_sub_32	---	6594	0, // sub_hi_then_sub_32	---
6595	0, // sub_32_sub_hi_then_sub_32	---	6595	0, // sub_32_sub_hi_then_sub_32	---
6596	},	---	6596	},	---
6597	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---	6597	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---
6598	50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---	6598	50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---
6599	0, // sub_64	---	6599	0, // sub_64	---
6600	0, // sub_dsp16_19	---	6600	0, // sub_dsp16_19	---
6601	0, // sub_dsp20	---	6601	0, // sub_dsp20	---
6602	0, // sub_dsp21	---	6602	0, // sub_dsp21	---
6603	0, // sub_dsp22	---	6603	0, // sub_dsp22	---
6604	0, // sub_dsp23	---	6604	0, // sub_dsp23	---
6605	0, // sub_hi	---	6605	0, // sub_hi	---
6606	0, // sub_lo	---	6606	0, // sub_lo	---
6607	0, // sub_hi_then_sub_32	---	6607	0, // sub_hi_then_sub_32	---
6608	0, // sub_32_sub_hi_then_sub_32	---	6608	0, // sub_32_sub_hi_then_sub_32	---
6609	},	---	6609	},	---
6610	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---	6610	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---
6611	51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---	6611	51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---
6612	0, // sub_64	---	6612	0, // sub_64	---
6613	0, // sub_dsp16_19	---	6613	0, // sub_dsp16_19	---
6614	0, // sub_dsp20	---	6614	0, // sub_dsp20	---
6615	0, // sub_dsp21	---	6615	0, // sub_dsp21	---
6616	0, // sub_dsp22	---	6616	0, // sub_dsp22	---
6617	0, // sub_dsp23	---	6617	0, // sub_dsp23	---
6618	0, // sub_hi	---	6618	0, // sub_hi	---
6619	0, // sub_lo	---	6619	0, // sub_lo	---
6620	0, // sub_hi_then_sub_32	---	6620	0, // sub_hi_then_sub_32	---
6621	0, // sub_32_sub_hi_then_sub_32	---	6621	0, // sub_32_sub_hi_then_sub_32	---
6622	},	---	6622	},	---
6623	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---	6623	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---
6624	52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---	6624	52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---
6625	0, // sub_64	---	6625	0, // sub_64	---
6626	0, // sub_dsp16_19	---	6626	0, // sub_dsp16_19	---
6627	0, // sub_dsp20	---	6627	0, // sub_dsp20	---
6628	0, // sub_dsp21	---	6628	0, // sub_dsp21	---
6629	0, // sub_dsp22	---	6629	0, // sub_dsp22	---
6630	0, // sub_dsp23	---	6630	0, // sub_dsp23	---
6631	0, // sub_hi	---	6631	0, // sub_hi	---
6632	0, // sub_lo	---	6632	0, // sub_lo	---
6633	0, // sub_hi_then_sub_32	---	6633	0, // sub_hi_then_sub_32	---
6634	0, // sub_32_sub_hi_then_sub_32	---	6634	0, // sub_32_sub_hi_then_sub_32	---
6635	},	---	6635	},	---
6636	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---	6636	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---
6637	53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---	6637	53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---
6638	0, // sub_64	---	6638	0, // sub_64	---
6639	0, // sub_dsp16_19	---	6639	0, // sub_dsp16_19	---
6640	0, // sub_dsp20	---	6640	0, // sub_dsp20	---
6641	0, // sub_dsp21	---	6641	0, // sub_dsp21	---
6642	0, // sub_dsp22	---	6642	0, // sub_dsp22	---
6643	0, // sub_dsp23	---	6643	0, // sub_dsp23	---
6644	0, // sub_hi	---	6644	0, // sub_hi	---
6645	0, // sub_lo	---	6645	0, // sub_lo	---
6646	0, // sub_hi_then_sub_32	---	6646	0, // sub_hi_then_sub_32	---
6647	0, // sub_32_sub_hi_then_sub_32	---	6647	0, // sub_32_sub_hi_then_sub_32	---
6648	},	---	6648	},	---
6649	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	6649	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
6650	54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	6650	54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
6651	0, // sub_64	---	6651	0, // sub_64	---
6652	0, // sub_dsp16_19	---	6652	0, // sub_dsp16_19	---
6653	0, // sub_dsp20	---	6653	0, // sub_dsp20	---
6654	0, // sub_dsp21	---	6654	0, // sub_dsp21	---
6655	0, // sub_dsp22	---	6655	0, // sub_dsp22	---
6656	0, // sub_dsp23	---	6656	0, // sub_dsp23	---
6657	0, // sub_hi	---	6657	0, // sub_hi	---
6658	0, // sub_lo	---	6658	0, // sub_lo	---
6659	0, // sub_hi_then_sub_32	---	6659	0, // sub_hi_then_sub_32	---
6660	0, // sub_32_sub_hi_then_sub_32	---	6660	0, // sub_32_sub_hi_then_sub_32	---
6661	},	---	6661	},	---
6662	{ // OCTEON_MPL	---	6662	{ // OCTEON_MPL	---
6663	0, // sub_32	---	6663	0, // sub_32	---
6664	0, // sub_64	---	6664	0, // sub_64	---
6665	0, // sub_dsp16_19	---	6665	0, // sub_dsp16_19	---
6666	0, // sub_dsp20	---	6666	0, // sub_dsp20	---
6667	0, // sub_dsp21	---	6667	0, // sub_dsp21	---
6668	0, // sub_dsp22	---	6668	0, // sub_dsp22	---
6669	0, // sub_dsp23	---	6669	0, // sub_dsp23	---
6670	0, // sub_hi	---	6670	0, // sub_hi	---
6671	0, // sub_lo	---	6671	0, // sub_lo	---
6672	0, // sub_hi_then_sub_32	---	6672	0, // sub_hi_then_sub_32	---
6673	0, // sub_32_sub_hi_then_sub_32	---	6673	0, // sub_32_sub_hi_then_sub_32	---
6674	},	---	6674	},	---
6675	{ // OCTEON_P	---	6675	{ // OCTEON_P	---
6676	0, // sub_32	---	6676	0, // sub_32	---
6677	0, // sub_64	---	6677	0, // sub_64	---
6678	0, // sub_dsp16_19	---	6678	0, // sub_dsp16_19	---
6679	0, // sub_dsp20	---	6679	0, // sub_dsp20	---
6680	0, // sub_dsp21	---	6680	0, // sub_dsp21	---
6681	0, // sub_dsp22	---	6681	0, // sub_dsp22	---
6682	0, // sub_dsp23	---	6682	0, // sub_dsp23	---
6683	0, // sub_hi	---	6683	0, // sub_hi	---
6684	0, // sub_lo	---	6684	0, // sub_lo	---
6685	0, // sub_hi_then_sub_32	---	6685	0, // sub_hi_then_sub_32	---
6686	0, // sub_32_sub_hi_then_sub_32	---	6686	0, // sub_32_sub_hi_then_sub_32	---
6687	},	---	6687	},	---
6688	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	6688	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
6689	57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	6689	57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
6690	0, // sub_64	---	6690	0, // sub_64	---
6691	0, // sub_dsp16_19	---	6691	0, // sub_dsp16_19	---
6692	0, // sub_dsp20	---	6692	0, // sub_dsp20	---
6693	0, // sub_dsp21	---	6693	0, // sub_dsp21	---
6694	0, // sub_dsp22	---	6694	0, // sub_dsp22	---
6695	0, // sub_dsp23	---	6695	0, // sub_dsp23	---
6696	0, // sub_hi	---	6696	0, // sub_hi	---
6697	0, // sub_lo	---	6697	0, // sub_lo	---
6698	0, // sub_hi_then_sub_32	---	6698	0, // sub_hi_then_sub_32	---
6699	0, // sub_32_sub_hi_then_sub_32	---	6699	0, // sub_32_sub_hi_then_sub_32	---
6700	},	---	6700	},	---
6701	{ // ACC64	---	6701	{ // ACC64	---
6702	0, // sub_32	---	6702	0, // sub_32	---
6703	0, // sub_64	---	6703	0, // sub_64	---
6704	0, // sub_dsp16_19	---	6704	0, // sub_dsp16_19	---
6705	0, // sub_dsp20	---	6705	0, // sub_dsp20	---
6706	0, // sub_dsp21	---	6706	0, // sub_dsp21	---
6707	0, // sub_dsp22	---	6707	0, // sub_dsp22	---
6708	0, // sub_dsp23	---	6708	0, // sub_dsp23	---
6709	58, // sub_hi -> ACC64	---	6709	58, // sub_hi -> ACC64	---
6710	58, // sub_lo -> ACC64	---	6710	58, // sub_lo -> ACC64	---
6711	0, // sub_hi_then_sub_32	---	6711	0, // sub_hi_then_sub_32	---
6712	0, // sub_32_sub_hi_then_sub_32	---	6712	0, // sub_32_sub_hi_then_sub_32	---
6713	},	---	6713	},	---
6714	{ // GP64	---	6714	{ // GP64	---
6715	59, // sub_32 -> GP64	---	6715	59, // sub_32 -> GP64	---
6716	0, // sub_64	---	6716	0, // sub_64	---
6717	0, // sub_dsp16_19	---	6717	0, // sub_dsp16_19	---
6718	0, // sub_dsp20	---	6718	0, // sub_dsp20	---
6719	0, // sub_dsp21	---	6719	0, // sub_dsp21	---
6720	0, // sub_dsp22	---	6720	0, // sub_dsp22	---
6721	0, // sub_dsp23	---	6721	0, // sub_dsp23	---
6722	0, // sub_hi	---	6722	0, // sub_hi	---
6723	0, // sub_lo	---	6723	0, // sub_lo	---
6724	0, // sub_hi_then_sub_32	---	6724	0, // sub_hi_then_sub_32	---
6725	0, // sub_32_sub_hi_then_sub_32	---	6725	0, // sub_32_sub_hi_then_sub_32	---
6726	},	---	6726	},	---
6727	{ // GPR64_with_sub_32_in_CPURAReg	---	6727	{ // GPR64_with_sub_32_in_CPURAReg	---
6728	60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg	---	6728	60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg	---
6729	0, // sub_64	---	6729	0, // sub_64	---
6730	0, // sub_dsp16_19	---	6730	0, // sub_dsp16_19	---
6731	0, // sub_dsp20	---	6731	0, // sub_dsp20	---
6732	0, // sub_dsp21	---	6732	0, // sub_dsp21	---
6733	0, // sub_dsp22	---	6733	0, // sub_dsp22	---
6734	0, // sub_dsp23	---	6734	0, // sub_dsp23	---
6735	0, // sub_hi	---	6735	0, // sub_hi	---
6736	0, // sub_lo	---	6736	0, // sub_lo	---
6737	0, // sub_hi_then_sub_32	---	6737	0, // sub_hi_then_sub_32	---
6738	0, // sub_32_sub_hi_then_sub_32	---	6738	0, // sub_32_sub_hi_then_sub_32	---
6739	},	---	6739	},	---
6740	{ // GPR64_with_sub_32_in_GPR32ZERO	---	6740	{ // GPR64_with_sub_32_in_GPR32ZERO	---
6741	61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO	---	6741	61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO	---
6742	0, // sub_64	---	6742	0, // sub_64	---
6743	0, // sub_dsp16_19	---	6743	0, // sub_dsp16_19	---
6744	0, // sub_dsp20	---	6744	0, // sub_dsp20	---
6745	0, // sub_dsp21	---	6745	0, // sub_dsp21	---
6746	0, // sub_dsp22	---	6746	0, // sub_dsp22	---
6747	0, // sub_dsp23	---	6747	0, // sub_dsp23	---
6748	0, // sub_hi	---	6748	0, // sub_hi	---
6749	0, // sub_lo	---	6749	0, // sub_lo	---
6750	0, // sub_hi_then_sub_32	---	6750	0, // sub_hi_then_sub_32	---
6751	0, // sub_32_sub_hi_then_sub_32	---	6751	0, // sub_32_sub_hi_then_sub_32	---
6752	},	---	6752	},	---
6753	{ // HI64	---	6753	{ // HI64	---
6754	62, // sub_32 -> HI64	---	6754	62, // sub_32 -> HI64	---
6755	0, // sub_64	---	6755	0, // sub_64	---
6756	0, // sub_dsp16_19	---	6756	0, // sub_dsp16_19	---
6757	0, // sub_dsp20	---	6757	0, // sub_dsp20	---
6758	0, // sub_dsp21	---	6758	0, // sub_dsp21	---
6759	0, // sub_dsp22	---	6759	0, // sub_dsp22	---
6760	0, // sub_dsp23	---	6760	0, // sub_dsp23	---
6761	0, // sub_hi	---	6761	0, // sub_hi	---
6762	0, // sub_lo	---	6762	0, // sub_lo	---
6763	0, // sub_hi_then_sub_32	---	6763	0, // sub_hi_then_sub_32	---
6764	0, // sub_32_sub_hi_then_sub_32	---	6764	0, // sub_32_sub_hi_then_sub_32	---
6765	},	---	6765	},	---
6766	{ // LO64	---	6766	{ // LO64	---
6767	63, // sub_32 -> LO64	---	6767	63, // sub_32 -> LO64	---
6768	0, // sub_64	---	6768	0, // sub_64	---
6769	0, // sub_dsp16_19	---	6769	0, // sub_dsp16_19	---
6770	0, // sub_dsp20	---	6770	0, // sub_dsp20	---
6771	0, // sub_dsp21	---	6771	0, // sub_dsp21	---
6772	0, // sub_dsp22	---	6772	0, // sub_dsp22	---
6773	0, // sub_dsp23	---	6773	0, // sub_dsp23	---
6774	0, // sub_hi	---	6774	0, // sub_hi	---
6775	0, // sub_lo	---	6775	0, // sub_lo	---
6776	0, // sub_hi_then_sub_32	---	6776	0, // sub_hi_then_sub_32	---
6777	0, // sub_32_sub_hi_then_sub_32	---	6777	0, // sub_32_sub_hi_then_sub_32	---
6778	},	---	6778	},	---
6779	{ // SP64	---	6779	{ // SP64	---
6780	64, // sub_32 -> SP64	---	6780	64, // sub_32 -> SP64	---
6781	0, // sub_64	---	6781	0, // sub_64	---
6782	0, // sub_dsp16_19	---	6782	0, // sub_dsp16_19	---
6783	0, // sub_dsp20	---	6783	0, // sub_dsp20	---
6784	0, // sub_dsp21	---	6784	0, // sub_dsp21	---
6785	0, // sub_dsp22	---	6785	0, // sub_dsp22	---
6786	0, // sub_dsp23	---	6786	0, // sub_dsp23	---
6787	0, // sub_hi	---	6787	0, // sub_hi	---
6788	0, // sub_lo	---	6788	0, // sub_lo	---
6789	0, // sub_hi_then_sub_32	---	6789	0, // sub_hi_then_sub_32	---
6790	0, // sub_32_sub_hi_then_sub_32	---	6790	0, // sub_32_sub_hi_then_sub_32	---
6791	},	---	6791	},	---
6792	{ // MSA128B	---	6792	{ // MSA128B	---
6793	0, // sub_32	---	6793	0, // sub_32	---
6794	65, // sub_64 -> MSA128B	---	6794	65, // sub_64 -> MSA128B	---
6795	0, // sub_dsp16_19	---	6795	0, // sub_dsp16_19	---
6796	0, // sub_dsp20	---	6796	0, // sub_dsp20	---
6797	0, // sub_dsp21	---	6797	0, // sub_dsp21	---
6798	0, // sub_dsp22	---	6798	0, // sub_dsp22	---
6799	0, // sub_dsp23	---	6799	0, // sub_dsp23	---
6800	65, // sub_hi -> MSA128B	---	6800	65, // sub_hi -> MSA128B	---
6801	65, // sub_lo -> MSA128B	---	6801	65, // sub_lo -> MSA128B	---
6802	0, // sub_hi_then_sub_32	---	6802	0, // sub_hi_then_sub_32	---
6803	0, // sub_32_sub_hi_then_sub_32	---	6803	0, // sub_32_sub_hi_then_sub_32	---
6804	},	---	6804	},	---
6805	{ // MSA128D	---	6805	{ // MSA128D	---
6806	0, // sub_32	---	6806	0, // sub_32	---
6807	66, // sub_64 -> MSA128D	---	6807	66, // sub_64 -> MSA128D	---
6808	0, // sub_dsp16_19	---	6808	0, // sub_dsp16_19	---
6809	0, // sub_dsp20	---	6809	0, // sub_dsp20	---
6810	0, // sub_dsp21	---	6810	0, // sub_dsp21	---
6811	0, // sub_dsp22	---	6811	0, // sub_dsp22	---
6812	0, // sub_dsp23	---	6812	0, // sub_dsp23	---
6813	66, // sub_hi -> MSA128D	---	6813	66, // sub_hi -> MSA128D	---
6814	66, // sub_lo -> MSA128D	---	6814	66, // sub_lo -> MSA128D	---
6815	0, // sub_hi_then_sub_32	---	6815	0, // sub_hi_then_sub_32	---
6816	0, // sub_32_sub_hi_then_sub_32	---	6816	0, // sub_32_sub_hi_then_sub_32	---
6817	},	---	6817	},	---
6818	{ // MSA128H	---	6818	{ // MSA128H	---
6819	0, // sub_32	---	6819	0, // sub_32	---
6820	67, // sub_64 -> MSA128H	---	6820	67, // sub_64 -> MSA128H	---
6821	0, // sub_dsp16_19	---	6821	0, // sub_dsp16_19	---
6822	0, // sub_dsp20	---	6822	0, // sub_dsp20	---
6823	0, // sub_dsp21	---	6823	0, // sub_dsp21	---
6824	0, // sub_dsp22	---	6824	0, // sub_dsp22	---
6825	0, // sub_dsp23	---	6825	0, // sub_dsp23	---
6826	67, // sub_hi -> MSA128H	---	6826	67, // sub_hi -> MSA128H	---
6827	67, // sub_lo -> MSA128H	---	6827	67, // sub_lo -> MSA128H	---
6828	0, // sub_hi_then_sub_32	---	6828	0, // sub_hi_then_sub_32	---
6829	0, // sub_32_sub_hi_then_sub_32	---	6829	0, // sub_32_sub_hi_then_sub_32	---
6830	},	---	6830	},	---
6831	{ // MSA128W	---	6831	{ // MSA128W	---
6832	0, // sub_32	---	6832	0, // sub_32	---
6833	68, // sub_64 -> MSA128W	---	6833	68, // sub_64 -> MSA128W	---
6834	0, // sub_dsp16_19	---	6834	0, // sub_dsp16_19	---
6835	0, // sub_dsp20	---	6835	0, // sub_dsp20	---
6836	0, // sub_dsp21	---	6836	0, // sub_dsp21	---
6837	0, // sub_dsp22	---	6837	0, // sub_dsp22	---
6838	0, // sub_dsp23	---	6838	0, // sub_dsp23	---
6839	68, // sub_hi -> MSA128W	---	6839	68, // sub_hi -> MSA128W	---
6840	68, // sub_lo -> MSA128W	---	6840	68, // sub_lo -> MSA128W	---
6841	0, // sub_hi_then_sub_32	---	6841	0, // sub_hi_then_sub_32	---
6842	0, // sub_32_sub_hi_then_sub_32	---	6842	0, // sub_32_sub_hi_then_sub_32	---
6843	},	---	6843	},	---
6844	{ // MSA128WEvens	---	6844	{ // MSA128WEvens	---
6845	0, // sub_32	---	6845	0, // sub_32	---
6846	69, // sub_64 -> MSA128WEvens	---	6846	69, // sub_64 -> MSA128WEvens	---
6847	0, // sub_dsp16_19	---	6847	0, // sub_dsp16_19	---
6848	0, // sub_dsp20	---	6848	0, // sub_dsp20	---
6849	0, // sub_dsp21	---	6849	0, // sub_dsp21	---
6850	0, // sub_dsp22	---	6850	0, // sub_dsp22	---
6851	0, // sub_dsp23	---	6851	0, // sub_dsp23	---
6852	69, // sub_hi -> MSA128WEvens	---	6852	69, // sub_hi -> MSA128WEvens	---
6853	69, // sub_lo -> MSA128WEvens	---	6853	69, // sub_lo -> MSA128WEvens	---
6854	0, // sub_hi_then_sub_32	---	6854	0, // sub_hi_then_sub_32	---
6855	0, // sub_32_sub_hi_then_sub_32	---	6855	0, // sub_32_sub_hi_then_sub_32	---
6856	},	---	6856	},	---
6857	{ // ACC128	---	6857	{ // ACC128	---
6858	70, // sub_32 -> ACC128	---	6858	70, // sub_32 -> ACC128	---
6859	0, // sub_64	---	6859	0, // sub_64	---
6860	0, // sub_dsp16_19	---	6860	0, // sub_dsp16_19	---
6861	0, // sub_dsp20	---	6861	0, // sub_dsp20	---
6862	0, // sub_dsp21	---	6862	0, // sub_dsp21	---
6863	0, // sub_dsp22	---	6863	0, // sub_dsp22	---
6864	0, // sub_dsp23	---	6864	0, // sub_dsp23	---
6865	70, // sub_hi -> ACC128	---	6865	70, // sub_hi -> ACC128	---
6866	70, // sub_lo -> ACC128	---	6866	70, // sub_lo -> ACC128	---
6867	70, // sub_hi_then_sub_32 -> ACC128	---	6867	70, // sub_hi_then_sub_32 -> ACC128	---
6868	70, // sub_32_sub_hi_then_sub_32 -> ACC128	---	6868	70, // sub_32_sub_hi_then_sub_32 -> ACC128	---
6869	},	---	6869	},	---
6870	};	---	6870	};	---
6871	assert(RC && "Missing regclass");	0	6871	assert(RC && "Missing regclass");	0
6872	if (!Idx) return RC;	0	6872	if (!Idx) return RC;	0
6873	--Idx;	0	6873	--Idx;	0
6874	assert(Idx < 11 && "Bad subreg");	0	6874	assert(Idx < 11 && "Bad subreg");	0
6875	unsigned TV = Table[RC->getID()][Idx];	0	6875	unsigned TV = Table[RC->getID()][Idx];	0
6876	return TV ? getRegClass(TV - 1) : nullptr;	0	6876	return TV ? getRegClass(TV - 1) : nullptr;	0
6877	}	---	6877	}	---
6878		---	6878		---
6879	const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {	0	6879	const TargetRegisterClass MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass RC, unsigned Idx) const {	0
6880	static const uint8_t Table[70][11] = {	---	6880	static const uint8_t Table[70][11] = {	---
6881	{ // MSA128F16	---	6881	{ // MSA128F16	---
6882	0, // MSA128F16:sub_32	---	6882	0, // MSA128F16:sub_32	---
6883	38, // MSA128F16:sub_64 -> FGR64	---	6883	38, // MSA128F16:sub_64 -> FGR64	---
6884	0, // MSA128F16:sub_dsp16_19	---	6884	0, // MSA128F16:sub_dsp16_19	---
6885	0, // MSA128F16:sub_dsp20	---	6885	0, // MSA128F16:sub_dsp20	---
6886	0, // MSA128F16:sub_dsp21	---	6886	0, // MSA128F16:sub_dsp21	---
6887	0, // MSA128F16:sub_dsp22	---	6887	0, // MSA128F16:sub_dsp22	---
6888	0, // MSA128F16:sub_dsp23	---	6888	0, // MSA128F16:sub_dsp23	---
6889	0, // MSA128F16:sub_hi	---	6889	0, // MSA128F16:sub_hi	---
6890	7, // MSA128F16:sub_lo -> FGR32	---	6890	7, // MSA128F16:sub_lo -> FGR32	---
6891	0, // MSA128F16:sub_hi_then_sub_32	---	6891	0, // MSA128F16:sub_hi_then_sub_32	---
6892	0, // MSA128F16:sub_32_sub_hi_then_sub_32	---	6892	0, // MSA128F16:sub_32_sub_hi_then_sub_32	---
6893	},	---	6893	},	---
6894	{ // CCR	---	6894	{ // CCR	---
6895	0, // CCR:sub_32	---	6895	0, // CCR:sub_32	---
6896	0, // CCR:sub_64	---	6896	0, // CCR:sub_64	---
6897	0, // CCR:sub_dsp16_19	---	6897	0, // CCR:sub_dsp16_19	---
6898	0, // CCR:sub_dsp20	---	6898	0, // CCR:sub_dsp20	---
6899	0, // CCR:sub_dsp21	---	6899	0, // CCR:sub_dsp21	---
6900	0, // CCR:sub_dsp22	---	6900	0, // CCR:sub_dsp22	---
6901	0, // CCR:sub_dsp23	---	6901	0, // CCR:sub_dsp23	---
6902	0, // CCR:sub_hi	---	6902	0, // CCR:sub_hi	---
6903	0, // CCR:sub_lo	---	6903	0, // CCR:sub_lo	---
6904	0, // CCR:sub_hi_then_sub_32	---	6904	0, // CCR:sub_hi_then_sub_32	---
6905	0, // CCR:sub_32_sub_hi_then_sub_32	---	6905	0, // CCR:sub_32_sub_hi_then_sub_32	---
6906	},	---	6906	},	---
6907	{ // COP0	---	6907	{ // COP0	---
6908	0, // COP0:sub_32	---	6908	0, // COP0:sub_32	---
6909	0, // COP0:sub_64	---	6909	0, // COP0:sub_64	---
6910	0, // COP0:sub_dsp16_19	---	6910	0, // COP0:sub_dsp16_19	---
6911	0, // COP0:sub_dsp20	---	6911	0, // COP0:sub_dsp20	---
6912	0, // COP0:sub_dsp21	---	6912	0, // COP0:sub_dsp21	---
6913	0, // COP0:sub_dsp22	---	6913	0, // COP0:sub_dsp22	---
6914	0, // COP0:sub_dsp23	---	6914	0, // COP0:sub_dsp23	---
6915	0, // COP0:sub_hi	---	6915	0, // COP0:sub_hi	---
6916	0, // COP0:sub_lo	---	6916	0, // COP0:sub_lo	---
6917	0, // COP0:sub_hi_then_sub_32	---	6917	0, // COP0:sub_hi_then_sub_32	---
6918	0, // COP0:sub_32_sub_hi_then_sub_32	---	6918	0, // COP0:sub_32_sub_hi_then_sub_32	---
6919	},	---	6919	},	---
6920	{ // COP2	---	6920	{ // COP2	---
6921	0, // COP2:sub_32	---	6921	0, // COP2:sub_32	---
6922	0, // COP2:sub_64	---	6922	0, // COP2:sub_64	---
6923	0, // COP2:sub_dsp16_19	---	6923	0, // COP2:sub_dsp16_19	---
6924	0, // COP2:sub_dsp20	---	6924	0, // COP2:sub_dsp20	---
6925	0, // COP2:sub_dsp21	---	6925	0, // COP2:sub_dsp21	---
6926	0, // COP2:sub_dsp22	---	6926	0, // COP2:sub_dsp22	---
6927	0, // COP2:sub_dsp23	---	6927	0, // COP2:sub_dsp23	---
6928	0, // COP2:sub_hi	---	6928	0, // COP2:sub_hi	---
6929	0, // COP2:sub_lo	---	6929	0, // COP2:sub_lo	---
6930	0, // COP2:sub_hi_then_sub_32	---	6930	0, // COP2:sub_hi_then_sub_32	---
6931	0, // COP2:sub_32_sub_hi_then_sub_32	---	6931	0, // COP2:sub_32_sub_hi_then_sub_32	---
6932	},	---	6932	},	---
6933	{ // COP3	---	6933	{ // COP3	---
6934	0, // COP3:sub_32	---	6934	0, // COP3:sub_32	---
6935	0, // COP3:sub_64	---	6935	0, // COP3:sub_64	---
6936	0, // COP3:sub_dsp16_19	---	6936	0, // COP3:sub_dsp16_19	---
6937	0, // COP3:sub_dsp20	---	6937	0, // COP3:sub_dsp20	---
6938	0, // COP3:sub_dsp21	---	6938	0, // COP3:sub_dsp21	---
6939	0, // COP3:sub_dsp22	---	6939	0, // COP3:sub_dsp22	---
6940	0, // COP3:sub_dsp23	---	6940	0, // COP3:sub_dsp23	---
6941	0, // COP3:sub_hi	---	6941	0, // COP3:sub_hi	---
6942	0, // COP3:sub_lo	---	6942	0, // COP3:sub_lo	---
6943	0, // COP3:sub_hi_then_sub_32	---	6943	0, // COP3:sub_hi_then_sub_32	---
6944	0, // COP3:sub_32_sub_hi_then_sub_32	---	6944	0, // COP3:sub_32_sub_hi_then_sub_32	---
6945	},	---	6945	},	---
6946	{ // DSPR	---	6946	{ // DSPR	---
6947	0, // DSPR:sub_32	---	6947	0, // DSPR:sub_32	---
6948	0, // DSPR:sub_64	---	6948	0, // DSPR:sub_64	---
6949	0, // DSPR:sub_dsp16_19	---	6949	0, // DSPR:sub_dsp16_19	---
6950	0, // DSPR:sub_dsp20	---	6950	0, // DSPR:sub_dsp20	---
6951	0, // DSPR:sub_dsp21	---	6951	0, // DSPR:sub_dsp21	---
6952	0, // DSPR:sub_dsp22	---	6952	0, // DSPR:sub_dsp22	---
6953	0, // DSPR:sub_dsp23	---	6953	0, // DSPR:sub_dsp23	---
6954	0, // DSPR:sub_hi	---	6954	0, // DSPR:sub_hi	---
6955	0, // DSPR:sub_lo	---	6955	0, // DSPR:sub_lo	---
6956	0, // DSPR:sub_hi_then_sub_32	---	6956	0, // DSPR:sub_hi_then_sub_32	---
6957	0, // DSPR:sub_32_sub_hi_then_sub_32	---	6957	0, // DSPR:sub_32_sub_hi_then_sub_32	---
6958	},	---	6958	},	---
6959	{ // FGR32	---	6959	{ // FGR32	---
6960	0, // FGR32:sub_32	---	6960	0, // FGR32:sub_32	---
6961	0, // FGR32:sub_64	---	6961	0, // FGR32:sub_64	---
6962	0, // FGR32:sub_dsp16_19	---	6962	0, // FGR32:sub_dsp16_19	---
6963	0, // FGR32:sub_dsp20	---	6963	0, // FGR32:sub_dsp20	---
6964	0, // FGR32:sub_dsp21	---	6964	0, // FGR32:sub_dsp21	---
6965	0, // FGR32:sub_dsp22	---	6965	0, // FGR32:sub_dsp22	---
6966	0, // FGR32:sub_dsp23	---	6966	0, // FGR32:sub_dsp23	---
6967	0, // FGR32:sub_hi	---	6967	0, // FGR32:sub_hi	---
6968	0, // FGR32:sub_lo	---	6968	0, // FGR32:sub_lo	---
6969	0, // FGR32:sub_hi_then_sub_32	---	6969	0, // FGR32:sub_hi_then_sub_32	---
6970	0, // FGR32:sub_32_sub_hi_then_sub_32	---	6970	0, // FGR32:sub_32_sub_hi_then_sub_32	---
6971	},	---	6971	},	---
6972	{ // FGRCC	---	6972	{ // FGRCC	---
6973	0, // FGRCC:sub_32	---	6973	0, // FGRCC:sub_32	---
6974	0, // FGRCC:sub_64	---	6974	0, // FGRCC:sub_64	---
6975	0, // FGRCC:sub_dsp16_19	---	6975	0, // FGRCC:sub_dsp16_19	---
6976	0, // FGRCC:sub_dsp20	---	6976	0, // FGRCC:sub_dsp20	---
6977	0, // FGRCC:sub_dsp21	---	6977	0, // FGRCC:sub_dsp21	---
6978	0, // FGRCC:sub_dsp22	---	6978	0, // FGRCC:sub_dsp22	---
6979	0, // FGRCC:sub_dsp23	---	6979	0, // FGRCC:sub_dsp23	---
6980	0, // FGRCC:sub_hi	---	6980	0, // FGRCC:sub_hi	---
6981	0, // FGRCC:sub_lo	---	6981	0, // FGRCC:sub_lo	---
6982	0, // FGRCC:sub_hi_then_sub_32	---	6982	0, // FGRCC:sub_hi_then_sub_32	---
6983	0, // FGRCC:sub_32_sub_hi_then_sub_32	---	6983	0, // FGRCC:sub_32_sub_hi_then_sub_32	---
6984	},	---	6984	},	---
6985	{ // GPR32	---	6985	{ // GPR32	---
6986	0, // GPR32:sub_32	---	6986	0, // GPR32:sub_32	---
6987	0, // GPR32:sub_64	---	6987	0, // GPR32:sub_64	---
6988	0, // GPR32:sub_dsp16_19	---	6988	0, // GPR32:sub_dsp16_19	---
6989	0, // GPR32:sub_dsp20	---	6989	0, // GPR32:sub_dsp20	---
6990	0, // GPR32:sub_dsp21	---	6990	0, // GPR32:sub_dsp21	---
6991	0, // GPR32:sub_dsp22	---	6991	0, // GPR32:sub_dsp22	---
6992	0, // GPR32:sub_dsp23	---	6992	0, // GPR32:sub_dsp23	---
6993	0, // GPR32:sub_hi	---	6993	0, // GPR32:sub_hi	---
6994	0, // GPR32:sub_lo	---	6994	0, // GPR32:sub_lo	---
6995	0, // GPR32:sub_hi_then_sub_32	---	6995	0, // GPR32:sub_hi_then_sub_32	---
6996	0, // GPR32:sub_32_sub_hi_then_sub_32	---	6996	0, // GPR32:sub_32_sub_hi_then_sub_32	---
6997	},	---	6997	},	---
6998	{ // HWRegs	---	6998	{ // HWRegs	---
6999	0, // HWRegs:sub_32	---	6999	0, // HWRegs:sub_32	---
7000	0, // HWRegs:sub_64	---	7000	0, // HWRegs:sub_64	---
7001	0, // HWRegs:sub_dsp16_19	---	7001	0, // HWRegs:sub_dsp16_19	---
7002	0, // HWRegs:sub_dsp20	---	7002	0, // HWRegs:sub_dsp20	---
7003	0, // HWRegs:sub_dsp21	---	7003	0, // HWRegs:sub_dsp21	---
7004	0, // HWRegs:sub_dsp22	---	7004	0, // HWRegs:sub_dsp22	---
7005	0, // HWRegs:sub_dsp23	---	7005	0, // HWRegs:sub_dsp23	---
7006	0, // HWRegs:sub_hi	---	7006	0, // HWRegs:sub_hi	---
7007	0, // HWRegs:sub_lo	---	7007	0, // HWRegs:sub_lo	---
7008	0, // HWRegs:sub_hi_then_sub_32	---	7008	0, // HWRegs:sub_hi_then_sub_32	---
7009	0, // HWRegs:sub_32_sub_hi_then_sub_32	---	7009	0, // HWRegs:sub_32_sub_hi_then_sub_32	---
7010	},	---	7010	},	---
7011	{ // MSACtrl	---	7011	{ // MSACtrl	---
7012	0, // MSACtrl:sub_32	---	7012	0, // MSACtrl:sub_32	---
7013	0, // MSACtrl:sub_64	---	7013	0, // MSACtrl:sub_64	---
7014	0, // MSACtrl:sub_dsp16_19	---	7014	0, // MSACtrl:sub_dsp16_19	---
7015	0, // MSACtrl:sub_dsp20	---	7015	0, // MSACtrl:sub_dsp20	---
7016	0, // MSACtrl:sub_dsp21	---	7016	0, // MSACtrl:sub_dsp21	---
7017	0, // MSACtrl:sub_dsp22	---	7017	0, // MSACtrl:sub_dsp22	---
7018	0, // MSACtrl:sub_dsp23	---	7018	0, // MSACtrl:sub_dsp23	---
7019	0, // MSACtrl:sub_hi	---	7019	0, // MSACtrl:sub_hi	---
7020	0, // MSACtrl:sub_lo	---	7020	0, // MSACtrl:sub_lo	---
7021	0, // MSACtrl:sub_hi_then_sub_32	---	7021	0, // MSACtrl:sub_hi_then_sub_32	---
7022	0, // MSACtrl:sub_32_sub_hi_then_sub_32	---	7022	0, // MSACtrl:sub_32_sub_hi_then_sub_32	---
7023	},	---	7023	},	---
7024	{ // GPR32NONZERO	---	7024	{ // GPR32NONZERO	---
7025	0, // GPR32NONZERO:sub_32	---	7025	0, // GPR32NONZERO:sub_32	---
7026	0, // GPR32NONZERO:sub_64	---	7026	0, // GPR32NONZERO:sub_64	---
7027	0, // GPR32NONZERO:sub_dsp16_19	---	7027	0, // GPR32NONZERO:sub_dsp16_19	---
7028	0, // GPR32NONZERO:sub_dsp20	---	7028	0, // GPR32NONZERO:sub_dsp20	---
7029	0, // GPR32NONZERO:sub_dsp21	---	7029	0, // GPR32NONZERO:sub_dsp21	---
7030	0, // GPR32NONZERO:sub_dsp22	---	7030	0, // GPR32NONZERO:sub_dsp22	---
7031	0, // GPR32NONZERO:sub_dsp23	---	7031	0, // GPR32NONZERO:sub_dsp23	---
7032	0, // GPR32NONZERO:sub_hi	---	7032	0, // GPR32NONZERO:sub_hi	---
7033	0, // GPR32NONZERO:sub_lo	---	7033	0, // GPR32NONZERO:sub_lo	---
7034	0, // GPR32NONZERO:sub_hi_then_sub_32	---	7034	0, // GPR32NONZERO:sub_hi_then_sub_32	---
7035	0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32	---	7035	0, // GPR32NONZERO:sub_32_sub_hi_then_sub_32	---
7036	},	---	7036	},	---
7037	{ // CPU16RegsPlusSP	---	7037	{ // CPU16RegsPlusSP	---
7038	0, // CPU16RegsPlusSP:sub_32	---	7038	0, // CPU16RegsPlusSP:sub_32	---
7039	0, // CPU16RegsPlusSP:sub_64	---	7039	0, // CPU16RegsPlusSP:sub_64	---
7040	0, // CPU16RegsPlusSP:sub_dsp16_19	---	7040	0, // CPU16RegsPlusSP:sub_dsp16_19	---
7041	0, // CPU16RegsPlusSP:sub_dsp20	---	7041	0, // CPU16RegsPlusSP:sub_dsp20	---
7042	0, // CPU16RegsPlusSP:sub_dsp21	---	7042	0, // CPU16RegsPlusSP:sub_dsp21	---
7043	0, // CPU16RegsPlusSP:sub_dsp22	---	7043	0, // CPU16RegsPlusSP:sub_dsp22	---
7044	0, // CPU16RegsPlusSP:sub_dsp23	---	7044	0, // CPU16RegsPlusSP:sub_dsp23	---
7045	0, // CPU16RegsPlusSP:sub_hi	---	7045	0, // CPU16RegsPlusSP:sub_hi	---
7046	0, // CPU16RegsPlusSP:sub_lo	---	7046	0, // CPU16RegsPlusSP:sub_lo	---
7047	0, // CPU16RegsPlusSP:sub_hi_then_sub_32	---	7047	0, // CPU16RegsPlusSP:sub_hi_then_sub_32	---
7048	0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	---	7048	0, // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	---
7049	},	---	7049	},	---
7050	{ // CPU16Regs	---	7050	{ // CPU16Regs	---
7051	0, // CPU16Regs:sub_32	---	7051	0, // CPU16Regs:sub_32	---
7052	0, // CPU16Regs:sub_64	---	7052	0, // CPU16Regs:sub_64	---
7053	0, // CPU16Regs:sub_dsp16_19	---	7053	0, // CPU16Regs:sub_dsp16_19	---
7054	0, // CPU16Regs:sub_dsp20	---	7054	0, // CPU16Regs:sub_dsp20	---
7055	0, // CPU16Regs:sub_dsp21	---	7055	0, // CPU16Regs:sub_dsp21	---
7056	0, // CPU16Regs:sub_dsp22	---	7056	0, // CPU16Regs:sub_dsp22	---
7057	0, // CPU16Regs:sub_dsp23	---	7057	0, // CPU16Regs:sub_dsp23	---
7058	0, // CPU16Regs:sub_hi	---	7058	0, // CPU16Regs:sub_hi	---
7059	0, // CPU16Regs:sub_lo	---	7059	0, // CPU16Regs:sub_lo	---
7060	0, // CPU16Regs:sub_hi_then_sub_32	---	7060	0, // CPU16Regs:sub_hi_then_sub_32	---
7061	0, // CPU16Regs:sub_32_sub_hi_then_sub_32	---	7061	0, // CPU16Regs:sub_32_sub_hi_then_sub_32	---
7062	},	---	7062	},	---
7063	{ // FCC	---	7063	{ // FCC	---
7064	0, // FCC:sub_32	---	7064	0, // FCC:sub_32	---
7065	0, // FCC:sub_64	---	7065	0, // FCC:sub_64	---
7066	0, // FCC:sub_dsp16_19	---	7066	0, // FCC:sub_dsp16_19	---
7067	0, // FCC:sub_dsp20	---	7067	0, // FCC:sub_dsp20	---
7068	0, // FCC:sub_dsp21	---	7068	0, // FCC:sub_dsp21	---
7069	0, // FCC:sub_dsp22	---	7069	0, // FCC:sub_dsp22	---
7070	0, // FCC:sub_dsp23	---	7070	0, // FCC:sub_dsp23	---
7071	0, // FCC:sub_hi	---	7071	0, // FCC:sub_hi	---
7072	0, // FCC:sub_lo	---	7072	0, // FCC:sub_lo	---
7073	0, // FCC:sub_hi_then_sub_32	---	7073	0, // FCC:sub_hi_then_sub_32	---
7074	0, // FCC:sub_32_sub_hi_then_sub_32	---	7074	0, // FCC:sub_32_sub_hi_then_sub_32	---
7075	},	---	7075	},	---
7076	{ // GPRMM16	---	7076	{ // GPRMM16	---
7077	0, // GPRMM16:sub_32	---	7077	0, // GPRMM16:sub_32	---
7078	0, // GPRMM16:sub_64	---	7078	0, // GPRMM16:sub_64	---
7079	0, // GPRMM16:sub_dsp16_19	---	7079	0, // GPRMM16:sub_dsp16_19	---
7080	0, // GPRMM16:sub_dsp20	---	7080	0, // GPRMM16:sub_dsp20	---
7081	0, // GPRMM16:sub_dsp21	---	7081	0, // GPRMM16:sub_dsp21	---
7082	0, // GPRMM16:sub_dsp22	---	7082	0, // GPRMM16:sub_dsp22	---
7083	0, // GPRMM16:sub_dsp23	---	7083	0, // GPRMM16:sub_dsp23	---
7084	0, // GPRMM16:sub_hi	---	7084	0, // GPRMM16:sub_hi	---
7085	0, // GPRMM16:sub_lo	---	7085	0, // GPRMM16:sub_lo	---
7086	0, // GPRMM16:sub_hi_then_sub_32	---	7086	0, // GPRMM16:sub_hi_then_sub_32	---
7087	0, // GPRMM16:sub_32_sub_hi_then_sub_32	---	7087	0, // GPRMM16:sub_32_sub_hi_then_sub_32	---
7088	},	---	7088	},	---
7089	{ // GPRMM16MoveP	---	7089	{ // GPRMM16MoveP	---
7090	0, // GPRMM16MoveP:sub_32	---	7090	0, // GPRMM16MoveP:sub_32	---
7091	0, // GPRMM16MoveP:sub_64	---	7091	0, // GPRMM16MoveP:sub_64	---
7092	0, // GPRMM16MoveP:sub_dsp16_19	---	7092	0, // GPRMM16MoveP:sub_dsp16_19	---
7093	0, // GPRMM16MoveP:sub_dsp20	---	7093	0, // GPRMM16MoveP:sub_dsp20	---
7094	0, // GPRMM16MoveP:sub_dsp21	---	7094	0, // GPRMM16MoveP:sub_dsp21	---
7095	0, // GPRMM16MoveP:sub_dsp22	---	7095	0, // GPRMM16MoveP:sub_dsp22	---
7096	0, // GPRMM16MoveP:sub_dsp23	---	7096	0, // GPRMM16MoveP:sub_dsp23	---
7097	0, // GPRMM16MoveP:sub_hi	---	7097	0, // GPRMM16MoveP:sub_hi	---
7098	0, // GPRMM16MoveP:sub_lo	---	7098	0, // GPRMM16MoveP:sub_lo	---
7099	0, // GPRMM16MoveP:sub_hi_then_sub_32	---	7099	0, // GPRMM16MoveP:sub_hi_then_sub_32	---
7100	0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7100	0, // GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7101	},	---	7101	},	---
7102	{ // GPRMM16Zero	---	7102	{ // GPRMM16Zero	---
7103	0, // GPRMM16Zero:sub_32	---	7103	0, // GPRMM16Zero:sub_32	---
7104	0, // GPRMM16Zero:sub_64	---	7104	0, // GPRMM16Zero:sub_64	---
7105	0, // GPRMM16Zero:sub_dsp16_19	---	7105	0, // GPRMM16Zero:sub_dsp16_19	---
7106	0, // GPRMM16Zero:sub_dsp20	---	7106	0, // GPRMM16Zero:sub_dsp20	---
7107	0, // GPRMM16Zero:sub_dsp21	---	7107	0, // GPRMM16Zero:sub_dsp21	---
7108	0, // GPRMM16Zero:sub_dsp22	---	7108	0, // GPRMM16Zero:sub_dsp22	---
7109	0, // GPRMM16Zero:sub_dsp23	---	7109	0, // GPRMM16Zero:sub_dsp23	---
7110	0, // GPRMM16Zero:sub_hi	---	7110	0, // GPRMM16Zero:sub_hi	---
7111	0, // GPRMM16Zero:sub_lo	---	7111	0, // GPRMM16Zero:sub_lo	---
7112	0, // GPRMM16Zero:sub_hi_then_sub_32	---	7112	0, // GPRMM16Zero:sub_hi_then_sub_32	---
7113	0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7113	0, // GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7114	},	---	7114	},	---
7115	{ // CPU16Regs_and_GPRMM16Zero	---	7115	{ // CPU16Regs_and_GPRMM16Zero	---
7116	0, // CPU16Regs_and_GPRMM16Zero:sub_32	---	7116	0, // CPU16Regs_and_GPRMM16Zero:sub_32	---
7117	0, // CPU16Regs_and_GPRMM16Zero:sub_64	---	7117	0, // CPU16Regs_and_GPRMM16Zero:sub_64	---
7118	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---	7118	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---
7119	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20	---	7119	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp20	---
7120	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21	---	7120	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp21	---
7121	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22	---	7121	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp22	---
7122	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23	---	7122	0, // CPU16Regs_and_GPRMM16Zero:sub_dsp23	---
7123	0, // CPU16Regs_and_GPRMM16Zero:sub_hi	---	7123	0, // CPU16Regs_and_GPRMM16Zero:sub_hi	---
7124	0, // CPU16Regs_and_GPRMM16Zero:sub_lo	---	7124	0, // CPU16Regs_and_GPRMM16Zero:sub_lo	---
7125	0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---	7125	0, // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---
7126	0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7126	0, // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7127	},	---	7127	},	---
7128	{ // GPR32NONZERO_and_GPRMM16MoveP	---	7128	{ // GPR32NONZERO_and_GPRMM16MoveP	---
7129	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32	---	7129	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32	---
7130	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64	---	7130	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_64	---
7131	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	---	7131	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	---
7132	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	---	7132	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	---
7133	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	---	7133	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	---
7134	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	---	7134	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	---
7135	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	---	7135	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	---
7136	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi	---	7136	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi	---
7137	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo	---	7137	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_lo	---
7138	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	---	7138	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	---
7139	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7139	0, // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7140	},	---	7140	},	---
7141	{ // GPRMM16MovePPairSecond	---	7141	{ // GPRMM16MovePPairSecond	---
7142	0, // GPRMM16MovePPairSecond:sub_32	---	7142	0, // GPRMM16MovePPairSecond:sub_32	---
7143	0, // GPRMM16MovePPairSecond:sub_64	---	7143	0, // GPRMM16MovePPairSecond:sub_64	---
7144	0, // GPRMM16MovePPairSecond:sub_dsp16_19	---	7144	0, // GPRMM16MovePPairSecond:sub_dsp16_19	---
7145	0, // GPRMM16MovePPairSecond:sub_dsp20	---	7145	0, // GPRMM16MovePPairSecond:sub_dsp20	---
7146	0, // GPRMM16MovePPairSecond:sub_dsp21	---	7146	0, // GPRMM16MovePPairSecond:sub_dsp21	---
7147	0, // GPRMM16MovePPairSecond:sub_dsp22	---	7147	0, // GPRMM16MovePPairSecond:sub_dsp22	---
7148	0, // GPRMM16MovePPairSecond:sub_dsp23	---	7148	0, // GPRMM16MovePPairSecond:sub_dsp23	---
7149	0, // GPRMM16MovePPairSecond:sub_hi	---	7149	0, // GPRMM16MovePPairSecond:sub_hi	---
7150	0, // GPRMM16MovePPairSecond:sub_lo	---	7150	0, // GPRMM16MovePPairSecond:sub_lo	---
7151	0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7151	0, // GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7152	0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7152	0, // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7153	},	---	7153	},	---
7154	{ // CPU16Regs_and_GPRMM16MoveP	---	7154	{ // CPU16Regs_and_GPRMM16MoveP	---
7155	0, // CPU16Regs_and_GPRMM16MoveP:sub_32	---	7155	0, // CPU16Regs_and_GPRMM16MoveP:sub_32	---
7156	0, // CPU16Regs_and_GPRMM16MoveP:sub_64	---	7156	0, // CPU16Regs_and_GPRMM16MoveP:sub_64	---
7157	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	---	7157	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	---
7158	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20	---	7158	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp20	---
7159	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21	---	7159	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp21	---
7160	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22	---	7160	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp22	---
7161	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23	---	7161	0, // CPU16Regs_and_GPRMM16MoveP:sub_dsp23	---
7162	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi	---	7162	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi	---
7163	0, // CPU16Regs_and_GPRMM16MoveP:sub_lo	---	7163	0, // CPU16Regs_and_GPRMM16MoveP:sub_lo	---
7164	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	---	7164	0, // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	---
7165	0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7165	0, // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7166	},	---	7166	},	---
7167	{ // GPRMM16MoveP_and_GPRMM16Zero	---	7167	{ // GPRMM16MoveP_and_GPRMM16Zero	---
7168	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32	---	7168	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32	---
7169	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64	---	7169	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_64	---
7170	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	---	7170	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	---
7171	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	---	7171	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	---
7172	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	---	7172	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	---
7173	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	---	7173	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	---
7174	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	---	7174	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	---
7175	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi	---	7175	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi	---
7176	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo	---	7176	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_lo	---
7177	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	---	7177	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	---
7178	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7178	0, // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7179	},	---	7179	},	---
7180	{ // HI32DSP	---	7180	{ // HI32DSP	---
7181	0, // HI32DSP:sub_32	---	7181	0, // HI32DSP:sub_32	---
7182	0, // HI32DSP:sub_64	---	7182	0, // HI32DSP:sub_64	---
7183	0, // HI32DSP:sub_dsp16_19	---	7183	0, // HI32DSP:sub_dsp16_19	---
7184	0, // HI32DSP:sub_dsp20	---	7184	0, // HI32DSP:sub_dsp20	---
7185	0, // HI32DSP:sub_dsp21	---	7185	0, // HI32DSP:sub_dsp21	---
7186	0, // HI32DSP:sub_dsp22	---	7186	0, // HI32DSP:sub_dsp22	---
7187	0, // HI32DSP:sub_dsp23	---	7187	0, // HI32DSP:sub_dsp23	---
7188	0, // HI32DSP:sub_hi	---	7188	0, // HI32DSP:sub_hi	---
7189	0, // HI32DSP:sub_lo	---	7189	0, // HI32DSP:sub_lo	---
7190	0, // HI32DSP:sub_hi_then_sub_32	---	7190	0, // HI32DSP:sub_hi_then_sub_32	---
7191	0, // HI32DSP:sub_32_sub_hi_then_sub_32	---	7191	0, // HI32DSP:sub_32_sub_hi_then_sub_32	---
7192	},	---	7192	},	---
7193	{ // LO32DSP	---	7193	{ // LO32DSP	---
7194	0, // LO32DSP:sub_32	---	7194	0, // LO32DSP:sub_32	---
7195	0, // LO32DSP:sub_64	---	7195	0, // LO32DSP:sub_64	---
7196	0, // LO32DSP:sub_dsp16_19	---	7196	0, // LO32DSP:sub_dsp16_19	---
7197	0, // LO32DSP:sub_dsp20	---	7197	0, // LO32DSP:sub_dsp20	---
7198	0, // LO32DSP:sub_dsp21	---	7198	0, // LO32DSP:sub_dsp21	---
7199	0, // LO32DSP:sub_dsp22	---	7199	0, // LO32DSP:sub_dsp22	---
7200	0, // LO32DSP:sub_dsp23	---	7200	0, // LO32DSP:sub_dsp23	---
7201	0, // LO32DSP:sub_hi	---	7201	0, // LO32DSP:sub_hi	---
7202	0, // LO32DSP:sub_lo	---	7202	0, // LO32DSP:sub_lo	---
7203	0, // LO32DSP:sub_hi_then_sub_32	---	7203	0, // LO32DSP:sub_hi_then_sub_32	---
7204	0, // LO32DSP:sub_32_sub_hi_then_sub_32	---	7204	0, // LO32DSP:sub_32_sub_hi_then_sub_32	---
7205	},	---	7205	},	---
7206	{ // CPU16Regs_and_GPRMM16MovePPairSecond	---	7206	{ // CPU16Regs_and_GPRMM16MovePPairSecond	---
7207	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32	---	7207	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32	---
7208	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	---	7208	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	---
7209	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	---	7209	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	---
7210	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	---	7210	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	---
7211	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	---	7211	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	---
7212	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	---	7212	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	---
7213	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	---	7213	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	---
7214	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	---	7214	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	---
7215	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	---	7215	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	---
7216	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7216	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7217	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7217	0, // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7218	},	---	7218	},	---
7219	{ // GPRMM16MovePPairFirst	---	7219	{ // GPRMM16MovePPairFirst	---
7220	0, // GPRMM16MovePPairFirst:sub_32	---	7220	0, // GPRMM16MovePPairFirst:sub_32	---
7221	0, // GPRMM16MovePPairFirst:sub_64	---	7221	0, // GPRMM16MovePPairFirst:sub_64	---
7222	0, // GPRMM16MovePPairFirst:sub_dsp16_19	---	7222	0, // GPRMM16MovePPairFirst:sub_dsp16_19	---
7223	0, // GPRMM16MovePPairFirst:sub_dsp20	---	7223	0, // GPRMM16MovePPairFirst:sub_dsp20	---
7224	0, // GPRMM16MovePPairFirst:sub_dsp21	---	7224	0, // GPRMM16MovePPairFirst:sub_dsp21	---
7225	0, // GPRMM16MovePPairFirst:sub_dsp22	---	7225	0, // GPRMM16MovePPairFirst:sub_dsp22	---
7226	0, // GPRMM16MovePPairFirst:sub_dsp23	---	7226	0, // GPRMM16MovePPairFirst:sub_dsp23	---
7227	0, // GPRMM16MovePPairFirst:sub_hi	---	7227	0, // GPRMM16MovePPairFirst:sub_hi	---
7228	0, // GPRMM16MovePPairFirst:sub_lo	---	7228	0, // GPRMM16MovePPairFirst:sub_lo	---
7229	0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32	---	7229	0, // GPRMM16MovePPairFirst:sub_hi_then_sub_32	---
7230	0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	---	7230	0, // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	---
7231	},	---	7231	},	---
7232	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	7232	{ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
7233	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32	---	7233	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32	---
7234	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	---	7234	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	---
7235	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---	7235	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---
7236	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---	7236	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---
7237	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---	7237	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---
7238	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---	7238	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---
7239	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---	7239	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---
7240	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	---	7240	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	---
7241	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	---	7241	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	---
7242	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---	7242	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---
7243	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7243	0, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7244	},	---	7244	},	---
7245	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	7245	{ // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
7246	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32	---	7246	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32	---
7247	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	---	7247	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	---
7248	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	---	7248	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	---
7249	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	---	7249	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	---
7250	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	---	7250	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	---
7251	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	---	7251	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	---
7252	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	---	7252	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	---
7253	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	---	7253	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	---
7254	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	---	7254	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	---
7255	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7255	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7256	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7256	0, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7257	},	---	7257	},	---
7258	{ // CPURAReg	---	7258	{ // CPURAReg	---
7259	0, // CPURAReg:sub_32	---	7259	0, // CPURAReg:sub_32	---
7260	0, // CPURAReg:sub_64	---	7260	0, // CPURAReg:sub_64	---
7261	0, // CPURAReg:sub_dsp16_19	---	7261	0, // CPURAReg:sub_dsp16_19	---
7262	0, // CPURAReg:sub_dsp20	---	7262	0, // CPURAReg:sub_dsp20	---
7263	0, // CPURAReg:sub_dsp21	---	7263	0, // CPURAReg:sub_dsp21	---
7264	0, // CPURAReg:sub_dsp22	---	7264	0, // CPURAReg:sub_dsp22	---
7265	0, // CPURAReg:sub_dsp23	---	7265	0, // CPURAReg:sub_dsp23	---
7266	0, // CPURAReg:sub_hi	---	7266	0, // CPURAReg:sub_hi	---
7267	0, // CPURAReg:sub_lo	---	7267	0, // CPURAReg:sub_lo	---
7268	0, // CPURAReg:sub_hi_then_sub_32	---	7268	0, // CPURAReg:sub_hi_then_sub_32	---
7269	0, // CPURAReg:sub_32_sub_hi_then_sub_32	---	7269	0, // CPURAReg:sub_32_sub_hi_then_sub_32	---
7270	},	---	7270	},	---
7271	{ // CPUSPReg	---	7271	{ // CPUSPReg	---
7272	0, // CPUSPReg:sub_32	---	7272	0, // CPUSPReg:sub_32	---
7273	0, // CPUSPReg:sub_64	---	7273	0, // CPUSPReg:sub_64	---
7274	0, // CPUSPReg:sub_dsp16_19	---	7274	0, // CPUSPReg:sub_dsp16_19	---
7275	0, // CPUSPReg:sub_dsp20	---	7275	0, // CPUSPReg:sub_dsp20	---
7276	0, // CPUSPReg:sub_dsp21	---	7276	0, // CPUSPReg:sub_dsp21	---
7277	0, // CPUSPReg:sub_dsp22	---	7277	0, // CPUSPReg:sub_dsp22	---
7278	0, // CPUSPReg:sub_dsp23	---	7278	0, // CPUSPReg:sub_dsp23	---
7279	0, // CPUSPReg:sub_hi	---	7279	0, // CPUSPReg:sub_hi	---
7280	0, // CPUSPReg:sub_lo	---	7280	0, // CPUSPReg:sub_lo	---
7281	0, // CPUSPReg:sub_hi_then_sub_32	---	7281	0, // CPUSPReg:sub_hi_then_sub_32	---
7282	0, // CPUSPReg:sub_32_sub_hi_then_sub_32	---	7282	0, // CPUSPReg:sub_32_sub_hi_then_sub_32	---
7283	},	---	7283	},	---
7284	{ // DSPCC	---	7284	{ // DSPCC	---
7285	0, // DSPCC:sub_32	---	7285	0, // DSPCC:sub_32	---
7286	0, // DSPCC:sub_64	---	7286	0, // DSPCC:sub_64	---
7287	0, // DSPCC:sub_dsp16_19	---	7287	0, // DSPCC:sub_dsp16_19	---
7288	0, // DSPCC:sub_dsp20	---	7288	0, // DSPCC:sub_dsp20	---
7289	0, // DSPCC:sub_dsp21	---	7289	0, // DSPCC:sub_dsp21	---
7290	0, // DSPCC:sub_dsp22	---	7290	0, // DSPCC:sub_dsp22	---
7291	0, // DSPCC:sub_dsp23	---	7291	0, // DSPCC:sub_dsp23	---
7292	0, // DSPCC:sub_hi	---	7292	0, // DSPCC:sub_hi	---
7293	0, // DSPCC:sub_lo	---	7293	0, // DSPCC:sub_lo	---
7294	0, // DSPCC:sub_hi_then_sub_32	---	7294	0, // DSPCC:sub_hi_then_sub_32	---
7295	0, // DSPCC:sub_32_sub_hi_then_sub_32	---	7295	0, // DSPCC:sub_32_sub_hi_then_sub_32	---
7296	},	---	7296	},	---
7297	{ // GP32	---	7297	{ // GP32	---
7298	0, // GP32:sub_32	---	7298	0, // GP32:sub_32	---
7299	0, // GP32:sub_64	---	7299	0, // GP32:sub_64	---
7300	0, // GP32:sub_dsp16_19	---	7300	0, // GP32:sub_dsp16_19	---
7301	0, // GP32:sub_dsp20	---	7301	0, // GP32:sub_dsp20	---
7302	0, // GP32:sub_dsp21	---	7302	0, // GP32:sub_dsp21	---
7303	0, // GP32:sub_dsp22	---	7303	0, // GP32:sub_dsp22	---
7304	0, // GP32:sub_dsp23	---	7304	0, // GP32:sub_dsp23	---
7305	0, // GP32:sub_hi	---	7305	0, // GP32:sub_hi	---
7306	0, // GP32:sub_lo	---	7306	0, // GP32:sub_lo	---
7307	0, // GP32:sub_hi_then_sub_32	---	7307	0, // GP32:sub_hi_then_sub_32	---
7308	0, // GP32:sub_32_sub_hi_then_sub_32	---	7308	0, // GP32:sub_32_sub_hi_then_sub_32	---
7309	},	---	7309	},	---
7310	{ // GPR32ZERO	---	7310	{ // GPR32ZERO	---
7311	0, // GPR32ZERO:sub_32	---	7311	0, // GPR32ZERO:sub_32	---
7312	0, // GPR32ZERO:sub_64	---	7312	0, // GPR32ZERO:sub_64	---
7313	0, // GPR32ZERO:sub_dsp16_19	---	7313	0, // GPR32ZERO:sub_dsp16_19	---
7314	0, // GPR32ZERO:sub_dsp20	---	7314	0, // GPR32ZERO:sub_dsp20	---
7315	0, // GPR32ZERO:sub_dsp21	---	7315	0, // GPR32ZERO:sub_dsp21	---
7316	0, // GPR32ZERO:sub_dsp22	---	7316	0, // GPR32ZERO:sub_dsp22	---
7317	0, // GPR32ZERO:sub_dsp23	---	7317	0, // GPR32ZERO:sub_dsp23	---
7318	0, // GPR32ZERO:sub_hi	---	7318	0, // GPR32ZERO:sub_hi	---
7319	0, // GPR32ZERO:sub_lo	---	7319	0, // GPR32ZERO:sub_lo	---
7320	0, // GPR32ZERO:sub_hi_then_sub_32	---	7320	0, // GPR32ZERO:sub_hi_then_sub_32	---
7321	0, // GPR32ZERO:sub_32_sub_hi_then_sub_32	---	7321	0, // GPR32ZERO:sub_32_sub_hi_then_sub_32	---
7322	},	---	7322	},	---
7323	{ // HI32	---	7323	{ // HI32	---
7324	0, // HI32:sub_32	---	7324	0, // HI32:sub_32	---
7325	0, // HI32:sub_64	---	7325	0, // HI32:sub_64	---
7326	0, // HI32:sub_dsp16_19	---	7326	0, // HI32:sub_dsp16_19	---
7327	0, // HI32:sub_dsp20	---	7327	0, // HI32:sub_dsp20	---
7328	0, // HI32:sub_dsp21	---	7328	0, // HI32:sub_dsp21	---
7329	0, // HI32:sub_dsp22	---	7329	0, // HI32:sub_dsp22	---
7330	0, // HI32:sub_dsp23	---	7330	0, // HI32:sub_dsp23	---
7331	0, // HI32:sub_hi	---	7331	0, // HI32:sub_hi	---
7332	0, // HI32:sub_lo	---	7332	0, // HI32:sub_lo	---
7333	0, // HI32:sub_hi_then_sub_32	---	7333	0, // HI32:sub_hi_then_sub_32	---
7334	0, // HI32:sub_32_sub_hi_then_sub_32	---	7334	0, // HI32:sub_32_sub_hi_then_sub_32	---
7335	},	---	7335	},	---
7336	{ // LO32	---	7336	{ // LO32	---
7337	0, // LO32:sub_32	---	7337	0, // LO32:sub_32	---
7338	0, // LO32:sub_64	---	7338	0, // LO32:sub_64	---
7339	0, // LO32:sub_dsp16_19	---	7339	0, // LO32:sub_dsp16_19	---
7340	0, // LO32:sub_dsp20	---	7340	0, // LO32:sub_dsp20	---
7341	0, // LO32:sub_dsp21	---	7341	0, // LO32:sub_dsp21	---
7342	0, // LO32:sub_dsp22	---	7342	0, // LO32:sub_dsp22	---
7343	0, // LO32:sub_dsp23	---	7343	0, // LO32:sub_dsp23	---
7344	0, // LO32:sub_hi	---	7344	0, // LO32:sub_hi	---
7345	0, // LO32:sub_lo	---	7345	0, // LO32:sub_lo	---
7346	0, // LO32:sub_hi_then_sub_32	---	7346	0, // LO32:sub_hi_then_sub_32	---
7347	0, // LO32:sub_32_sub_hi_then_sub_32	---	7347	0, // LO32:sub_32_sub_hi_then_sub_32	---
7348	},	---	7348	},	---
7349	{ // SP32	---	7349	{ // SP32	---
7350	0, // SP32:sub_32	---	7350	0, // SP32:sub_32	---
7351	0, // SP32:sub_64	---	7351	0, // SP32:sub_64	---
7352	0, // SP32:sub_dsp16_19	---	7352	0, // SP32:sub_dsp16_19	---
7353	0, // SP32:sub_dsp20	---	7353	0, // SP32:sub_dsp20	---
7354	0, // SP32:sub_dsp21	---	7354	0, // SP32:sub_dsp21	---
7355	0, // SP32:sub_dsp22	---	7355	0, // SP32:sub_dsp22	---
7356	0, // SP32:sub_dsp23	---	7356	0, // SP32:sub_dsp23	---
7357	0, // SP32:sub_hi	---	7357	0, // SP32:sub_hi	---
7358	0, // SP32:sub_lo	---	7358	0, // SP32:sub_lo	---
7359	0, // SP32:sub_hi_then_sub_32	---	7359	0, // SP32:sub_hi_then_sub_32	---
7360	0, // SP32:sub_32_sub_hi_then_sub_32	---	7360	0, // SP32:sub_32_sub_hi_then_sub_32	---
7361	},	---	7361	},	---
7362	{ // FGR64	---	7362	{ // FGR64	---
7363	0, // FGR64:sub_32	---	7363	0, // FGR64:sub_32	---
7364	0, // FGR64:sub_64	---	7364	0, // FGR64:sub_64	---
7365	0, // FGR64:sub_dsp16_19	---	7365	0, // FGR64:sub_dsp16_19	---
7366	0, // FGR64:sub_dsp20	---	7366	0, // FGR64:sub_dsp20	---
7367	0, // FGR64:sub_dsp21	---	7367	0, // FGR64:sub_dsp21	---
7368	0, // FGR64:sub_dsp22	---	7368	0, // FGR64:sub_dsp22	---
7369	0, // FGR64:sub_dsp23	---	7369	0, // FGR64:sub_dsp23	---
7370	0, // FGR64:sub_hi	---	7370	0, // FGR64:sub_hi	---
7371	7, // FGR64:sub_lo -> FGR32	---	7371	7, // FGR64:sub_lo -> FGR32	---
7372	0, // FGR64:sub_hi_then_sub_32	---	7372	0, // FGR64:sub_hi_then_sub_32	---
7373	0, // FGR64:sub_32_sub_hi_then_sub_32	---	7373	0, // FGR64:sub_32_sub_hi_then_sub_32	---
7374	},	---	7374	},	---
7375	{ // GPR64	---	7375	{ // GPR64	---
7376	9, // GPR64:sub_32 -> GPR32	---	7376	9, // GPR64:sub_32 -> GPR32	---
7377	0, // GPR64:sub_64	---	7377	0, // GPR64:sub_64	---
7378	0, // GPR64:sub_dsp16_19	---	7378	0, // GPR64:sub_dsp16_19	---
7379	0, // GPR64:sub_dsp20	---	7379	0, // GPR64:sub_dsp20	---
7380	0, // GPR64:sub_dsp21	---	7380	0, // GPR64:sub_dsp21	---
7381	0, // GPR64:sub_dsp22	---	7381	0, // GPR64:sub_dsp22	---
7382	0, // GPR64:sub_dsp23	---	7382	0, // GPR64:sub_dsp23	---
7383	0, // GPR64:sub_hi	---	7383	0, // GPR64:sub_hi	---
7384	0, // GPR64:sub_lo	---	7384	0, // GPR64:sub_lo	---
7385	0, // GPR64:sub_hi_then_sub_32	---	7385	0, // GPR64:sub_hi_then_sub_32	---
7386	0, // GPR64:sub_32_sub_hi_then_sub_32	---	7386	0, // GPR64:sub_32_sub_hi_then_sub_32	---
7387	},	---	7387	},	---
7388	{ // GPR64_with_sub_32_in_GPR32NONZERO	---	7388	{ // GPR64_with_sub_32_in_GPR32NONZERO	---
7389	12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO	---	7389	12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO	---
7390	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64	---	7390	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_64	---
7391	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19	---	7391	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19	---
7392	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20	---	7392	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20	---
7393	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21	---	7393	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21	---
7394	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22	---	7394	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22	---
7395	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23	---	7395	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23	---
7396	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi	---	7396	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi	---
7397	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo	---	7397	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo	---
7398	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32	---	7398	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32	---
7399	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32	---	7399	0, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32	---
7400	},	---	7400	},	---
7401	{ // AFGR64	---	7401	{ // AFGR64	---
7402	0, // AFGR64:sub_32	---	7402	0, // AFGR64:sub_32	---
7403	0, // AFGR64:sub_64	---	7403	0, // AFGR64:sub_64	---
7404	0, // AFGR64:sub_dsp16_19	---	7404	0, // AFGR64:sub_dsp16_19	---
7405	0, // AFGR64:sub_dsp20	---	7405	0, // AFGR64:sub_dsp20	---
7406	0, // AFGR64:sub_dsp21	---	7406	0, // AFGR64:sub_dsp21	---
7407	0, // AFGR64:sub_dsp22	---	7407	0, // AFGR64:sub_dsp22	---
7408	0, // AFGR64:sub_dsp23	---	7408	0, // AFGR64:sub_dsp23	---
7409	8, // AFGR64:sub_hi -> FGRCC	---	7409	8, // AFGR64:sub_hi -> FGRCC	---
7410	8, // AFGR64:sub_lo -> FGRCC	---	7410	8, // AFGR64:sub_lo -> FGRCC	---
7411	0, // AFGR64:sub_hi_then_sub_32	---	7411	0, // AFGR64:sub_hi_then_sub_32	---
7412	0, // AFGR64:sub_32_sub_hi_then_sub_32	---	7412	0, // AFGR64:sub_32_sub_hi_then_sub_32	---
7413	},	---	7413	},	---
7414	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	---	7414	{ // GPR64_with_sub_32_in_CPU16RegsPlusSP	---
7415	13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP	---	7415	13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP	---
7416	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64	---	7416	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64	---
7417	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19	---	7417	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19	---
7418	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20	---	7418	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20	---
7419	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21	---	7419	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21	---
7420	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22	---	7420	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22	---
7421	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23	---	7421	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23	---
7422	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi	---	7422	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi	---
7423	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo	---	7423	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo	---
7424	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32	---	7424	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32	---
7425	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	---	7425	0, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32	---
7426	},	---	7426	},	---
7427	{ // GPR64_with_sub_32_in_CPU16Regs	---	7427	{ // GPR64_with_sub_32_in_CPU16Regs	---
7428	14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs	---	7428	14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs	---
7429	0, // GPR64_with_sub_32_in_CPU16Regs:sub_64	---	7429	0, // GPR64_with_sub_32_in_CPU16Regs:sub_64	---
7430	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19	---	7430	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19	---
7431	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20	---	7431	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20	---
7432	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21	---	7432	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21	---
7433	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22	---	7433	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22	---
7434	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23	---	7434	0, // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23	---
7435	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi	---	7435	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi	---
7436	0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo	---	7436	0, // GPR64_with_sub_32_in_CPU16Regs:sub_lo	---
7437	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32	---	7437	0, // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32	---
7438	0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32	---	7438	0, // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32	---
7439	},	---	7439	},	---
7440	{ // GPR64_with_sub_32_in_GPRMM16MoveP	---	7440	{ // GPR64_with_sub_32_in_GPRMM16MoveP	---
7441	17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP	---	7441	17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP	---
7442	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64	---	7442	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64	---
7443	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19	---	7443	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19	---
7444	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20	---	7444	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20	---
7445	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21	---	7445	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21	---
7446	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22	---	7446	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22	---
7447	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23	---	7447	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23	---
7448	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi	---	7448	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi	---
7449	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo	---	7449	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo	---
7450	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32	---	7450	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32	---
7451	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7451	0, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7452	},	---	7452	},	---
7453	{ // GPR64_with_sub_32_in_GPRMM16Zero	---	7453	{ // GPR64_with_sub_32_in_GPRMM16Zero	---
7454	18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero	---	7454	18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero	---
7455	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64	---	7455	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_64	---
7456	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19	---	7456	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19	---
7457	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20	---	7457	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20	---
7458	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21	---	7458	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21	---
7459	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22	---	7459	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22	---
7460	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23	---	7460	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23	---
7461	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi	---	7461	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi	---
7462	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo	---	7462	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo	---
7463	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32	---	7463	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32	---
7464	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7464	0, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7465	},	---	7465	},	---
7466	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---	7466	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---
7467	19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero	---	7467	19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero	---
7468	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64	---	7468	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64	---
7469	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---	7469	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---
7470	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---	7470	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---
7471	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---	7471	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---
7472	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---	7472	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---
7473	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---	7473	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---
7474	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi	---	7474	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi	---
7475	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo	---	7475	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo	---
7476	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---	7476	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---
7477	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7477	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7478	},	---	7478	},	---
7479	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---	7479	{ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---
7480	20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP	---	7480	20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP	---
7481	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64	---	7481	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64	---
7482	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	---	7482	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19	---
7483	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	---	7483	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20	---
7484	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	---	7484	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21	---
7485	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	---	7485	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22	---
7486	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	---	7486	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23	---
7487	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi	---	7487	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi	---
7488	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo	---	7488	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo	---
7489	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	---	7489	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32	---
7490	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7490	0, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7491	},	---	7491	},	---
7492	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---	7492	{ // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---
7493	21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond	---	7493	21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond	---
7494	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64	---	7494	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64	---
7495	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19	---	7495	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19	---
7496	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20	---	7496	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20	---
7497	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21	---	7497	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21	---
7498	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22	---	7498	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22	---
7499	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23	---	7499	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23	---
7500	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi	---	7500	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi	---
7501	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo	---	7501	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo	---
7502	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7502	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7503	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7503	0, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7504	},	---	7504	},	---
7505	{ // ACC64DSP	---	7505	{ // ACC64DSP	---
7506	0, // ACC64DSP:sub_32	---	7506	0, // ACC64DSP:sub_32	---
7507	0, // ACC64DSP:sub_64	---	7507	0, // ACC64DSP:sub_64	---
7508	0, // ACC64DSP:sub_dsp16_19	---	7508	0, // ACC64DSP:sub_dsp16_19	---
7509	0, // ACC64DSP:sub_dsp20	---	7509	0, // ACC64DSP:sub_dsp20	---
7510	0, // ACC64DSP:sub_dsp21	---	7510	0, // ACC64DSP:sub_dsp21	---
7511	0, // ACC64DSP:sub_dsp22	---	7511	0, // ACC64DSP:sub_dsp22	---
7512	0, // ACC64DSP:sub_dsp23	---	7512	0, // ACC64DSP:sub_dsp23	---
7513	24, // ACC64DSP:sub_hi -> HI32DSP	---	7513	24, // ACC64DSP:sub_hi -> HI32DSP	---
7514	25, // ACC64DSP:sub_lo -> LO32DSP	---	7514	25, // ACC64DSP:sub_lo -> LO32DSP	---
7515	0, // ACC64DSP:sub_hi_then_sub_32	---	7515	0, // ACC64DSP:sub_hi_then_sub_32	---
7516	0, // ACC64DSP:sub_32_sub_hi_then_sub_32	---	7516	0, // ACC64DSP:sub_32_sub_hi_then_sub_32	---
7517	},	---	7517	},	---
7518	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---	7518	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---
7519	22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP	---	7519	22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP	---
7520	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64	---	7520	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64	---
7521	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	---	7521	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19	---
7522	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20	---	7522	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20	---
7523	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21	---	7523	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21	---
7524	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22	---	7524	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22	---
7525	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23	---	7525	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23	---
7526	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi	---	7526	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi	---
7527	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo	---	7527	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo	---
7528	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	---	7528	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32	---
7529	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---	7529	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32	---
7530	},	---	7530	},	---
7531	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---	7531	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---
7532	23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero	---	7532	23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero	---
7533	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64	---	7533	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64	---
7534	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	---	7534	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19	---
7535	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	---	7535	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20	---
7536	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	---	7536	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21	---
7537	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	---	7537	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22	---
7538	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	---	7538	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23	---
7539	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi	---	7539	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi	---
7540	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo	---	7540	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo	---
7541	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	---	7541	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32	---
7542	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7542	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7543	},	---	7543	},	---
7544	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---	7544	{ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---
7545	26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond	---	7545	26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond	---
7546	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	---	7546	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64	---
7547	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	---	7547	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19	---
7548	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	---	7548	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20	---
7549	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	---	7549	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21	---
7550	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	---	7550	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22	---
7551	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	---	7551	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23	---
7552	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	---	7552	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi	---
7553	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	---	7553	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo	---
7554	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7554	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7555	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7555	0, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7556	},	---	7556	},	---
7557	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---	7557	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---
7558	27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst	---	7558	27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst	---
7559	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64	---	7559	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64	---
7560	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19	---	7560	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19	---
7561	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20	---	7561	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20	---
7562	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21	---	7562	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21	---
7563	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22	---	7563	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22	---
7564	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23	---	7564	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23	---
7565	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi	---	7565	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi	---
7566	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo	---	7566	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo	---
7567	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32	---	7567	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32	---
7568	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	---	7568	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32	---
7569	},	---	7569	},	---
7570	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	7570	{ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
7571	28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	7571	28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
7572	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	---	7572	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64	---
7573	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---	7573	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19	---
7574	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---	7574	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20	---
7575	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---	7575	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21	---
7576	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---	7576	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22	---
7577	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---	7577	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23	---
7578	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	---	7578	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi	---
7579	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	---	7579	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo	---
7580	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---	7580	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32	---
7581	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---	7581	0, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32	---
7582	},	---	7582	},	---
7583	{ // OCTEON_MPL	---	7583	{ // OCTEON_MPL	---
7584	0, // OCTEON_MPL:sub_32	---	7584	0, // OCTEON_MPL:sub_32	---
7585	0, // OCTEON_MPL:sub_64	---	7585	0, // OCTEON_MPL:sub_64	---
7586	0, // OCTEON_MPL:sub_dsp16_19	---	7586	0, // OCTEON_MPL:sub_dsp16_19	---
7587	0, // OCTEON_MPL:sub_dsp20	---	7587	0, // OCTEON_MPL:sub_dsp20	---
7588	0, // OCTEON_MPL:sub_dsp21	---	7588	0, // OCTEON_MPL:sub_dsp21	---
7589	0, // OCTEON_MPL:sub_dsp22	---	7589	0, // OCTEON_MPL:sub_dsp22	---
7590	0, // OCTEON_MPL:sub_dsp23	---	7590	0, // OCTEON_MPL:sub_dsp23	---
7591	0, // OCTEON_MPL:sub_hi	---	7591	0, // OCTEON_MPL:sub_hi	---
7592	0, // OCTEON_MPL:sub_lo	---	7592	0, // OCTEON_MPL:sub_lo	---
7593	0, // OCTEON_MPL:sub_hi_then_sub_32	---	7593	0, // OCTEON_MPL:sub_hi_then_sub_32	---
7594	0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32	---	7594	0, // OCTEON_MPL:sub_32_sub_hi_then_sub_32	---
7595	},	---	7595	},	---
7596	{ // OCTEON_P	---	7596	{ // OCTEON_P	---
7597	0, // OCTEON_P:sub_32	---	7597	0, // OCTEON_P:sub_32	---
7598	0, // OCTEON_P:sub_64	---	7598	0, // OCTEON_P:sub_64	---
7599	0, // OCTEON_P:sub_dsp16_19	---	7599	0, // OCTEON_P:sub_dsp16_19	---
7600	0, // OCTEON_P:sub_dsp20	---	7600	0, // OCTEON_P:sub_dsp20	---
7601	0, // OCTEON_P:sub_dsp21	---	7601	0, // OCTEON_P:sub_dsp21	---
7602	0, // OCTEON_P:sub_dsp22	---	7602	0, // OCTEON_P:sub_dsp22	---
7603	0, // OCTEON_P:sub_dsp23	---	7603	0, // OCTEON_P:sub_dsp23	---
7604	0, // OCTEON_P:sub_hi	---	7604	0, // OCTEON_P:sub_hi	---
7605	0, // OCTEON_P:sub_lo	---	7605	0, // OCTEON_P:sub_lo	---
7606	0, // OCTEON_P:sub_hi_then_sub_32	---	7606	0, // OCTEON_P:sub_hi_then_sub_32	---
7607	0, // OCTEON_P:sub_32_sub_hi_then_sub_32	---	7607	0, // OCTEON_P:sub_32_sub_hi_then_sub_32	---
7608	},	---	7608	},	---
7609	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	7609	{ // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
7610	29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	7610	29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
7611	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	---	7611	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64	---
7612	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	---	7612	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19	---
7613	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	---	7613	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20	---
7614	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	---	7614	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21	---
7615	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	---	7615	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22	---
7616	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	---	7616	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23	---
7617	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	---	7617	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi	---
7618	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	---	7618	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo	---
7619	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---	7619	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32	---
7620	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---	7620	0, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32	---
7621	},	---	7621	},	---
7622	{ // ACC64	---	7622	{ // ACC64	---
7623	0, // ACC64:sub_32	---	7623	0, // ACC64:sub_32	---
7624	0, // ACC64:sub_64	---	7624	0, // ACC64:sub_64	---
7625	0, // ACC64:sub_dsp16_19	---	7625	0, // ACC64:sub_dsp16_19	---
7626	0, // ACC64:sub_dsp20	---	7626	0, // ACC64:sub_dsp20	---
7627	0, // ACC64:sub_dsp21	---	7627	0, // ACC64:sub_dsp21	---
7628	0, // ACC64:sub_dsp22	---	7628	0, // ACC64:sub_dsp22	---
7629	0, // ACC64:sub_dsp23	---	7629	0, // ACC64:sub_dsp23	---
7630	35, // ACC64:sub_hi -> HI32	---	7630	35, // ACC64:sub_hi -> HI32	---
7631	36, // ACC64:sub_lo -> LO32	---	7631	36, // ACC64:sub_lo -> LO32	---
7632	0, // ACC64:sub_hi_then_sub_32	---	7632	0, // ACC64:sub_hi_then_sub_32	---
7633	0, // ACC64:sub_32_sub_hi_then_sub_32	---	7633	0, // ACC64:sub_32_sub_hi_then_sub_32	---
7634	},	---	7634	},	---
7635	{ // GP64	---	7635	{ // GP64	---
7636	33, // GP64:sub_32 -> GP32	---	7636	33, // GP64:sub_32 -> GP32	---
7637	0, // GP64:sub_64	---	7637	0, // GP64:sub_64	---
7638	0, // GP64:sub_dsp16_19	---	7638	0, // GP64:sub_dsp16_19	---
7639	0, // GP64:sub_dsp20	---	7639	0, // GP64:sub_dsp20	---
7640	0, // GP64:sub_dsp21	---	7640	0, // GP64:sub_dsp21	---
7641	0, // GP64:sub_dsp22	---	7641	0, // GP64:sub_dsp22	---
7642	0, // GP64:sub_dsp23	---	7642	0, // GP64:sub_dsp23	---
7643	0, // GP64:sub_hi	---	7643	0, // GP64:sub_hi	---
7644	0, // GP64:sub_lo	---	7644	0, // GP64:sub_lo	---
7645	0, // GP64:sub_hi_then_sub_32	---	7645	0, // GP64:sub_hi_then_sub_32	---
7646	0, // GP64:sub_32_sub_hi_then_sub_32	---	7646	0, // GP64:sub_32_sub_hi_then_sub_32	---
7647	},	---	7647	},	---
7648	{ // GPR64_with_sub_32_in_CPURAReg	---	7648	{ // GPR64_with_sub_32_in_CPURAReg	---
7649	30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg	---	7649	30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg	---
7650	0, // GPR64_with_sub_32_in_CPURAReg:sub_64	---	7650	0, // GPR64_with_sub_32_in_CPURAReg:sub_64	---
7651	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19	---	7651	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19	---
7652	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20	---	7652	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp20	---
7653	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21	---	7653	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp21	---
7654	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22	---	7654	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp22	---
7655	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23	---	7655	0, // GPR64_with_sub_32_in_CPURAReg:sub_dsp23	---
7656	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi	---	7656	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi	---
7657	0, // GPR64_with_sub_32_in_CPURAReg:sub_lo	---	7657	0, // GPR64_with_sub_32_in_CPURAReg:sub_lo	---
7658	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32	---	7658	0, // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32	---
7659	0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32	---	7659	0, // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32	---
7660	},	---	7660	},	---
7661	{ // GPR64_with_sub_32_in_GPR32ZERO	---	7661	{ // GPR64_with_sub_32_in_GPR32ZERO	---
7662	34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO	---	7662	34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO	---
7663	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64	---	7663	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_64	---
7664	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19	---	7664	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19	---
7665	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20	---	7665	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20	---
7666	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21	---	7666	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21	---
7667	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22	---	7667	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22	---
7668	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23	---	7668	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23	---
7669	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi	---	7669	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi	---
7670	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo	---	7670	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_lo	---
7671	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32	---	7671	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32	---
7672	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32	---	7672	0, // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32	---
7673	},	---	7673	},	---
7674	{ // HI64	---	7674	{ // HI64	---
7675	35, // HI64:sub_32 -> HI32	---	7675	35, // HI64:sub_32 -> HI32	---
7676	0, // HI64:sub_64	---	7676	0, // HI64:sub_64	---
7677	0, // HI64:sub_dsp16_19	---	7677	0, // HI64:sub_dsp16_19	---
7678	0, // HI64:sub_dsp20	---	7678	0, // HI64:sub_dsp20	---
7679	0, // HI64:sub_dsp21	---	7679	0, // HI64:sub_dsp21	---
7680	0, // HI64:sub_dsp22	---	7680	0, // HI64:sub_dsp22	---
7681	0, // HI64:sub_dsp23	---	7681	0, // HI64:sub_dsp23	---
7682	0, // HI64:sub_hi	---	7682	0, // HI64:sub_hi	---
7683	0, // HI64:sub_lo	---	7683	0, // HI64:sub_lo	---
7684	0, // HI64:sub_hi_then_sub_32	---	7684	0, // HI64:sub_hi_then_sub_32	---
7685	0, // HI64:sub_32_sub_hi_then_sub_32	---	7685	0, // HI64:sub_32_sub_hi_then_sub_32	---
7686	},	---	7686	},	---
7687	{ // LO64	---	7687	{ // LO64	---
7688	36, // LO64:sub_32 -> LO32	---	7688	36, // LO64:sub_32 -> LO32	---
7689	0, // LO64:sub_64	---	7689	0, // LO64:sub_64	---
7690	0, // LO64:sub_dsp16_19	---	7690	0, // LO64:sub_dsp16_19	---
7691	0, // LO64:sub_dsp20	---	7691	0, // LO64:sub_dsp20	---
7692	0, // LO64:sub_dsp21	---	7692	0, // LO64:sub_dsp21	---
7693	0, // LO64:sub_dsp22	---	7693	0, // LO64:sub_dsp22	---
7694	0, // LO64:sub_dsp23	---	7694	0, // LO64:sub_dsp23	---
7695	0, // LO64:sub_hi	---	7695	0, // LO64:sub_hi	---
7696	0, // LO64:sub_lo	---	7696	0, // LO64:sub_lo	---
7697	0, // LO64:sub_hi_then_sub_32	---	7697	0, // LO64:sub_hi_then_sub_32	---
7698	0, // LO64:sub_32_sub_hi_then_sub_32	---	7698	0, // LO64:sub_32_sub_hi_then_sub_32	---
7699	},	---	7699	},	---
7700	{ // SP64	---	7700	{ // SP64	---
7701	31, // SP64:sub_32 -> CPUSPReg	---	7701	31, // SP64:sub_32 -> CPUSPReg	---
7702	0, // SP64:sub_64	---	7702	0, // SP64:sub_64	---
7703	0, // SP64:sub_dsp16_19	---	7703	0, // SP64:sub_dsp16_19	---
7704	0, // SP64:sub_dsp20	---	7704	0, // SP64:sub_dsp20	---
7705	0, // SP64:sub_dsp21	---	7705	0, // SP64:sub_dsp21	---
7706	0, // SP64:sub_dsp22	---	7706	0, // SP64:sub_dsp22	---
7707	0, // SP64:sub_dsp23	---	7707	0, // SP64:sub_dsp23	---
7708	0, // SP64:sub_hi	---	7708	0, // SP64:sub_hi	---
7709	0, // SP64:sub_lo	---	7709	0, // SP64:sub_lo	---
7710	0, // SP64:sub_hi_then_sub_32	---	7710	0, // SP64:sub_hi_then_sub_32	---
7711	0, // SP64:sub_32_sub_hi_then_sub_32	---	7711	0, // SP64:sub_32_sub_hi_then_sub_32	---
7712	},	---	7712	},	---
7713	{ // MSA128B	---	7713	{ // MSA128B	---
7714	0, // MSA128B:sub_32	---	7714	0, // MSA128B:sub_32	---
7715	38, // MSA128B:sub_64 -> FGR64	---	7715	38, // MSA128B:sub_64 -> FGR64	---
7716	0, // MSA128B:sub_dsp16_19	---	7716	0, // MSA128B:sub_dsp16_19	---
7717	0, // MSA128B:sub_dsp20	---	7717	0, // MSA128B:sub_dsp20	---
7718	0, // MSA128B:sub_dsp21	---	7718	0, // MSA128B:sub_dsp21	---
7719	0, // MSA128B:sub_dsp22	---	7719	0, // MSA128B:sub_dsp22	---
7720	0, // MSA128B:sub_dsp23	---	7720	0, // MSA128B:sub_dsp23	---
7721	0, // MSA128B:sub_hi	---	7721	0, // MSA128B:sub_hi	---
7722	7, // MSA128B:sub_lo -> FGR32	---	7722	7, // MSA128B:sub_lo -> FGR32	---
7723	0, // MSA128B:sub_hi_then_sub_32	---	7723	0, // MSA128B:sub_hi_then_sub_32	---
7724	0, // MSA128B:sub_32_sub_hi_then_sub_32	---	7724	0, // MSA128B:sub_32_sub_hi_then_sub_32	---
7725	},	---	7725	},	---
7726	{ // MSA128D	---	7726	{ // MSA128D	---
7727	0, // MSA128D:sub_32	---	7727	0, // MSA128D:sub_32	---
7728	38, // MSA128D:sub_64 -> FGR64	---	7728	38, // MSA128D:sub_64 -> FGR64	---
7729	0, // MSA128D:sub_dsp16_19	---	7729	0, // MSA128D:sub_dsp16_19	---
7730	0, // MSA128D:sub_dsp20	---	7730	0, // MSA128D:sub_dsp20	---
7731	0, // MSA128D:sub_dsp21	---	7731	0, // MSA128D:sub_dsp21	---
7732	0, // MSA128D:sub_dsp22	---	7732	0, // MSA128D:sub_dsp22	---
7733	0, // MSA128D:sub_dsp23	---	7733	0, // MSA128D:sub_dsp23	---
7734	0, // MSA128D:sub_hi	---	7734	0, // MSA128D:sub_hi	---
7735	7, // MSA128D:sub_lo -> FGR32	---	7735	7, // MSA128D:sub_lo -> FGR32	---
7736	0, // MSA128D:sub_hi_then_sub_32	---	7736	0, // MSA128D:sub_hi_then_sub_32	---
7737	0, // MSA128D:sub_32_sub_hi_then_sub_32	---	7737	0, // MSA128D:sub_32_sub_hi_then_sub_32	---
7738	},	---	7738	},	---
7739	{ // MSA128H	---	7739	{ // MSA128H	---
7740	0, // MSA128H:sub_32	---	7740	0, // MSA128H:sub_32	---
7741	38, // MSA128H:sub_64 -> FGR64	---	7741	38, // MSA128H:sub_64 -> FGR64	---
7742	0, // MSA128H:sub_dsp16_19	---	7742	0, // MSA128H:sub_dsp16_19	---
7743	0, // MSA128H:sub_dsp20	---	7743	0, // MSA128H:sub_dsp20	---
7744	0, // MSA128H:sub_dsp21	---	7744	0, // MSA128H:sub_dsp21	---
7745	0, // MSA128H:sub_dsp22	---	7745	0, // MSA128H:sub_dsp22	---
7746	0, // MSA128H:sub_dsp23	---	7746	0, // MSA128H:sub_dsp23	---
7747	0, // MSA128H:sub_hi	---	7747	0, // MSA128H:sub_hi	---
7748	7, // MSA128H:sub_lo -> FGR32	---	7748	7, // MSA128H:sub_lo -> FGR32	---
7749	0, // MSA128H:sub_hi_then_sub_32	---	7749	0, // MSA128H:sub_hi_then_sub_32	---
7750	0, // MSA128H:sub_32_sub_hi_then_sub_32	---	7750	0, // MSA128H:sub_32_sub_hi_then_sub_32	---
7751	},	---	7751	},	---
7752	{ // MSA128W	---	7752	{ // MSA128W	---
7753	0, // MSA128W:sub_32	---	7753	0, // MSA128W:sub_32	---
7754	38, // MSA128W:sub_64 -> FGR64	---	7754	38, // MSA128W:sub_64 -> FGR64	---
7755	0, // MSA128W:sub_dsp16_19	---	7755	0, // MSA128W:sub_dsp16_19	---
7756	0, // MSA128W:sub_dsp20	---	7756	0, // MSA128W:sub_dsp20	---
7757	0, // MSA128W:sub_dsp21	---	7757	0, // MSA128W:sub_dsp21	---
7758	0, // MSA128W:sub_dsp22	---	7758	0, // MSA128W:sub_dsp22	---
7759	0, // MSA128W:sub_dsp23	---	7759	0, // MSA128W:sub_dsp23	---
7760	0, // MSA128W:sub_hi	---	7760	0, // MSA128W:sub_hi	---
7761	7, // MSA128W:sub_lo -> FGR32	---	7761	7, // MSA128W:sub_lo -> FGR32	---
7762	0, // MSA128W:sub_hi_then_sub_32	---	7762	0, // MSA128W:sub_hi_then_sub_32	---
7763	0, // MSA128W:sub_32_sub_hi_then_sub_32	---	7763	0, // MSA128W:sub_32_sub_hi_then_sub_32	---
7764	},	---	7764	},	---
7765	{ // MSA128WEvens	---	7765	{ // MSA128WEvens	---
7766	0, // MSA128WEvens:sub_32	---	7766	0, // MSA128WEvens:sub_32	---
7767	38, // MSA128WEvens:sub_64 -> FGR64	---	7767	38, // MSA128WEvens:sub_64 -> FGR64	---
7768	0, // MSA128WEvens:sub_dsp16_19	---	7768	0, // MSA128WEvens:sub_dsp16_19	---
7769	0, // MSA128WEvens:sub_dsp20	---	7769	0, // MSA128WEvens:sub_dsp20	---
7770	0, // MSA128WEvens:sub_dsp21	---	7770	0, // MSA128WEvens:sub_dsp21	---
7771	0, // MSA128WEvens:sub_dsp22	---	7771	0, // MSA128WEvens:sub_dsp22	---
7772	0, // MSA128WEvens:sub_dsp23	---	7772	0, // MSA128WEvens:sub_dsp23	---
7773	0, // MSA128WEvens:sub_hi	---	7773	0, // MSA128WEvens:sub_hi	---
7774	8, // MSA128WEvens:sub_lo -> FGRCC	---	7774	8, // MSA128WEvens:sub_lo -> FGRCC	---
7775	0, // MSA128WEvens:sub_hi_then_sub_32	---	7775	0, // MSA128WEvens:sub_hi_then_sub_32	---
7776	0, // MSA128WEvens:sub_32_sub_hi_then_sub_32	---	7776	0, // MSA128WEvens:sub_32_sub_hi_then_sub_32	---
7777	},	---	7777	},	---
7778	{ // ACC128	---	7778	{ // ACC128	---
7779	36, // ACC128:sub_32 -> LO32	---	7779	36, // ACC128:sub_32 -> LO32	---
7780	0, // ACC128:sub_64	---	7780	0, // ACC128:sub_64	---
7781	0, // ACC128:sub_dsp16_19	---	7781	0, // ACC128:sub_dsp16_19	---
7782	0, // ACC128:sub_dsp20	---	7782	0, // ACC128:sub_dsp20	---
7783	0, // ACC128:sub_dsp21	---	7783	0, // ACC128:sub_dsp21	---
7784	0, // ACC128:sub_dsp22	---	7784	0, // ACC128:sub_dsp22	---
7785	0, // ACC128:sub_dsp23	---	7785	0, // ACC128:sub_dsp23	---
7786	62, // ACC128:sub_hi -> HI64	---	7786	62, // ACC128:sub_hi -> HI64	---
7787	63, // ACC128:sub_lo -> LO64	---	7787	63, // ACC128:sub_lo -> LO64	---
7788	35, // ACC128:sub_hi_then_sub_32 -> HI32	---	7788	35, // ACC128:sub_hi_then_sub_32 -> HI32	---
7789	58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64	---	7789	58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64	---
7790	},	---	7790	},	---
7791	};	---	7791	};	---
7792	assert(RC && "Missing regclass");	0	7792	assert(RC && "Missing regclass");	0
7793	if (!Idx) return RC;	0	7793	if (!Idx) return RC;	0
7794	--Idx;	0	7794	--Idx;	0
7795	assert(Idx < 11 && "Bad subreg");	0	7795	assert(Idx < 11 && "Bad subreg");	0
7796	unsigned TV = Table[RC->getID()][Idx];	0	7796	unsigned TV = Table[RC->getID()][Idx];	0
7797	return TV ? getRegClass(TV - 1) : nullptr;	0	7797	return TV ? getRegClass(TV - 1) : nullptr;	0
7798	}	---	7798	}	---
7799		---	7799		---
7800	/// Get the weight in units of pressure for this register class.	---	7800	/// Get the weight in units of pressure for this register class.	---
7801	const RegClassWeight &MipsGenRegisterInfo::	0	7801	const RegClassWeight &MipsGenRegisterInfo::	0
7802	getRegClassWeight(const TargetRegisterClass *RC) const {	---	7802	getRegClassWeight(const TargetRegisterClass *RC) const {	---
7803	static const RegClassWeight RCWeightTable[] = {	---	7803	static const RegClassWeight RCWeightTable[] = {	---
7804	{2, 64}, // MSA128F16	---	7804	{2, 64}, // MSA128F16	---
7805	{0, 0}, // CCR	---	7805	{0, 0}, // CCR	---
7806	{0, 0}, // COP0	---	7806	{0, 0}, // COP0	---
7807	{0, 0}, // COP2	---	7807	{0, 0}, // COP2	---
7808	{0, 0}, // COP3	---	7808	{0, 0}, // COP3	---
7809	{1, 32}, // DSPR	---	7809	{1, 32}, // DSPR	---
7810	{1, 32}, // FGR32	---	7810	{1, 32}, // FGR32	---
7811	{1, 32}, // FGRCC	---	7811	{1, 32}, // FGRCC	---
7812	{1, 32}, // GPR32	---	7812	{1, 32}, // GPR32	---
7813	{0, 0}, // HWRegs	---	7813	{0, 0}, // HWRegs	---
7814	{0, 0}, // MSACtrl	---	7814	{0, 0}, // MSACtrl	---
7815	{1, 31}, // GPR32NONZERO	---	7815	{1, 31}, // GPR32NONZERO	---
7816	{1, 9}, // CPU16RegsPlusSP	---	7816	{1, 9}, // CPU16RegsPlusSP	---
7817	{1, 8}, // CPU16Regs	---	7817	{1, 8}, // CPU16Regs	---
7818	{0, 0}, // FCC	---	7818	{0, 0}, // FCC	---
7819	{1, 8}, // GPRMM16	---	7819	{1, 8}, // GPRMM16	---
7820	{1, 8}, // GPRMM16MoveP	---	7820	{1, 8}, // GPRMM16MoveP	---
7821	{1, 8}, // GPRMM16Zero	---	7821	{1, 8}, // GPRMM16Zero	---
7822	{1, 7}, // CPU16Regs_and_GPRMM16Zero	---	7822	{1, 7}, // CPU16Regs_and_GPRMM16Zero	---
7823	{1, 7}, // GPR32NONZERO_and_GPRMM16MoveP	---	7823	{1, 7}, // GPR32NONZERO_and_GPRMM16MoveP	---
7824	{1, 5}, // GPRMM16MovePPairSecond	---	7824	{1, 5}, // GPRMM16MovePPairSecond	---
7825	{1, 4}, // CPU16Regs_and_GPRMM16MoveP	---	7825	{1, 4}, // CPU16Regs_and_GPRMM16MoveP	---
7826	{1, 4}, // GPRMM16MoveP_and_GPRMM16Zero	---	7826	{1, 4}, // GPRMM16MoveP_and_GPRMM16Zero	---
7827	{1, 4}, // HI32DSP	---	7827	{1, 4}, // HI32DSP	---
7828	{1, 4}, // LO32DSP	---	7828	{1, 4}, // LO32DSP	---
7829	{1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond	---	7829	{1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond	---
7830	{1, 3}, // GPRMM16MovePPairFirst	---	7830	{1, 3}, // GPRMM16MovePPairFirst	---
7831	{1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	7831	{1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
7832	{1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	7832	{1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
7833	{1, 1}, // CPURAReg	---	7833	{1, 1}, // CPURAReg	---
7834	{1, 1}, // CPUSPReg	---	7834	{1, 1}, // CPUSPReg	---
7835	{1, 1}, // DSPCC	---	7835	{1, 1}, // DSPCC	---
7836	{1, 1}, // GP32	---	7836	{1, 1}, // GP32	---
7837	{1, 1}, // GPR32ZERO	---	7837	{1, 1}, // GPR32ZERO	---
7838	{1, 1}, // HI32	---	7838	{1, 1}, // HI32	---
7839	{1, 1}, // LO32	---	7839	{1, 1}, // LO32	---
7840	{1, 1}, // SP32	---	7840	{1, 1}, // SP32	---
7841	{2, 64}, // FGR64	---	7841	{2, 64}, // FGR64	---
7842	{1, 32}, // GPR64	---	7842	{1, 32}, // GPR64	---
7843	{1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO	---	7843	{1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO	---
7844	{2, 32}, // AFGR64	---	7844	{2, 32}, // AFGR64	---
7845	{1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP	---	7845	{1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP	---
7846	{1, 8}, // GPR64_with_sub_32_in_CPU16Regs	---	7846	{1, 8}, // GPR64_with_sub_32_in_CPU16Regs	---
7847	{1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP	---	7847	{1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP	---
7848	{1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero	---	7848	{1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero	---
7849	{1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---	7849	{1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero	---
7850	{1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---	7850	{1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP	---
7851	{1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---	7851	{1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond	---
7852	{2, 8}, // ACC64DSP	---	7852	{2, 8}, // ACC64DSP	---
7853	{1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---	7853	{1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP	---
7854	{1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---	7854	{1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero	---
7855	{1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---	7855	{1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond	---
7856	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---	7856	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst	---
7857	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---	7857	{1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero	---
7858	{0, 0}, // OCTEON_MPL	---	7858	{0, 0}, // OCTEON_MPL	---
7859	{0, 0}, // OCTEON_P	---	7859	{0, 0}, // OCTEON_P	---
7860	{1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---	7860	{1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond	---
7861	{2, 2}, // ACC64	---	7861	{2, 2}, // ACC64	---
7862	{1, 1}, // GP64	---	7862	{1, 1}, // GP64	---
7863	{1, 1}, // GPR64_with_sub_32_in_CPURAReg	---	7863	{1, 1}, // GPR64_with_sub_32_in_CPURAReg	---
7864	{1, 1}, // GPR64_with_sub_32_in_GPR32ZERO	---	7864	{1, 1}, // GPR64_with_sub_32_in_GPR32ZERO	---
7865	{1, 1}, // HI64	---	7865	{1, 1}, // HI64	---
7866	{1, 1}, // LO64	---	7866	{1, 1}, // LO64	---
7867	{1, 1}, // SP64	---	7867	{1, 1}, // SP64	---
7868	{2, 64}, // MSA128B	---	7868	{2, 64}, // MSA128B	---
7869	{2, 64}, // MSA128D	---	7869	{2, 64}, // MSA128D	---
7870	{2, 64}, // MSA128H	---	7870	{2, 64}, // MSA128H	---
7871	{2, 64}, // MSA128W	---	7871	{2, 64}, // MSA128W	---
7872	{2, 32}, // MSA128WEvens	---	7872	{2, 32}, // MSA128WEvens	---
7873	{2, 2}, // ACC128	---	7873	{2, 2}, // ACC128	---
7874	};	---	7874	};	---
7875	return RCWeightTable[RC->getID()];	0	7875	return RCWeightTable[RC->getID()];	0
7876	}	---	7876	}	---
7877		---	7877		---
7878	/// Get the weight in units of pressure for this register unit.	---	7878	/// Get the weight in units of pressure for this register unit.	---
7879	unsigned MipsGenRegisterInfo::	0	7879	unsigned MipsGenRegisterInfo::	0
7880	getRegUnitWeight(unsigned RegUnit) const {	---	7880	getRegUnitWeight(unsigned RegUnit) const {	---
7881	assert(RegUnit < 321 && "invalid register unit");	0	7881	assert(RegUnit < 321 && "invalid register unit");	0
7882	// All register units have unit weight.	---	7882	// All register units have unit weight.	---
7883	return 1;	0	7883	return 1;	0
7884	}	---	7884	}	---
7885		---	7885		---
7886		---	7886		---
7887	// Get the number of dimensions of register pressure.	---	7887	// Get the number of dimensions of register pressure.	---
7888	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {	2	7888	unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {	2
7889	return 20;	2	7889	return 20;	2
7890	}	---	7890	}	---
7891		---	7891		---
7892	// Get the name of this register unit pressure set.	---	7892	// Get the name of this register unit pressure set.	---
7893	const char *MipsGenRegisterInfo::	0	7893	const char *MipsGenRegisterInfo::	0
7894	getRegPressureSetName(unsigned Idx) const {	---	7894	getRegPressureSetName(unsigned Idx) const {	---
7895	static const char *PressureNameTable[] = {	---	7895	static const char *PressureNameTable[] = {	---
7896	"DSPCC",	---	7896	"DSPCC",	---
7897	"GPR32ZERO",	---	7897	"GPR32ZERO",	---
7898	"GPR64_with_sub_32_in_CPURAReg",	---	7898	"GPR64_with_sub_32_in_CPURAReg",	---
7899	"HI32",	---	7899	"HI32",	---
7900	"GPRMM16MovePPairFirst",	---	7900	"GPRMM16MovePPairFirst",	---
7901	"CPU16Regs_and_GPRMM16MoveP",	---	7901	"CPU16Regs_and_GPRMM16MoveP",	---
7902	"HI32DSP",	---	7902	"HI32DSP",	---
7903	"LO32DSP",	---	7903	"LO32DSP",	---
7904	"GPRMM16MovePPairSecond",	---	7904	"GPRMM16MovePPairSecond",	---
7905	"GPRMM16MoveP",	---	7905	"GPRMM16MoveP",	---
7906	"ACC64DSP",	---	7906	"ACC64DSP",	---
7907	"CPU16Regs",	---	7907	"CPU16Regs",	---
7908	"GPRMM16Zero_with_GPRMM16MovePPairSecond",	---	7908	"GPRMM16Zero_with_GPRMM16MovePPairSecond",	---
7909	"CPU16Regs_with_GPRMM16MovePPairSecond",	---	7909	"CPU16Regs_with_GPRMM16MovePPairSecond",	---
7910	"CPU16Regs_with_GPRMM16MoveP",	---	7910	"CPU16Regs_with_GPRMM16MoveP",	---
7911	"DSPR",	---	7911	"DSPR",	---
7912	"FGR32",	---	7912	"FGR32",	---
7913	"MSA128WEvens",	---	7913	"MSA128WEvens",	---
7914	"FGR32_with_MSA128WEvens",	---	7914	"FGR32_with_MSA128WEvens",	---
7915	"MSA128F16",	---	7915	"MSA128F16",	---
7916	};	---	7916	};	---
7917	return PressureNameTable[Idx];	0	7917	return PressureNameTable[Idx];	0
7918	}	---	7918	}	---
7919		---	7919		---
7920	// Get the register unit pressure limit for this dimension.	---	7920	// Get the register unit pressure limit for this dimension.	---
7921	// This limit must be adjusted dynamically for reserved registers.	---	7921	// This limit must be adjusted dynamically for reserved registers.	---
7922	unsigned MipsGenRegisterInfo::	0	7922	unsigned MipsGenRegisterInfo::	0
7923	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {	---	7923	getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {	---
7924	static const uint8_t PressureLimitTable[] = {	---	7924	static const uint8_t PressureLimitTable[] = {	---
7925	1, // 0: DSPCC	---	7925	1, // 0: DSPCC	---
7926	1, // 1: GPR32ZERO	---	7926	1, // 1: GPR32ZERO	---
7927	1, // 2: GPR64_with_sub_32_in_CPURAReg	---	7927	1, // 2: GPR64_with_sub_32_in_CPURAReg	---
7928	2, // 3: HI32	---	7928	2, // 3: HI32	---
7929	3, // 4: GPRMM16MovePPairFirst	---	7929	3, // 4: GPRMM16MovePPairFirst	---
7930	5, // 5: CPU16Regs_and_GPRMM16MoveP	---	7930	5, // 5: CPU16Regs_and_GPRMM16MoveP	---
7931	5, // 6: HI32DSP	---	7931	5, // 6: HI32DSP	---
7932	5, // 7: LO32DSP	---	7932	5, // 7: LO32DSP	---
7933	6, // 8: GPRMM16MovePPairSecond	---	7933	6, // 8: GPRMM16MovePPairSecond	---
7934	8, // 9: GPRMM16MoveP	---	7934	8, // 9: GPRMM16MoveP	---
7935	8, // 10: ACC64DSP	---	7935	8, // 10: ACC64DSP	---
7936	10, // 11: CPU16Regs	---	7936	10, // 11: CPU16Regs	---
7937	10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond	---	7937	10, // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond	---
7938	11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond	---	7938	11, // 13: CPU16Regs_with_GPRMM16MovePPairSecond	---
7939	13, // 14: CPU16Regs_with_GPRMM16MoveP	---	7939	13, // 14: CPU16Regs_with_GPRMM16MoveP	---
7940	32, // 15: DSPR	---	7940	32, // 15: DSPR	---
7941	32, // 16: FGR32	---	7941	32, // 16: FGR32	---
7942	32, // 17: MSA128WEvens	---	7942	32, // 17: MSA128WEvens	---
7943	48, // 18: FGR32_with_MSA128WEvens	---	7943	48, // 18: FGR32_with_MSA128WEvens	---
7944	64, // 19: MSA128F16	---	7944	64, // 19: MSA128F16	---
7945	};	---	7945	};	---
7946	return PressureLimitTable[Idx];	0	7946	return PressureLimitTable[Idx];	0
7947	}	---	7947	}	---
7948		---	7948		---
7949	/// Table of pressure sets per register class or unit.	---	7949	/// Table of pressure sets per register class or unit.	---
7950	static const int RCSetsTable[] = {	---	7950	static const int RCSetsTable[] = {	---
7951	/* 0 */ 0, -1,	---	7951	/* 0 */ 0, -1,	---
7952	/* 2 */ 6, 10, -1,	---	7952	/* 2 */ 6, 10, -1,	---
7953	/* 5 */ 3, 6, 7, 10, -1,	---	7953	/* 5 */ 3, 6, 7, 10, -1,	---
7954	/* 10 */ 2, 15, -1,	---	7954	/* 10 */ 2, 15, -1,	---
7955	/* 13 */ 8, 12, 13, 15, -1,	---	7955	/* 13 */ 8, 12, 13, 15, -1,	---
7956	/* 18 */ 9, 14, 15, -1,	---	7956	/* 18 */ 9, 14, 15, -1,	---
7957	/* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,	---	7957	/* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,	---
7958	/* 30 */ 5, 9, 11, 13, 14, 15, -1,	---	7958	/* 30 */ 5, 9, 11, 13, 14, 15, -1,	---
7959	/* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,	---	7959	/* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,	---
7960	/* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,	---	7960	/* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,	---
7961	/* 53 */ 16, 18, 19, -1,	---	7961	/* 53 */ 16, 18, 19, -1,	---
7962	/* 57 */ 16, 17, 18, 19, -1,	---	7962	/* 57 */ 16, 17, 18, 19, -1,	---
7963	};	---	7963	};	---
7964		---	7964		---
7965	/// Get the dimensions of register pressure impacted by this register class.	---	7965	/// Get the dimensions of register pressure impacted by this register class.	---
7966	/// Returns a -1 terminated array of pressure set IDs	---	7966	/// Returns a -1 terminated array of pressure set IDs	---
7967	const int *MipsGenRegisterInfo::	0	7967	const int *MipsGenRegisterInfo::	0
7968	getRegClassPressureSets(const TargetRegisterClass *RC) const {	---	7968	getRegClassPressureSets(const TargetRegisterClass *RC) const {	---
7969	static const uint8_t RCSetStartTable[] = {	---	7969	static const uint8_t RCSetStartTable[] = {	---
7970	55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};	---	7970	55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};	---
7971	return &RCSetsTable[RCSetStartTable[RC->getID()]];	0	7971	return &RCSetsTable[RCSetStartTable[RC->getID()]];	0
7972	}	---	7972	}	---
7973		---	7973		---
7974	/// Get the dimensions of register pressure impacted by this register unit.	---	7974	/// Get the dimensions of register pressure impacted by this register unit.	---
7975	/// Returns a -1 terminated array of pressure set IDs	---	7975	/// Returns a -1 terminated array of pressure set IDs	---
7976	const int *MipsGenRegisterInfo::	0	7976	const int *MipsGenRegisterInfo::	0
7977	getRegUnitPressureSets(unsigned RegUnit) const {	---	7977	getRegUnitPressureSets(unsigned RegUnit) const {	---
7978	assert(RegUnit < 321 && "invalid register unit");	0	7978	assert(RegUnit < 321 && "invalid register unit");	0
7979	static const uint8_t RUSetStartTable[] = {	---	7979	static const uint8_t RUSetStartTable[] = {	---
7980	11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};	---	7980	11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};	---
7981	return &RCSetsTable[RUSetStartTable[RegUnit]];	0	7981	return &RCSetsTable[RUSetStartTable[RegUnit]];	0
7982	}	---	7982	}	---
7983		---	7983		---
7984	extern const MCRegisterDesc MipsRegDesc[];	---	7984	extern const MCRegisterDesc MipsRegDesc[];	---
7985	extern const int16_t MipsRegDiffLists[];	---	7985	extern const int16_t MipsRegDiffLists[];	---
7986	extern const LaneBitmask MipsLaneMaskLists[];	---	7986	extern const LaneBitmask MipsLaneMaskLists[];	---
7987	extern const char MipsRegStrings[];	---	7987	extern const char MipsRegStrings[];	---
7988	extern const char MipsRegClassStrings[];	---	7988	extern const char MipsRegClassStrings[];	---
7989	extern const MCPhysReg MipsRegUnitRoots[][2];	---	7989	extern const MCPhysReg MipsRegUnitRoots[][2];	---
7990	extern const uint16_t MipsSubRegIdxLists[];	---	7990	extern const uint16_t MipsSubRegIdxLists[];	---
7991	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];	---	7991	extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];	---
7992	extern const uint16_t MipsRegEncodingTable[];	---	7992	extern const uint16_t MipsRegEncodingTable[];	---
7993	// Mips Dwarf<->LLVM register mappings.	---	7993	// Mips Dwarf<->LLVM register mappings.	---
7994	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];	---	7994	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];	---
7995	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;	---	7995	extern const unsigned MipsDwarfFlavour0Dwarf2LSize;	---
7996		---	7996		---
7997	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];	---	7997	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];	---
7998	extern const unsigned MipsEHFlavour0Dwarf2LSize;	---	7998	extern const unsigned MipsEHFlavour0Dwarf2LSize;	---
7999		---	7999		---
8000	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];	---	8000	extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];	---
8001	extern const unsigned MipsDwarfFlavour0L2DwarfSize;	---	8001	extern const unsigned MipsDwarfFlavour0L2DwarfSize;	---
8002		---	8002		---
8003	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];	---	8003	extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];	---
8004	extern const unsigned MipsEHFlavour0L2DwarfSize;	---	8004	extern const unsigned MipsEHFlavour0L2DwarfSize;	---
8005		---	8005		---
8006	MipsGenRegisterInfo::	5	8006	MipsGenRegisterInfo::	5
8007	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,	---	8007	MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,	---
8008	unsigned PC, unsigned HwMode)	---	8008	unsigned PC, unsigned HwMode)	---
8009	: TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,	---	8009	: TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,	---
8010	SubRegIndexNameTable, SubRegIndexLaneMaskTable,	---	8010	SubRegIndexNameTable, SubRegIndexLaneMaskTable,	---
8011	LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {	5	8011	LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, HwMode) {	5
8012	InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,	5	8012	InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,	5
8013	MipsMCRegisterClasses, 70,	---	8013	MipsMCRegisterClasses, 70,	---
8014	MipsRegUnitRoots,	---	8014	MipsRegUnitRoots,	---
8015	321,	---	8015	321,	---
8016	MipsRegDiffLists,	---	8016	MipsRegDiffLists,	---
8017	MipsLaneMaskLists,	---	8017	MipsLaneMaskLists,	---
8018	MipsRegStrings,	---	8018	MipsRegStrings,	---
8019	MipsRegClassStrings,	---	8019	MipsRegClassStrings,	---
8020	MipsSubRegIdxLists,	---	8020	MipsSubRegIdxLists,	---
8021	12,	---	8021	12,	---
8022	MipsSubRegIdxRanges,	---	8022	MipsSubRegIdxRanges,	---
8023	MipsRegEncodingTable);	---	8023	MipsRegEncodingTable);	---
8024		---	8024		---
8025	switch (DwarfFlavour) {	5	8025	switch (DwarfFlavour) {	5
8026	default:	0	8026	default:	0
8027	llvm_unreachable("Unknown DWARF flavour");	0	8027	llvm_unreachable("Unknown DWARF flavour");	0
8028	case 0:	5	8028	case 0:	5
8029	mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	5	8029	mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);	5
8030	break;	5	8030	break;	5
8031	}	---	8031	}	---
8032	switch (EHFlavour) {	5	8032	switch (EHFlavour) {	5
8033	default:	0	8033	default:	0
8034	llvm_unreachable("Unknown DWARF flavour");	0	8034	llvm_unreachable("Unknown DWARF flavour");	0
8035	case 0:	5	8035	case 0:	5
8036	mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	5	8036	mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);	5
8037	break;	5	8037	break;	5
8038	}	---	8038	}	---
8039	switch (DwarfFlavour) {	5	8039	switch (DwarfFlavour) {	5
8040	default:	0	8040	default:	0
8041	llvm_unreachable("Unknown DWARF flavour");	0	8041	llvm_unreachable("Unknown DWARF flavour");	0
8042	case 0:	5	8042	case 0:	5
8043	mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	5	8043	mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);	5
8044	break;	5	8044	break;	5
8045	}	---	8045	}	---
8046	switch (EHFlavour) {	5	8046	switch (EHFlavour) {	5
8047	default:	0	8047	default:	0
8048	llvm_unreachable("Unknown DWARF flavour");	0	8048	llvm_unreachable("Unknown DWARF flavour");	0
8049	case 0:	5	8049	case 0:	5
8050	mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	5	8050	mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);	5
8051	break;	5	8051	break;	5
8052	}	---	8052	}	---
8053	}	5	8053	}	5
8054		---	8054		---
8055	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };	---	8055	static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };	---
8056	static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	---	8056	static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	---
8057	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };	---	8057	static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };	---
8058	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	---	8058	static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };	---
8059	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };	---	8059	static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };	---
8060	static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };	---	8060	static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };	---
8061	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };	---	8061	static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };	---
8062	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };	---	8062	static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };	---
8063	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };	---	8063	static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };	---
8064	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };	---	8064	static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };	---
8065	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	---	8065	static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	---
8066	static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };	---	8066	static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };	---
8067	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	---	8067	static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };	---
8068	static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };	---	8068	static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };	---
8069	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---	8069	static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---
8070	static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---	8070	static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---
8071	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---	8071	static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---
8072	static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };	---	8072	static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };	---
8073	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---	8073	static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---
8074	static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---	8074	static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---
8075	static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---	8075	static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };	---
8076	static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---	8076	static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };	---
8077		---	8077		---
8078		---	8078		---
8079	ArrayRef MipsGenRegisterInfo::getRegMasks() const {	0	8079	ArrayRef MipsGenRegisterInfo::getRegMasks() const {	0
8080	static const uint32_t *const Masks[] = {	---	8080	static const uint32_t *const Masks[] = {	---
8081	CSR_Interrupt_32_RegMask,	---	8081	CSR_Interrupt_32_RegMask,	---
8082	CSR_Interrupt_32R6_RegMask,	---	8082	CSR_Interrupt_32R6_RegMask,	---
8083	CSR_Interrupt_64_RegMask,	---	8083	CSR_Interrupt_64_RegMask,	---
8084	CSR_Interrupt_64R6_RegMask,	---	8084	CSR_Interrupt_64R6_RegMask,	---
8085	CSR_Mips16RetHelper_RegMask,	---	8085	CSR_Mips16RetHelper_RegMask,	---
8086	CSR_N32_RegMask,	---	8086	CSR_N32_RegMask,	---
8087	CSR_N64_RegMask,	---	8087	CSR_N64_RegMask,	---
8088	CSR_O32_RegMask,	---	8088	CSR_O32_RegMask,	---
8089	CSR_O32_FP64_RegMask,	---	8089	CSR_O32_FP64_RegMask,	---
8090	CSR_O32_FPXX_RegMask,	---	8090	CSR_O32_FPXX_RegMask,	---
8091	CSR_SingleFloatOnly_RegMask,	---	8091	CSR_SingleFloatOnly_RegMask,	---
8092	};	---	8092	};	---
8093	return ArrayRef(Masks);	0	8093	return ArrayRef(Masks);	0
8094	}	---	8094	}	---
8095		---	8095		---
8096	bool MipsGenRegisterInfo::	0	8096	bool MipsGenRegisterInfo::	0
8097	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---	8097	isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---
8098	return	---	8098	return	---
8099	false;	0	8099	false;	0
8100	}	---	8100	}	---
8101		---	8101		---
8102	bool MipsGenRegisterInfo::	0	8102	bool MipsGenRegisterInfo::	0
8103	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---	8103	isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---
8104	return	---	8104	return	---
8105	false;	0	8105	false;	0
8106	}	---	8106	}	---
8107		---	8107		---
8108	bool MipsGenRegisterInfo::	0	8108	bool MipsGenRegisterInfo::	0
8109	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---	8109	isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {	---
8110	return	---	8110	return	---
8111	false;	0	8111	false;	0
8112	}	---	8112	}	---
8113		---	8113		---
8114	bool MipsGenRegisterInfo::	0	8114	bool MipsGenRegisterInfo::	0
8115	isConstantPhysReg(MCRegister PhysReg) const {	---	8115	isConstantPhysReg(MCRegister PhysReg) const {	---
8116	return	---	8116	return	---
8117	PhysReg == Mips::ZERO \|\|	0	8117	PhysReg == Mips::ZERO \|\|	0
8118	PhysReg == Mips::ZERO_64 \|\|	0	8118	PhysReg == Mips::ZERO_64 \|\|	0
8119	false;	0	8119	false;	0
8120	}	---	8120	}	---
8121		---	8121		---
8122	ArrayRef MipsGenRegisterInfo::getRegMaskNames() const {	0	8122	ArrayRef MipsGenRegisterInfo::getRegMaskNames() const {	0
8123	static const char *Names[] = {	---	8123	static const char *Names[] = {	---
8124	"CSR_Interrupt_32",	---	8124	"CSR_Interrupt_32",	---
8125	"CSR_Interrupt_32R6",	---	8125	"CSR_Interrupt_32R6",	---
8126	"CSR_Interrupt_64",	---	8126	"CSR_Interrupt_64",	---
8127	"CSR_Interrupt_64R6",	---	8127	"CSR_Interrupt_64R6",	---
8128	"CSR_Mips16RetHelper",	---	8128	"CSR_Mips16RetHelper",	---
8129	"CSR_N32",	---	8129	"CSR_N32",	---
8130	"CSR_N64",	---	8130	"CSR_N64",	---
8131	"CSR_O32",	---	8131	"CSR_O32",	---
8132	"CSR_O32_FP64",	---	8132	"CSR_O32_FP64",	---
8133	"CSR_O32_FPXX",	---	8133	"CSR_O32_FPXX",	---
8134	"CSR_SingleFloatOnly",	---	8134	"CSR_SingleFloatOnly",	---
8135	};	---	8135	};	---
8136	return ArrayRef(Names);	0	8136	return ArrayRef(Names);	0
8137	}	---	8137	}	---
8138		---	8138		---
8139	const MipsFrameLowering *	---	8139	const MipsFrameLowering *	---
8140	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {	0	8140	MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {	0
8141	return static_cast(	---	8141	return static_cast(	---
8142	MF.getSubtarget().getFrameLowering());	0	8142	MF.getSubtarget().getFrameLowering());	0
8143	}	---	8143	}	---
8144		---	8144		---
8145	} // end namespace llvm	---	8145	} // end namespace llvm	---
8146		---	8146		---
8147	#endif // GET_REGINFO_TARGET_DESC	---	8147	#endif // GET_REGINFO_TARGET_DESC	---
8148		---	8148		---
8149		---	8149		---